1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
19 #include "MipsSubtarget.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
26 // Start the numbering from where ISD NodeType finishes.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 // Jump and link (call)
32 // Get the Higher 16 bits from a 32-bit immediate
33 // No relation with Mips Hi register
36 // Get the Lower 16 bits from a 32-bit immediate
37 // No relation with Mips Lo register
40 // Handle gp_rel (small data/bss sections) relocation.
46 // Floating Point Branch Conditional
49 // Floating Point Compare
52 // Floating Point Conditional Moves
56 // Floating Point Rounding
84 // EXTR.W instrinsic nodes.
94 // DPA.W intrinsic nodes.
125 // Load/Store Left/Right nodes.
126 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
137 //===--------------------------------------------------------------------===//
138 // TargetLowering Implementation
139 //===--------------------------------------------------------------------===//
141 class MipsTargetLowering : public TargetLowering {
143 explicit MipsTargetLowering(MipsTargetMachine &TM);
145 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
147 virtual bool allowsUnalignedMemoryAccesses (EVT VT) const;
149 /// LowerOperation - Provide custom lowering hooks for some operations.
150 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
152 /// getTargetNodeName - This method returns the name of a target specific
154 virtual const char *getTargetNodeName(unsigned Opcode) const;
156 /// getSetCCResultType - get the ISD::SETCC result ValueType
157 EVT getSetCCResultType(EVT VT) const;
159 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
162 const MipsSubtarget *Subtarget;
164 bool HasMips64, IsN64, IsO32;
166 // Lower Operand helpers
167 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
168 CallingConv::ID CallConv, bool isVarArg,
169 const SmallVectorImpl<ISD::InputArg> &Ins,
170 DebugLoc dl, SelectionDAG &DAG,
171 SmallVectorImpl<SDValue> &InVals) const;
173 // Lower Operand specifics
174 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
175 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
176 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
177 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
178 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
179 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
180 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
181 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
182 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
183 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
184 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
185 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
186 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
187 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
188 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
189 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
190 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
191 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
193 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
194 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
197 LowerFormalArguments(SDValue Chain,
198 CallingConv::ID CallConv, bool isVarArg,
199 const SmallVectorImpl<ISD::InputArg> &Ins,
200 DebugLoc dl, SelectionDAG &DAG,
201 SmallVectorImpl<SDValue> &InVals) const;
204 LowerCall(TargetLowering::CallLoweringInfo &CLI,
205 SmallVectorImpl<SDValue> &InVals) const;
208 LowerReturn(SDValue Chain,
209 CallingConv::ID CallConv, bool isVarArg,
210 const SmallVectorImpl<ISD::OutputArg> &Outs,
211 const SmallVectorImpl<SDValue> &OutVals,
212 DebugLoc dl, SelectionDAG &DAG) const;
214 virtual MachineBasicBlock *
215 EmitInstrWithCustomInserter(MachineInstr *MI,
216 MachineBasicBlock *MBB) const;
218 // Inline asm support
219 ConstraintType getConstraintType(const std::string &Constraint) const;
221 /// Examine constraint string and operand type and determine a weight value.
222 /// The operand object must already have been set up with the operand type.
223 ConstraintWeight getSingleConstraintMatchWeight(
224 AsmOperandInfo &info, const char *constraint) const;
226 std::pair<unsigned, const TargetRegisterClass*>
227 getRegForInlineAsmConstraint(const std::string &Constraint,
230 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
231 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
232 /// true it means one of the asm constraint of the inline asm instruction
233 /// being processed is 'm'.
234 virtual void LowerAsmOperandForConstraint(SDValue Op,
235 std::string &Constraint,
236 std::vector<SDValue> &Ops,
237 SelectionDAG &DAG) const;
239 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
241 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
242 unsigned SrcAlign, bool IsZeroVal,
244 MachineFunction &MF) const;
246 /// isFPImmLegal - Returns true if the target can instruction select the
247 /// specified FP immediate natively. If false, the legalizer will
248 /// materialize the FP immediate as a load from a constant pool.
249 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
251 virtual unsigned getJumpTableEncoding() const;
253 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
254 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
255 MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI,
256 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
257 bool Nand = false) const;
258 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
259 MachineBasicBlock *BB, unsigned Size) const;
260 MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI,
261 MachineBasicBlock *BB, unsigned Size) const;
265 #endif // MipsISELLOWERING_H