1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
19 #include "MipsSubtarget.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
26 // Start the numbering from where ISD NodeType finishes.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 // Jump and link (call)
35 // Get the Higher 16 bits from a 32-bit immediate
36 // No relation with Mips Hi register
39 // Get the Lower 16 bits from a 32-bit immediate
40 // No relation with Mips Lo register
43 // Handle gp_rel (small data/bss sections) relocation.
49 // Floating Point Branch Conditional
52 // Floating Point Compare
55 // Floating Point Conditional Moves
59 // Floating Point Rounding
87 // EXTR.W instrinsic nodes.
97 // DPA.W intrinsic nodes.
128 // Load/Store Left/Right nodes.
129 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
140 //===--------------------------------------------------------------------===//
141 // TargetLowering Implementation
142 //===--------------------------------------------------------------------===//
144 class MipsTargetLowering : public TargetLowering {
146 explicit MipsTargetLowering(MipsTargetMachine &TM);
148 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
150 virtual bool allowsUnalignedMemoryAccesses (EVT VT) const;
152 virtual void LowerOperationWrapper(SDNode *N,
153 SmallVectorImpl<SDValue> &Results,
154 SelectionDAG &DAG) const;
156 /// LowerOperation - Provide custom lowering hooks for some operations.
157 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
159 /// ReplaceNodeResults - Replace the results of node with an illegal result
160 /// type with new values built out of custom code.
162 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
163 SelectionDAG &DAG) const;
165 /// getTargetNodeName - This method returns the name of a target specific
167 virtual const char *getTargetNodeName(unsigned Opcode) const;
169 /// getSetCCResultType - get the ISD::SETCC result ValueType
170 EVT getSetCCResultType(EVT VT) const;
172 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
175 const MipsSubtarget *Subtarget;
177 bool HasMips64, IsN64, IsO32;
179 // Lower Operand helpers
180 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
181 CallingConv::ID CallConv, bool isVarArg,
182 const SmallVectorImpl<ISD::InputArg> &Ins,
183 DebugLoc dl, SelectionDAG &DAG,
184 SmallVectorImpl<SDValue> &InVals) const;
186 // Lower Operand specifics
187 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
188 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
189 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
190 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
191 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
192 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
193 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
194 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
195 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
196 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
197 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
198 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
199 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
200 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
201 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
202 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
203 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
204 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
206 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
207 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
208 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
209 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
211 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
212 /// for tail call optimization.
213 bool IsEligibleForTailCallOptimization(CallingConv::ID CalleeCC,
214 unsigned NextStackOffset) const;
217 LowerFormalArguments(SDValue Chain,
218 CallingConv::ID CallConv, bool isVarArg,
219 const SmallVectorImpl<ISD::InputArg> &Ins,
220 DebugLoc dl, SelectionDAG &DAG,
221 SmallVectorImpl<SDValue> &InVals) const;
224 LowerCall(TargetLowering::CallLoweringInfo &CLI,
225 SmallVectorImpl<SDValue> &InVals) const;
228 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
230 const SmallVectorImpl<ISD::OutputArg> &Outs,
231 LLVMContext &Context) const;
234 LowerReturn(SDValue Chain,
235 CallingConv::ID CallConv, bool isVarArg,
236 const SmallVectorImpl<ISD::OutputArg> &Outs,
237 const SmallVectorImpl<SDValue> &OutVals,
238 DebugLoc dl, SelectionDAG &DAG) const;
240 virtual MachineBasicBlock *
241 EmitInstrWithCustomInserter(MachineInstr *MI,
242 MachineBasicBlock *MBB) const;
244 // Inline asm support
245 ConstraintType getConstraintType(const std::string &Constraint) const;
247 /// Examine constraint string and operand type and determine a weight value.
248 /// The operand object must already have been set up with the operand type.
249 ConstraintWeight getSingleConstraintMatchWeight(
250 AsmOperandInfo &info, const char *constraint) const;
252 std::pair<unsigned, const TargetRegisterClass*>
253 getRegForInlineAsmConstraint(const std::string &Constraint,
256 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
257 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
258 /// true it means one of the asm constraint of the inline asm instruction
259 /// being processed is 'm'.
260 virtual void LowerAsmOperandForConstraint(SDValue Op,
261 std::string &Constraint,
262 std::vector<SDValue> &Ops,
263 SelectionDAG &DAG) const;
265 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
267 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
268 unsigned SrcAlign, bool IsZeroVal,
270 MachineFunction &MF) const;
272 /// isFPImmLegal - Returns true if the target can instruction select the
273 /// specified FP immediate natively. If false, the legalizer will
274 /// materialize the FP immediate as a load from a constant pool.
275 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
277 virtual unsigned getJumpTableEncoding() const;
279 MachineBasicBlock *EmitBPOSGE32(MachineInstr *MI,
280 MachineBasicBlock *BB) const;
281 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
282 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
283 MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI,
284 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
285 bool Nand = false) const;
286 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
287 MachineBasicBlock *BB, unsigned Size) const;
288 MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI,
289 MachineBasicBlock *BB, unsigned Size) const;
293 #endif // MipsISELLOWERING_H