1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Bruno Cardoso Lopes and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
17 #include "MipsISelLowering.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsTargetMachine.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/SelectionDAGISel.h"
29 #include "llvm/CodeGen/SSARegMap.h"
30 #include "llvm/CodeGen/ValueTypes.h"
31 #include "llvm/Support/Debug.h"
37 const char *MipsTargetLowering::
38 getTargetNodeName(unsigned Opcode) const
42 case MipsISD::JmpLink : return "MipsISD::JmpLink";
43 case MipsISD::Hi : return "MipsISD::Hi";
44 case MipsISD::Lo : return "MipsISD::Lo";
45 case MipsISD::Ret : return "MipsISD::Ret";
46 case MipsISD::Add : return "MipsISD::Add";
47 default : return NULL;
52 MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
54 // Mips does not have i1 type, so use i32 for
55 // setcc operations results (slt, sgt, ...).
56 setSetCCResultType(MVT::i32);
57 setSetCCResultContents(ZeroOrOneSetCCResult);
59 // Set up the register classes
60 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
63 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
64 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
65 setOperationAction(ISD::RET, MVT::Other, Custom);
67 // Load extented operations for i1 types must be promoted
68 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
69 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
70 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
72 // Store operations for i1 types must be promoted
73 setStoreXAction(MVT::i1, Promote);
75 // Mips does not have these NodeTypes below.
76 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
77 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
78 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
79 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
80 setOperationAction(ISD::SELECT, MVT::i32, Expand);
81 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
83 // Mips not supported intrinsics.
84 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
85 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
86 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
88 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
89 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
90 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
91 setOperationAction(ISD::ROTL , MVT::i32, Expand);
92 setOperationAction(ISD::ROTR , MVT::i32, Expand);
93 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
95 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
96 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
97 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
99 // We don't have line number support yet.
100 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
101 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
102 setOperationAction(ISD::LABEL, MVT::Other, Expand);
104 // Use the default for now
105 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
106 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
108 setStackPointerRegisterToSaveRestore(Mips::SP);
109 computeRegisterProperties();
113 SDOperand MipsTargetLowering::
114 LowerOperation(SDOperand Op, SelectionDAG &DAG)
116 switch (Op.getOpcode())
118 case ISD::CALL: return LowerCALL(Op, DAG);
119 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
120 case ISD::RET: return LowerRET(Op, DAG);
121 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
122 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
127 //===----------------------------------------------------------------------===//
128 // Lower helper functions
129 //===----------------------------------------------------------------------===//
131 // AddLiveIn - This helper function adds the specified physical register to the
132 // MachineFunction as a live in value. It also creates a corresponding
133 // virtual register for it.
135 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
137 assert(RC->contains(PReg) && "Not the correct regclass!");
138 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
139 MF.addLiveIn(PReg, VReg);
143 //===----------------------------------------------------------------------===//
144 // Misc Lower Operation implementation
145 //===----------------------------------------------------------------------===//
146 SDOperand MipsTargetLowering::
147 LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG)
149 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
151 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
153 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::i32, MVT::Flag);
154 SDOperand Ops[] = { GA };
156 SDOperand Hi = DAG.getNode(MipsISD::Hi, VTs, 2, Ops, 1);
157 SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
159 SDOperand InFlag = Hi.getValue(1);
160 return DAG.getNode(MipsISD::Add, MVT::i32, Lo, Hi, InFlag);
163 SDOperand MipsTargetLowering::
164 LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG)
166 assert(0 && "TLS not implemented for MIPS.");
169 //===----------------------------------------------------------------------===//
170 // Calling Convention Implementation
172 // The lower operations present on calling convention works on this order:
173 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
174 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
175 // LowerRET (virt regs --> phys regs)
176 // LowerCALL (phys regs --> virt regs)
178 //===----------------------------------------------------------------------===//
180 #include "MipsGenCallingConv.inc"
182 //===----------------------------------------------------------------------===//
183 // CALL Calling Convention Implementation
184 //===----------------------------------------------------------------------===//
186 /// Mips custom CALL implementation
187 SDOperand MipsTargetLowering::
188 LowerCALL(SDOperand Op, SelectionDAG &DAG)
190 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
192 // By now, only CallingConv::C implemented
196 assert(0 && "Unsupported calling convention");
197 case CallingConv::Fast:
199 return LowerCCCCallTo(Op, DAG, CallingConv);
203 /// LowerCCCCallTo - functions arguments are copied from virtual
204 /// regs to (physical regs)/(stack frame), CALLSEQ_START and
205 /// CALLSEQ_END are emitted.
206 /// TODO: isVarArg, isTailCall, sret, GOT, linkage types.
207 SDOperand MipsTargetLowering::
208 LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
210 MachineFunction &MF = DAG.getMachineFunction();
211 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
213 SDOperand Chain = Op.getOperand(0);
214 SDOperand Callee = Op.getOperand(4);
215 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
217 MachineFrameInfo *MFI = MF.getFrameInfo();
219 // Analyze operands of the call, assigning locations to each operand.
220 SmallVector<CCValAssign, 16> ArgLocs;
221 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
223 // To meet ABI, Mips must always allocate 16 bytes on
224 // the stack (even if less than 4 are used as arguments)
225 int VTsize = MVT::getSizeInBits(MVT::i32)/8;
226 MFI->CreateFixedObject(VTsize, (VTsize*3));
228 CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips);
230 // Get a count of how many bytes are to be pushed on the stack.
231 unsigned NumBytes = CCInfo.getNextStackOffset();
232 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
235 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
236 SmallVector<SDOperand, 8> MemOpChains;
240 // Walk the register/memloc assignments, inserting copies/loads.
241 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
242 CCValAssign &VA = ArgLocs[i];
244 // Arguments start after the 5 first operands of ISD::CALL
245 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
247 // Promote the value if needed.
248 switch (VA.getLocInfo()) {
249 default: assert(0 && "Unknown loc info!");
250 case CCValAssign::Full: break;
251 case CCValAssign::SExt:
252 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
254 case CCValAssign::ZExt:
255 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
257 case CCValAssign::AExt:
258 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
262 // Arguments that can be passed on register,
263 // must be kept at RegsToPass vector
265 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
268 assert(VA.isMemLoc());
270 if (StackPtr.Val == 0)
271 StackPtr = DAG.getRegister(StackReg, getPointerTy());
273 // Create the frame index object for this incoming parameter
274 // This guarantees that when allocating Local Area the firsts
275 // 16 bytes which are alwayes reserved won't be overwritten.
276 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
277 (16 + VA.getLocMemOffset()));
279 SDOperand PtrOff = DAG.getFrameIndex(FI,getPointerTy());
281 // emit ISD::STORE whichs stores the
282 // parameter value to a stack Location
283 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
287 // Transform all store nodes into one single node because
288 // all store nodes are independent of each other.
289 if (!MemOpChains.empty())
290 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
291 &MemOpChains[0], MemOpChains.size());
293 // Build a sequence of copy-to-reg nodes chained together with token
294 // chain and flag operands which copy the outgoing args into registers.
295 // The InFlag in necessary since all emited instructions must be
298 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
299 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first,
300 RegsToPass[i].second, InFlag);
301 InFlag = Chain.getValue(1);
304 // If the callee is a GlobalAddress node (quite common, every direct
305 // call is) turn it into a TargetGlobalAddress node so that legalize
307 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
308 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
310 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
311 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
313 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
314 // = Chain, Callee, Reg#1, Reg#2, ...
316 // Returns a chain & a flag for retval copy to use.
317 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
318 SmallVector<SDOperand, 8> Ops;
319 Ops.push_back(Chain);
320 Ops.push_back(Callee);
322 // Add argument registers to the end of the list so that they are
323 // known live into the call.
324 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
325 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
326 RegsToPass[i].second.getValueType()));
329 Ops.push_back(InFlag);
331 Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size());
332 InFlag = Chain.getValue(1);
334 // Create the CALLSEQ_END node.
335 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
337 Ops.push_back(Chain);
338 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
339 Ops.push_back(InFlag);
340 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
341 InFlag = Chain.getValue(1);
343 // Handle result values, copying them out of physregs into vregs that we
345 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
348 /// LowerCallResult - Lower the result values of an ISD::CALL into the
349 /// appropriate copies out of appropriate physical registers. This assumes that
350 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
351 /// being lowered. Returns a SDNode with the same number of values as the
353 SDNode *MipsTargetLowering::
354 LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
355 unsigned CallingConv, SelectionDAG &DAG) {
357 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
359 // Assign locations to each value returned by this call.
360 SmallVector<CCValAssign, 16> RVLocs;
361 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
363 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
364 SmallVector<SDOperand, 8> ResultVals;
366 // Copy all of the result registers out of their specified physreg.
367 for (unsigned i = 0; i != RVLocs.size(); ++i) {
368 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
369 RVLocs[i].getValVT(), InFlag).getValue(1);
370 InFlag = Chain.getValue(2);
371 ResultVals.push_back(Chain.getValue(0));
374 // Merge everything together with a MERGE_VALUES node.
375 ResultVals.push_back(Chain);
376 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
377 &ResultVals[0], ResultVals.size()).Val;
380 //===----------------------------------------------------------------------===//
381 // FORMAL_ARGUMENTS Calling Convention Implementation
382 //===----------------------------------------------------------------------===//
384 /// Mips custom FORMAL_ARGUMENTS implementation
385 SDOperand MipsTargetLowering::
386 LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG)
388 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
392 assert(0 && "Unsupported calling convention");
394 return LowerCCCArguments(Op, DAG);
398 /// LowerCCCArguments - transform physical registers into
399 /// virtual registers and generate load operations for
400 /// arguments places on the stack.
401 /// TODO: isVarArg, sret
402 SDOperand MipsTargetLowering::
403 LowerCCCArguments(SDOperand Op, SelectionDAG &DAG)
405 SDOperand Root = Op.getOperand(0);
406 MachineFunction &MF = DAG.getMachineFunction();
407 MachineFrameInfo *MFI = MF.getFrameInfo();
408 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
410 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
411 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
413 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
415 // Assign locations to all of the incoming arguments.
416 SmallVector<CCValAssign, 16> ArgLocs;
417 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
419 CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips);
420 SmallVector<SDOperand, 8> ArgValues;
423 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
425 CCValAssign &VA = ArgLocs[i];
427 // Arguments stored on registers
429 MVT::ValueType RegVT = VA.getLocVT();
430 TargetRegisterClass *RC;
432 if (RegVT == MVT::i32)
433 RC = Mips::CPURegsRegisterClass;
435 assert(0 && "support only Mips::CPURegsRegisterClass");
437 // Transform the arguments stored on
438 // physical registers into virtual ones
439 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
440 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
442 // If this is an 8 or 16-bit value, it is really passed promoted
443 // to 32 bits. Insert an assert[sz]ext to capture this, then
444 // truncate to the right size.
445 if (VA.getLocInfo() == CCValAssign::SExt)
446 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
447 DAG.getValueType(VA.getValVT()));
448 else if (VA.getLocInfo() == CCValAssign::ZExt)
449 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
450 DAG.getValueType(VA.getValVT()));
452 if (VA.getLocInfo() != CCValAssign::Full)
453 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
455 ArgValues.push_back(ArgValue);
457 // To meet ABI, when VARARGS are passed on registers, the registers
458 // must have their values written to the caller stack frame.
461 if (StackPtr.Val == 0)
462 StackPtr = DAG.getRegister(StackReg, getPointerTy());
464 // The stack pointer offset is relative to the caller stack frame.
465 // Since the real stack size is unknown here, a negative SPOffset
466 // is used so there's a way to adjust these offsets when the stack
467 // size get known (on EliminateFrameIndex). A dummy SPOffset is
468 // used instead of a direct negative address (which is recorded to
469 // be used on emitPrologue) to avoid mis-calc of the first stack
470 // offset on PEI::calculateFrameObjectOffsets.
471 // Arguments are always 32-bit.
472 int FI = MFI->CreateFixedObject(4, 0);
473 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
474 SDOperand PtrOff = DAG.getFrameIndex(FI, getPointerTy());
476 // emit ISD::STORE whichs stores the
477 // parameter value to a stack Location
478 ArgValues.push_back(DAG.getStore(Root, ArgValue, PtrOff, NULL, 0));
483 assert(VA.isMemLoc());
485 // The stack pointer offset is relative to the caller stack frame.
486 // Since the real stack size is unknown here, a negative SPOffset
487 // is used so there's a way to adjust these offsets when the stack
488 // size get known (on EliminateFrameIndex). A dummy SPOffset is
489 // used instead of a direct negative address (which is recorded to
490 // be used on emitPrologue) to avoid mis-calc of the first stack
491 // offset on PEI::calculateFrameObjectOffsets.
492 // Arguments are always 32-bit.
493 int FI = MFI->CreateFixedObject(4, 0);
494 MipsFI->recordLoadArgsFI(FI, -(4+(16+VA.getLocMemOffset())));
496 // Create load nodes to retrieve arguments from the stack
497 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
498 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
501 ArgValues.push_back(Root);
503 // Return the new list of results.
504 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
505 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
508 //===----------------------------------------------------------------------===//
509 // Return Value Calling Convention Implementation
510 //===----------------------------------------------------------------------===//
512 SDOperand MipsTargetLowering::
513 LowerRET(SDOperand Op, SelectionDAG &DAG)
515 // CCValAssign - represent the assignment of
516 // the return value to a location
517 SmallVector<CCValAssign, 16> RVLocs;
518 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
519 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
521 // CCState - Info about the registers and stack slot.
522 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
524 // Analize return values of ISD::RET
525 CCInfo.AnalyzeReturn(Op.Val, RetCC_Mips);
527 // If this is the first return lowered for this function, add
528 // the regs to the liveout set for the function.
529 if (DAG.getMachineFunction().liveout_empty()) {
530 for (unsigned i = 0; i != RVLocs.size(); ++i)
531 if (RVLocs[i].isRegLoc())
532 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg());
535 // The chain is always operand #0
536 SDOperand Chain = Op.getOperand(0);
539 // Copy the result values into the output registers.
540 for (unsigned i = 0; i != RVLocs.size(); ++i) {
541 CCValAssign &VA = RVLocs[i];
542 assert(VA.isRegLoc() && "Can only return in registers!");
544 // ISD::RET => ret chain, (regnum1,val1), ...
545 // So i*2+1 index only the regnums
546 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(),
547 Op.getOperand(i*2+1), Flag);
549 // guarantee that all emitted copies are
550 // stuck together, avoiding something bad
551 Flag = Chain.getValue(1);
554 // Return on Mips is always a "jr $ra"
556 return DAG.getNode(MipsISD::Ret, MVT::Other,
557 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
559 return DAG.getNode(MipsISD::Ret, MVT::Other,
560 Chain, DAG.getRegister(Mips::RA, MVT::i32));
563 //===----------------------------------------------------------------------===//
564 // Mips Inline Assembly Support
565 //===----------------------------------------------------------------------===//
567 /// getConstraintType - Given a constraint letter, return the type of
568 /// constraint it is for this target.
569 MipsTargetLowering::ConstraintType MipsTargetLowering::
570 getConstraintType(const std::string &Constraint) const
572 if (Constraint.size() == 1) {
573 // Mips specific constrainy
574 // GCC config/mips/constraints.md
576 // 'd' : An address register. Equivalent to r
577 // unless generating MIPS16 code.
578 // 'y' : Equivalent to r; retained for
579 // backwards compatibility.
581 switch (Constraint[0]) {
585 return C_RegisterClass;
589 return TargetLowering::getConstraintType(Constraint);
592 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
593 getRegForInlineAsmConstraint(const std::string &Constraint,
594 MVT::ValueType VT) const
596 if (Constraint.size() == 1) {
597 switch (Constraint[0]) {
599 return std::make_pair(0U, Mips::CPURegsRegisterClass);
603 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
606 std::vector<unsigned> MipsTargetLowering::
607 getRegClassForInlineAsmConstraint(const std::string &Constraint,
608 MVT::ValueType VT) const
610 if (Constraint.size() != 1)
611 return std::vector<unsigned>();
613 switch (Constraint[0]) {
616 // GCC Mips Constraint Letters
619 return make_vector<unsigned>(Mips::V0, Mips::V1, Mips::A0,
620 Mips::A1, Mips::A2, Mips::A3,
621 Mips::T0, Mips::T1, Mips::T2,
622 Mips::T3, Mips::T4, Mips::T5,
623 Mips::T6, Mips::T7, Mips::S0,
624 Mips::S1, Mips::S2, Mips::S3,
625 Mips::S4, Mips::S5, Mips::S6,
626 Mips::S7, Mips::T8, Mips::T9, 0);
629 return std::vector<unsigned>();