1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
17 #include "MipsISelLowering.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsTargetMachine.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Target/TargetLoweringObjectFile.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
38 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
40 case MipsISD::JmpLink : return "MipsISD::JmpLink";
41 case MipsISD::Hi : return "MipsISD::Hi";
42 case MipsISD::Lo : return "MipsISD::Lo";
43 case MipsISD::GPRel : return "MipsISD::GPRel";
44 case MipsISD::Ret : return "MipsISD::Ret";
45 case MipsISD::CMov : return "MipsISD::CMov";
46 case MipsISD::SelectCC : return "MipsISD::SelectCC";
47 case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC";
48 case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
49 case MipsISD::FPCmp : return "MipsISD::FPCmp";
50 case MipsISD::FPRound : return "MipsISD::FPRound";
51 default : return NULL;
56 MipsTargetLowering(MipsTargetMachine &TM)
57 : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
58 Subtarget = &TM.getSubtarget<MipsSubtarget>();
60 // Mips does not have i1 type, so use i32 for
61 // setcc operations results (slt, sgt, ...).
62 setBooleanContents(ZeroOrOneBooleanContent);
64 // JumpTable targets must use GOT when using PIC_
65 setUsesGlobalOffsetTable(true);
67 // Set up the register classes
68 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
69 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
71 // When dealing with single precision only, use libcalls
72 if (!Subtarget->isSingleFloat())
73 if (!Subtarget->isFP64bit())
74 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
77 addLegalFPImmediate(APFloat(+0.0f));
79 // Load extented operations for i1 types must be promoted
80 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
81 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
82 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
84 // MIPS doesn't have extending float->double load/store
85 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
86 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
88 // Used by legalize types to correctly generate the setcc result.
89 // Without this, every float setcc comes with a AND/OR with the result,
90 // we don't want this, since the fpcmp result goes to a flag register,
91 // which is used implicitly by brcond and select operations.
92 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
94 // Mips Custom Operations
95 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
96 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
97 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
98 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
99 setOperationAction(ISD::SELECT, MVT::f32, Custom);
100 setOperationAction(ISD::SELECT, MVT::f64, Custom);
101 setOperationAction(ISD::SELECT, MVT::i32, Custom);
102 setOperationAction(ISD::SETCC, MVT::f32, Custom);
103 setOperationAction(ISD::SETCC, MVT::f64, Custom);
104 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
105 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
106 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
108 // We custom lower AND/OR to handle the case where the DAG contain 'ands/ors'
109 // with operands comming from setcc fp comparions. This is necessary since
110 // the result from these setcc are in a flag registers (FCR31).
111 setOperationAction(ISD::AND, MVT::i32, Custom);
112 setOperationAction(ISD::OR, MVT::i32, Custom);
114 // Operations not directly supported by Mips.
115 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
116 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
117 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
118 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
119 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
120 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
121 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
122 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
123 setOperationAction(ISD::ROTL, MVT::i32, Expand);
124 setOperationAction(ISD::ROTR, MVT::i32, Expand);
125 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
126 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
127 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
128 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
129 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
130 setOperationAction(ISD::FSIN, MVT::f32, Expand);
131 setOperationAction(ISD::FCOS, MVT::f32, Expand);
132 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
133 setOperationAction(ISD::FPOW, MVT::f32, Expand);
134 setOperationAction(ISD::FLOG, MVT::f32, Expand);
135 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
136 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
137 setOperationAction(ISD::FEXP, MVT::f32, Expand);
139 // We don't have line number support yet.
140 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
141 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
142 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
143 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
145 // Use the default for now
146 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
147 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
148 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
150 if (Subtarget->isSingleFloat())
151 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
153 if (!Subtarget->hasSEInReg()) {
154 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
155 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
158 if (!Subtarget->hasBitCount())
159 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
161 if (!Subtarget->hasSwap())
162 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
164 setStackPointerRegisterToSaveRestore(Mips::SP);
165 computeRegisterProperties();
168 MVT::SimpleValueType MipsTargetLowering::getSetCCResultType(EVT VT) const {
172 /// getFunctionAlignment - Return the Log2 alignment of this function.
173 unsigned MipsTargetLowering::getFunctionAlignment(const Function *) const {
177 SDValue MipsTargetLowering::
178 LowerOperation(SDValue Op, SelectionDAG &DAG)
180 switch (Op.getOpcode())
182 case ISD::AND: return LowerANDOR(Op, DAG);
183 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
184 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
185 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
186 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
187 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
188 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
189 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
190 case ISD::OR: return LowerANDOR(Op, DAG);
191 case ISD::SELECT: return LowerSELECT(Op, DAG);
192 case ISD::SETCC: return LowerSETCC(Op, DAG);
197 //===----------------------------------------------------------------------===//
198 // Lower helper functions
199 //===----------------------------------------------------------------------===//
201 // AddLiveIn - This helper function adds the specified physical register to the
202 // MachineFunction as a live in value. It also creates a corresponding
203 // virtual register for it.
205 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
207 assert(RC->contains(PReg) && "Not the correct regclass!");
208 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
209 MF.getRegInfo().addLiveIn(PReg, VReg);
213 // A address must be loaded from a small section if its size is less than the
214 // small section size threshold. Data in this section must be addressed using
216 bool MipsTargetLowering::IsInSmallSection(unsigned Size) {
217 return (Size > 0 && (Size <= Subtarget->getSSectionThreshold()));
220 // Discover if this global address can be placed into small data/bss section.
221 bool MipsTargetLowering::IsGlobalInSmallSection(GlobalValue *GV)
223 const TargetData *TD = getTargetData();
224 const GlobalVariable *GVA = dyn_cast<GlobalVariable>(GV);
229 const Type *Ty = GV->getType()->getElementType();
230 unsigned Size = TD->getTypeAllocSize(Ty);
232 // if this is a internal constant string, there is a special
233 // section for it, but not in small data/bss.
234 if (GVA->hasInitializer() && GV->hasLocalLinkage()) {
235 Constant *C = GVA->getInitializer();
236 const ConstantArray *CVA = dyn_cast<ConstantArray>(C);
237 if (CVA && CVA->isCString())
241 return IsInSmallSection(Size);
244 // Get fp branch code (not opcode) from condition code.
245 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
246 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
247 return Mips::BRANCH_T;
249 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
250 return Mips::BRANCH_F;
252 return Mips::BRANCH_INVALID;
255 static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) {
258 llvm_unreachable("Unknown branch code");
259 case Mips::BRANCH_T : return Mips::BC1T;
260 case Mips::BRANCH_F : return Mips::BC1F;
261 case Mips::BRANCH_TL : return Mips::BC1TL;
262 case Mips::BRANCH_FL : return Mips::BC1FL;
266 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
268 default: llvm_unreachable("Unknown fp condition code!");
270 case ISD::SETOEQ: return Mips::FCOND_EQ;
271 case ISD::SETUNE: return Mips::FCOND_OGL;
273 case ISD::SETOLT: return Mips::FCOND_OLT;
275 case ISD::SETOGT: return Mips::FCOND_OGT;
277 case ISD::SETOLE: return Mips::FCOND_OLE;
279 case ISD::SETOGE: return Mips::FCOND_OGE;
280 case ISD::SETULT: return Mips::FCOND_ULT;
281 case ISD::SETULE: return Mips::FCOND_ULE;
282 case ISD::SETUGT: return Mips::FCOND_UGT;
283 case ISD::SETUGE: return Mips::FCOND_UGE;
284 case ISD::SETUO: return Mips::FCOND_UN;
285 case ISD::SETO: return Mips::FCOND_OR;
287 case ISD::SETONE: return Mips::FCOND_NEQ;
288 case ISD::SETUEQ: return Mips::FCOND_UEQ;
293 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
294 MachineBasicBlock *BB) const {
295 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
296 bool isFPCmp = false;
297 DebugLoc dl = MI->getDebugLoc();
299 switch (MI->getOpcode()) {
300 default: assert(false && "Unexpected instr type to insert");
301 case Mips::Select_FCC:
302 case Mips::Select_FCC_S32:
303 case Mips::Select_FCC_D32:
304 isFPCmp = true; // FALL THROUGH
305 case Mips::Select_CC:
306 case Mips::Select_CC_S32:
307 case Mips::Select_CC_D32: {
308 // To "insert" a SELECT_CC instruction, we actually have to insert the
309 // diamond control-flow pattern. The incoming instruction knows the
310 // destination vreg to set, the condition code register to branch on, the
311 // true/false values to select between, and a branch opcode to use.
312 const BasicBlock *LLVM_BB = BB->getBasicBlock();
313 MachineFunction::iterator It = BB;
320 // bNE r1, r0, copy1MBB
321 // fallthrough --> copy0MBB
322 MachineBasicBlock *thisMBB = BB;
323 MachineFunction *F = BB->getParent();
324 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
325 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
327 // Emit the right instruction according to the type of the operands compared
329 // Find the condiction code present in the setcc operation.
330 Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm();
331 // Get the branch opcode from the branch code.
332 unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC));
333 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
335 BuildMI(BB, dl, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
336 .addReg(Mips::ZERO).addMBB(sinkMBB);
338 F->insert(It, copy0MBB);
339 F->insert(It, sinkMBB);
340 // Update machine-CFG edges by first adding all successors of the current
341 // block to the new block which will contain the Phi node for the select.
342 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
343 e = BB->succ_end(); i != e; ++i)
344 sinkMBB->addSuccessor(*i);
345 // Next, remove all successors of the current block, and add the true
346 // and fallthrough blocks as its successors.
347 while(!BB->succ_empty())
348 BB->removeSuccessor(BB->succ_begin());
349 BB->addSuccessor(copy0MBB);
350 BB->addSuccessor(sinkMBB);
354 // # fallthrough to sinkMBB
357 // Update machine-CFG edges
358 BB->addSuccessor(sinkMBB);
361 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
364 BuildMI(BB, dl, TII->get(Mips::PHI), MI->getOperand(0).getReg())
365 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
366 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
368 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
374 //===----------------------------------------------------------------------===//
375 // Misc Lower Operation implementation
376 //===----------------------------------------------------------------------===//
378 SDValue MipsTargetLowering::
379 LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG)
381 if (!Subtarget->isMips1())
384 MachineFunction &MF = DAG.getMachineFunction();
385 unsigned CCReg = AddLiveIn(MF, Mips::FCR31, Mips::CCRRegisterClass);
387 SDValue Chain = DAG.getEntryNode();
388 DebugLoc dl = Op.getDebugLoc();
389 SDValue Src = Op.getOperand(0);
391 // Set the condition register
392 SDValue CondReg = DAG.getCopyFromReg(Chain, dl, CCReg, MVT::i32);
393 CondReg = DAG.getCopyToReg(Chain, dl, Mips::AT, CondReg);
394 CondReg = DAG.getCopyFromReg(CondReg, dl, Mips::AT, MVT::i32);
396 SDValue Cst = DAG.getConstant(3, MVT::i32);
397 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i32, CondReg, Cst);
398 Cst = DAG.getConstant(2, MVT::i32);
399 SDValue Xor = DAG.getNode(ISD::XOR, dl, MVT::i32, Or, Cst);
401 SDValue InFlag(0, 0);
402 CondReg = DAG.getCopyToReg(Chain, dl, Mips::FCR31, Xor, InFlag);
404 // Emit the round instruction and bit convert to integer
405 SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, MVT::f32,
406 Src, CondReg.getValue(1));
407 SDValue BitCvt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Trunc);
411 SDValue MipsTargetLowering::
412 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG)
414 SDValue Chain = Op.getOperand(0);
415 SDValue Size = Op.getOperand(1);
416 DebugLoc dl = Op.getDebugLoc();
418 // Get a reference from Mips stack pointer
419 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32);
421 // Subtract the dynamic size from the actual stack size to
422 // obtain the new stack size.
423 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
425 // The Sub result contains the new stack start address, so it
426 // must be placed in the stack pointer register.
427 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub);
429 // This node always has two return values: a new stack pointer
431 SDValue Ops[2] = { Sub, Chain };
432 return DAG.getMergeValues(Ops, 2, dl);
435 SDValue MipsTargetLowering::
436 LowerANDOR(SDValue Op, SelectionDAG &DAG)
438 SDValue LHS = Op.getOperand(0);
439 SDValue RHS = Op.getOperand(1);
440 DebugLoc dl = Op.getDebugLoc();
442 if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp)
445 SDValue True = DAG.getConstant(1, MVT::i32);
446 SDValue False = DAG.getConstant(0, MVT::i32);
448 SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
449 LHS, True, False, LHS.getOperand(2));
450 SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
451 RHS, True, False, RHS.getOperand(2));
453 return DAG.getNode(Op.getOpcode(), dl, MVT::i32, LSEL, RSEL);
456 SDValue MipsTargetLowering::
457 LowerBRCOND(SDValue Op, SelectionDAG &DAG)
459 // The first operand is the chain, the second is the condition, the third is
460 // the block to branch to if the condition is true.
461 SDValue Chain = Op.getOperand(0);
462 SDValue Dest = Op.getOperand(2);
463 DebugLoc dl = Op.getDebugLoc();
465 if (Op.getOperand(1).getOpcode() != MipsISD::FPCmp)
468 SDValue CondRes = Op.getOperand(1);
469 SDValue CCNode = CondRes.getOperand(2);
471 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
472 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
474 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
478 SDValue MipsTargetLowering::
479 LowerSETCC(SDValue Op, SelectionDAG &DAG)
481 // The operands to this are the left and right operands to compare (ops #0,
482 // and #1) and the condition code to compare them with (op #2) as a
484 SDValue LHS = Op.getOperand(0);
485 SDValue RHS = Op.getOperand(1);
486 DebugLoc dl = Op.getDebugLoc();
488 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
490 return DAG.getNode(MipsISD::FPCmp, dl, Op.getValueType(), LHS, RHS,
491 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
494 SDValue MipsTargetLowering::
495 LowerSELECT(SDValue Op, SelectionDAG &DAG)
497 SDValue Cond = Op.getOperand(0);
498 SDValue True = Op.getOperand(1);
499 SDValue False = Op.getOperand(2);
500 DebugLoc dl = Op.getDebugLoc();
502 // if the incomming condition comes from a integer compare, the select
503 // operation must be SelectCC or a conditional move if the subtarget
505 if (Cond.getOpcode() != MipsISD::FPCmp) {
506 if (Subtarget->hasCondMov() && !True.getValueType().isFloatingPoint())
508 return DAG.getNode(MipsISD::SelectCC, dl, True.getValueType(),
512 // if the incomming condition comes from fpcmp, the select
513 // operation must use FPSelectCC.
514 SDValue CCNode = Cond.getOperand(2);
515 return DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
516 Cond, True, False, CCNode);
519 SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
520 // FIXME there isn't actually debug info here
521 DebugLoc dl = Op.getDebugLoc();
522 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
523 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
525 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
526 SDVTList VTs = DAG.getVTList(MVT::i32);
528 // %gp_rel relocation
529 if (!isa<Function>(GV) && IsGlobalInSmallSection(GV)) {
530 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
531 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
532 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
534 // %hi/%lo relocation
535 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GA, 1);
536 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
537 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
539 } else { // Abicall relocations, TODO: make this cleaner.
540 SDValue ResNode = DAG.getLoad(MVT::i32, dl,
541 DAG.getEntryNode(), GA, NULL, 0);
542 // On functions and global targets not internal linked only
543 // a load from got/GP is necessary for PIC to work.
544 if (!GV->hasLocalLinkage() || isa<Function>(GV))
546 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
547 return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo);
550 llvm_unreachable("Dont know how to handle GlobalAddress");
554 SDValue MipsTargetLowering::
555 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
557 llvm_unreachable("TLS not implemented for MIPS.");
558 return SDValue(); // Not reached
561 SDValue MipsTargetLowering::
562 LowerJumpTable(SDValue Op, SelectionDAG &DAG)
566 // FIXME there isn't actually debug info here
567 DebugLoc dl = Op.getDebugLoc();
569 EVT PtrVT = Op.getValueType();
570 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
571 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
573 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
574 SDVTList VTs = DAG.getVTList(MVT::i32);
575 SDValue Ops[] = { JTI };
576 HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, Ops, 1);
577 } else // Emit Load from Global Pointer
578 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, NULL, 0);
580 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTI);
581 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
586 SDValue MipsTargetLowering::
587 LowerConstantPool(SDValue Op, SelectionDAG &DAG)
590 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
591 Constant *C = N->getConstVal();
592 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
593 // FIXME there isn't actually debug info here
594 DebugLoc dl = Op.getDebugLoc();
597 // FIXME: we should reference the constant pool using small data sections,
598 // but the asm printer currently doens't support this feature without
599 // hacking it. This feature should come soon so we can uncomment the
601 //if (IsInSmallSection(C->getType())) {
602 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
603 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
604 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
605 //} else { // %hi/%lo relocation
606 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CP);
607 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP);
608 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
614 //===----------------------------------------------------------------------===//
615 // Calling Convention Implementation
616 //===----------------------------------------------------------------------===//
618 #include "MipsGenCallingConv.inc"
620 //===----------------------------------------------------------------------===//
621 // TODO: Implement a generic logic using tblgen that can support this.
622 // Mips O32 ABI rules:
624 // i32 - Passed in A0, A1, A2, A3 and stack
625 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
626 // an argument. Otherwise, passed in A1, A2, A3 and stack.
627 // f64 - Only passed in two aliased f32 registers if no int reg has been used
628 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
629 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
631 //===----------------------------------------------------------------------===//
633 static bool CC_MipsO32(unsigned ValNo, EVT ValVT,
634 EVT LocVT, CCValAssign::LocInfo LocInfo,
635 ISD::ArgFlagsTy ArgFlags, CCState &State) {
637 static const unsigned IntRegsSize=4, FloatRegsSize=2;
639 static const unsigned IntRegs[] = {
640 Mips::A0, Mips::A1, Mips::A2, Mips::A3
642 static const unsigned F32Regs[] = {
645 static const unsigned F64Regs[] = {
650 unsigned UnallocIntReg = State.getFirstUnallocated(IntRegs, IntRegsSize);
651 bool IntRegUsed = (IntRegs[UnallocIntReg] != (unsigned (Mips::A0)));
653 // Promote i8 and i16
654 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
656 if (ArgFlags.isSExt())
657 LocInfo = CCValAssign::SExt;
658 else if (ArgFlags.isZExt())
659 LocInfo = CCValAssign::ZExt;
661 LocInfo = CCValAssign::AExt;
664 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && IntRegUsed)) {
665 Reg = State.AllocateReg(IntRegs, IntRegsSize);
670 if (ValVT.isFloatingPoint() && !IntRegUsed) {
671 if (ValVT == MVT::f32)
672 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
674 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
677 if (ValVT == MVT::f64 && IntRegUsed) {
678 if (UnallocIntReg != IntRegsSize) {
679 // If we hit register A3 as the first not allocated, we must
680 // mark it as allocated (shadow) and use the stack instead.
681 if (IntRegs[UnallocIntReg] != (unsigned (Mips::A3)))
683 for (;UnallocIntReg < IntRegsSize; ++UnallocIntReg)
684 State.AllocateReg(UnallocIntReg);
690 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
691 unsigned Offset = State.AllocateStack(SizeInBytes, SizeInBytes);
692 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
694 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
696 return false; // CC must always match
699 //===----------------------------------------------------------------------===//
700 // Call Calling Convention Implementation
701 //===----------------------------------------------------------------------===//
703 /// LowerCall - functions arguments are copied from virtual regs to
704 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
705 /// TODO: isVarArg, isTailCall.
707 MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
708 unsigned CallConv, bool isVarArg,
710 const SmallVectorImpl<ISD::OutputArg> &Outs,
711 const SmallVectorImpl<ISD::InputArg> &Ins,
712 DebugLoc dl, SelectionDAG &DAG,
713 SmallVectorImpl<SDValue> &InVals) {
715 MachineFunction &MF = DAG.getMachineFunction();
716 MachineFrameInfo *MFI = MF.getFrameInfo();
718 // Analyze operands of the call, assigning locations to each operand.
719 SmallVector<CCValAssign, 16> ArgLocs;
720 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
723 // To meet O32 ABI, Mips must always allocate 16 bytes on
724 // the stack (even if less than 4 are used as arguments)
725 if (Subtarget->isABI_O32()) {
726 int VTsize = EVT(MVT::i32).getSizeInBits()/8;
727 MFI->CreateFixedObject(VTsize, (VTsize*3));
728 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32);
730 CCInfo.AnalyzeCallOperands(Outs, CC_Mips);
732 // Get a count of how many bytes are to be pushed on the stack.
733 unsigned NumBytes = CCInfo.getNextStackOffset();
734 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
736 // With EABI is it possible to have 16 args on registers.
737 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
738 SmallVector<SDValue, 8> MemOpChains;
740 // First/LastArgStackLoc contains the first/last
741 // "at stack" argument location.
742 int LastArgStackLoc = 0;
743 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
745 // Walk the register/memloc assignments, inserting copies/loads.
746 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
747 SDValue Arg = Outs[i].Val;
748 CCValAssign &VA = ArgLocs[i];
750 // Promote the value if needed.
751 switch (VA.getLocInfo()) {
752 default: llvm_unreachable("Unknown loc info!");
753 case CCValAssign::Full:
754 if (Subtarget->isABI_O32() && VA.isRegLoc()) {
755 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
756 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Arg);
757 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
758 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
759 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
760 DAG.getConstant(0, getPointerTy()));
761 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
762 DAG.getConstant(1, getPointerTy()));
763 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
764 RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi));
769 case CCValAssign::SExt:
770 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
772 case CCValAssign::ZExt:
773 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
775 case CCValAssign::AExt:
776 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
780 // Arguments that can be passed on register must be kept at
783 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
787 // Register can't get to this point...
788 assert(VA.isMemLoc());
790 // Create the frame index object for this incoming parameter
791 // This guarantees that when allocating Local Area the firsts
792 // 16 bytes which are alwayes reserved won't be overwritten
793 // if O32 ABI is used. For EABI the first address is zero.
794 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
795 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
798 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
800 // emit ISD::STORE whichs stores the
801 // parameter value to a stack Location
802 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0));
805 // Transform all store nodes into one single node because all store
806 // nodes are independent of each other.
807 if (!MemOpChains.empty())
808 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
809 &MemOpChains[0], MemOpChains.size());
811 // Build a sequence of copy-to-reg nodes chained together with token
812 // chain and flag operands which copy the outgoing args into registers.
813 // The InFlag in necessary since all emited instructions must be
816 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
817 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
818 RegsToPass[i].second, InFlag);
819 InFlag = Chain.getValue(1);
822 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
823 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
824 // node so that legalize doesn't hack it.
825 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
826 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
827 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
828 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
830 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
831 // = Chain, Callee, Reg#1, Reg#2, ...
833 // Returns a chain & a flag for retval copy to use.
834 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
835 SmallVector<SDValue, 8> Ops;
836 Ops.push_back(Chain);
837 Ops.push_back(Callee);
839 // Add argument registers to the end of the list so that they are
840 // known live into the call.
841 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
842 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
843 RegsToPass[i].second.getValueType()));
845 if (InFlag.getNode())
846 Ops.push_back(InFlag);
848 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
849 InFlag = Chain.getValue(1);
851 // Create the CALLSEQ_END node.
852 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
853 DAG.getIntPtrConstant(0, true), InFlag);
854 InFlag = Chain.getValue(1);
856 // Create a stack location to hold GP when PIC is used. This stack
857 // location is used on function prologue to save GP and also after all
858 // emited CALL's to restore GP.
859 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
860 // Function can have an arbitrary number of calls, so
861 // hold the LastArgStackLoc with the biggest offset.
863 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
864 if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
865 LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
866 // Create the frame index only once. SPOffset here can be anything
867 // (this will be fixed on processFunctionBeforeFrameFinalized)
868 if (MipsFI->getGPStackOffset() == -1) {
869 FI = MFI->CreateFixedObject(4, 0);
872 MipsFI->setGPStackOffset(LastArgStackLoc);
876 FI = MipsFI->getGPFI();
877 SDValue FIN = DAG.getFrameIndex(FI,getPointerTy());
878 SDValue GPLoad = DAG.getLoad(MVT::i32, dl, Chain, FIN, NULL, 0);
879 Chain = GPLoad.getValue(1);
880 Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, MVT::i32),
881 GPLoad, SDValue(0,0));
882 InFlag = Chain.getValue(1);
885 // Handle result values, copying them out of physregs into vregs that we
887 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
888 Ins, dl, DAG, InVals);
891 /// LowerCallResult - Lower the result values of a call into the
892 /// appropriate copies out of appropriate physical registers.
894 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
895 unsigned CallConv, bool isVarArg,
896 const SmallVectorImpl<ISD::InputArg> &Ins,
897 DebugLoc dl, SelectionDAG &DAG,
898 SmallVectorImpl<SDValue> &InVals) {
900 // Assign locations to each value returned by this call.
901 SmallVector<CCValAssign, 16> RVLocs;
902 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
903 RVLocs, *DAG.getContext());
905 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
907 // Copy all of the result registers out of their specified physreg.
908 for (unsigned i = 0; i != RVLocs.size(); ++i) {
909 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
910 RVLocs[i].getValVT(), InFlag).getValue(1);
911 InFlag = Chain.getValue(2);
912 InVals.push_back(Chain.getValue(0));
918 //===----------------------------------------------------------------------===//
919 // Formal Arguments Calling Convention Implementation
920 //===----------------------------------------------------------------------===//
922 /// LowerFormalArguments - transform physical registers into
923 /// virtual registers and generate load operations for
924 /// arguments places on the stack.
927 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
928 unsigned CallConv, bool isVarArg,
929 const SmallVectorImpl<ISD::InputArg>
931 DebugLoc dl, SelectionDAG &DAG,
932 SmallVectorImpl<SDValue> &InVals) {
934 MachineFunction &MF = DAG.getMachineFunction();
935 MachineFrameInfo *MFI = MF.getFrameInfo();
936 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
938 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
940 // Assign locations to all of the incoming arguments.
941 SmallVector<CCValAssign, 16> ArgLocs;
942 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
943 ArgLocs, *DAG.getContext());
945 if (Subtarget->isABI_O32())
946 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32);
948 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips);
952 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
954 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
955 CCValAssign &VA = ArgLocs[i];
957 // Arguments stored on registers
959 EVT RegVT = VA.getLocVT();
960 TargetRegisterClass *RC = 0;
962 if (RegVT == MVT::i32)
963 RC = Mips::CPURegsRegisterClass;
964 else if (RegVT == MVT::f32)
965 RC = Mips::FGR32RegisterClass;
966 else if (RegVT == MVT::f64) {
967 if (!Subtarget->isSingleFloat())
968 RC = Mips::AFGR64RegisterClass;
970 llvm_unreachable("RegVT not supported by LowerFormalArguments Lowering");
972 // Transform the arguments stored on
973 // physical registers into virtual ones
974 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
975 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
977 // If this is an 8 or 16-bit value, it has been passed promoted
978 // to 32 bits. Insert an assert[sz]ext to capture this, then
979 // truncate to the right size.
980 if (VA.getLocInfo() != CCValAssign::Full) {
982 if (VA.getLocInfo() == CCValAssign::SExt)
983 Opcode = ISD::AssertSext;
984 else if (VA.getLocInfo() == CCValAssign::ZExt)
985 Opcode = ISD::AssertZext;
987 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
988 DAG.getValueType(VA.getValVT()));
989 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
992 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64
993 if (Subtarget->isABI_O32()) {
994 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32)
995 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
996 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) {
997 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
998 VA.getLocReg()+1, RC);
999 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
1000 SDValue Hi = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
1001 SDValue Lo = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue2);
1002 ArgValue = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::f64, Lo, Hi);
1006 InVals.push_back(ArgValue);
1008 // To meet ABI, when VARARGS are passed on registers, the registers
1009 // must have their values written to the caller stack frame.
1010 if ((isVarArg) && (Subtarget->isABI_O32())) {
1011 if (StackPtr.getNode() == 0)
1012 StackPtr = DAG.getRegister(StackReg, getPointerTy());
1014 // The stack pointer offset is relative to the caller stack frame.
1015 // Since the real stack size is unknown here, a negative SPOffset
1016 // is used so there's a way to adjust these offsets when the stack
1017 // size get known (on EliminateFrameIndex). A dummy SPOffset is
1018 // used instead of a direct negative address (which is recorded to
1019 // be used on emitPrologue) to avoid mis-calc of the first stack
1020 // offset on PEI::calculateFrameObjectOffsets.
1021 // Arguments are always 32-bit.
1022 int FI = MFI->CreateFixedObject(4, 0);
1023 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
1024 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
1026 // emit ISD::STORE whichs stores the
1027 // parameter value to a stack Location
1028 InVals.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, NULL, 0));
1031 } else { // VA.isRegLoc()
1034 assert(VA.isMemLoc());
1036 // The stack pointer offset is relative to the caller stack frame.
1037 // Since the real stack size is unknown here, a negative SPOffset
1038 // is used so there's a way to adjust these offsets when the stack
1039 // size get known (on EliminateFrameIndex). A dummy SPOffset is
1040 // used instead of a direct negative address (which is recorded to
1041 // be used on emitPrologue) to avoid mis-calc of the first stack
1042 // offset on PEI::calculateFrameObjectOffsets.
1043 // Arguments are always 32-bit.
1044 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1045 int FI = MFI->CreateFixedObject(ArgSize, 0);
1046 MipsFI->recordLoadArgsFI(FI, -(ArgSize+
1047 (FirstStackArgLoc + VA.getLocMemOffset())));
1049 // Create load nodes to retrieve arguments from the stack
1050 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1051 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0));
1055 // The mips ABIs for returning structs by value requires that we copy
1056 // the sret argument into $v0 for the return. Save the argument into
1057 // a virtual register so that we can access it from the return points.
1058 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1059 unsigned Reg = MipsFI->getSRetReturnReg();
1061 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
1062 MipsFI->setSRetReturnReg(Reg);
1064 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1065 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1071 //===----------------------------------------------------------------------===//
1072 // Return Value Calling Convention Implementation
1073 //===----------------------------------------------------------------------===//
1076 MipsTargetLowering::LowerReturn(SDValue Chain,
1077 unsigned CallConv, bool isVarArg,
1078 const SmallVectorImpl<ISD::OutputArg> &Outs,
1079 DebugLoc dl, SelectionDAG &DAG) {
1081 // CCValAssign - represent the assignment of
1082 // the return value to a location
1083 SmallVector<CCValAssign, 16> RVLocs;
1085 // CCState - Info about the registers and stack slot.
1086 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1087 RVLocs, *DAG.getContext());
1089 // Analize return values.
1090 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
1092 // If this is the first return lowered for this function, add
1093 // the regs to the liveout set for the function.
1094 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1095 for (unsigned i = 0; i != RVLocs.size(); ++i)
1096 if (RVLocs[i].isRegLoc())
1097 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1102 // Copy the result values into the output registers.
1103 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1104 CCValAssign &VA = RVLocs[i];
1105 assert(VA.isRegLoc() && "Can only return in registers!");
1107 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1110 // guarantee that all emitted copies are
1111 // stuck together, avoiding something bad
1112 Flag = Chain.getValue(1);
1115 // The mips ABIs for returning structs by value requires that we copy
1116 // the sret argument into $v0 for the return. We saved the argument into
1117 // a virtual register in the entry block, so now we copy the value out
1119 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1120 MachineFunction &MF = DAG.getMachineFunction();
1121 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1122 unsigned Reg = MipsFI->getSRetReturnReg();
1125 llvm_unreachable("sret virtual register not created in the entry block");
1126 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1128 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
1129 Flag = Chain.getValue(1);
1132 // Return on Mips is always a "jr $ra"
1134 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1135 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
1137 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1138 Chain, DAG.getRegister(Mips::RA, MVT::i32));
1141 //===----------------------------------------------------------------------===//
1142 // Mips Inline Assembly Support
1143 //===----------------------------------------------------------------------===//
1145 /// getConstraintType - Given a constraint letter, return the type of
1146 /// constraint it is for this target.
1147 MipsTargetLowering::ConstraintType MipsTargetLowering::
1148 getConstraintType(const std::string &Constraint) const
1150 // Mips specific constrainy
1151 // GCC config/mips/constraints.md
1153 // 'd' : An address register. Equivalent to r
1154 // unless generating MIPS16 code.
1155 // 'y' : Equivalent to r; retained for
1156 // backwards compatibility.
1157 // 'f' : Floating Point registers.
1158 if (Constraint.size() == 1) {
1159 switch (Constraint[0]) {
1164 return C_RegisterClass;
1168 return TargetLowering::getConstraintType(Constraint);
1171 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1172 /// return a list of registers that can be used to satisfy the constraint.
1173 /// This should only be used for C_RegisterClass constraints.
1174 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
1175 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
1177 if (Constraint.size() == 1) {
1178 switch (Constraint[0]) {
1180 return std::make_pair(0U, Mips::CPURegsRegisterClass);
1183 return std::make_pair(0U, Mips::FGR32RegisterClass);
1185 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1186 return std::make_pair(0U, Mips::AFGR64RegisterClass);
1189 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1192 /// Given a register class constraint, like 'r', if this corresponds directly
1193 /// to an LLVM register class, return a register of 0 and the register class
1195 std::vector<unsigned> MipsTargetLowering::
1196 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1199 if (Constraint.size() != 1)
1200 return std::vector<unsigned>();
1202 switch (Constraint[0]) {
1205 // GCC Mips Constraint Letters
1208 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
1209 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
1210 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
1214 if (VT == MVT::f32) {
1215 if (Subtarget->isSingleFloat())
1216 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
1217 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
1218 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
1219 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
1220 Mips::F30, Mips::F31, 0);
1222 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
1223 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
1224 Mips::F28, Mips::F30, 0);
1228 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1229 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
1230 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
1231 Mips::D14, Mips::D15, 0);
1233 return std::vector<unsigned>();
1237 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1238 // The Mips target isn't yet aware of offsets.