1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
17 #include "MipsISelLowering.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsTargetMachine.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
37 const char *MipsTargetLowering::
38 getTargetNodeName(unsigned Opcode) const
42 case MipsISD::JmpLink : return "MipsISD::JmpLink";
43 case MipsISD::Hi : return "MipsISD::Hi";
44 case MipsISD::Lo : return "MipsISD::Lo";
45 case MipsISD::GPRel : return "MipsISD::GPRel";
46 case MipsISD::Ret : return "MipsISD::Ret";
47 case MipsISD::CMov : return "MipsISD::CMov";
48 case MipsISD::SelectCC : return "MipsISD::SelectCC";
49 case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC";
50 case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
51 case MipsISD::FPCmp : return "MipsISD::FPCmp";
52 case MipsISD::FPRound : return "MipsISD::FPRound";
53 default : return NULL;
58 MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
60 Subtarget = &TM.getSubtarget<MipsSubtarget>();
62 // Mips does not have i1 type, so use i32 for
63 // setcc operations results (slt, sgt, ...).
64 setBooleanContents(ZeroOrOneBooleanContent);
66 // JumpTable targets must use GOT when using PIC_
67 setUsesGlobalOffsetTable(true);
69 // Set up the register classes
70 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
71 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
73 // When dealing with single precision only, use libcalls
74 if (!Subtarget->isSingleFloat())
75 if (!Subtarget->isFP64bit())
76 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
79 addLegalFPImmediate(APFloat(+0.0f));
81 // Load extented operations for i1 types must be promoted
82 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
83 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
84 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
86 // MIPS doesn't have extending float->double load/store
87 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
88 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
90 // Used by legalize types to correctly generate the setcc result.
91 // Without this, every float setcc comes with a AND/OR with the result,
92 // we don't want this, since the fpcmp result goes to a flag register,
93 // which is used implicitly by brcond and select operations.
94 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
96 // Mips Custom Operations
97 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
98 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
99 setOperationAction(ISD::RET, MVT::Other, Custom);
100 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
101 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
102 setOperationAction(ISD::SELECT, MVT::f32, Custom);
103 setOperationAction(ISD::SELECT, MVT::f64, Custom);
104 setOperationAction(ISD::SELECT, MVT::i32, Custom);
105 setOperationAction(ISD::SETCC, MVT::f32, Custom);
106 setOperationAction(ISD::SETCC, MVT::f64, Custom);
107 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
108 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
109 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
111 // We custom lower AND/OR to handle the case where the DAG contain 'ands/ors'
112 // with operands comming from setcc fp comparions. This is necessary since
113 // the result from these setcc are in a flag registers (FCR31).
114 setOperationAction(ISD::AND, MVT::i32, Custom);
115 setOperationAction(ISD::OR, MVT::i32, Custom);
117 // Operations not directly supported by Mips.
118 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
119 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
120 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
121 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
122 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
123 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
124 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
125 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
126 setOperationAction(ISD::ROTL, MVT::i32, Expand);
127 setOperationAction(ISD::ROTR, MVT::i32, Expand);
128 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
129 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
130 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
131 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
132 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
133 setOperationAction(ISD::FSIN, MVT::f32, Expand);
134 setOperationAction(ISD::FCOS, MVT::f32, Expand);
135 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
136 setOperationAction(ISD::FPOW, MVT::f32, Expand);
137 setOperationAction(ISD::FLOG, MVT::f32, Expand);
138 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
139 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
140 setOperationAction(ISD::FEXP, MVT::f32, Expand);
142 // We don't have line number support yet.
143 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
144 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
145 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
146 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
148 // Use the default for now
149 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
150 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
151 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
153 if (Subtarget->isSingleFloat())
154 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
156 if (!Subtarget->hasSEInReg()) {
157 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
158 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
161 if (!Subtarget->hasBitCount())
162 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
164 if (!Subtarget->hasSwap())
165 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
167 setStackPointerRegisterToSaveRestore(Mips::SP);
168 computeRegisterProperties();
171 MVT MipsTargetLowering::getSetCCResultType(MVT VT) const {
175 /// getFunctionAlignment - Return the Log2 alignment of this function.
176 unsigned MipsTargetLowering::getFunctionAlignment(const Function *) const {
180 SDValue MipsTargetLowering::
181 LowerOperation(SDValue Op, SelectionDAG &DAG)
183 switch (Op.getOpcode())
185 case ISD::AND: return LowerANDOR(Op, DAG);
186 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
187 case ISD::CALL: return LowerCALL(Op, DAG);
188 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
189 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
190 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
191 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
192 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
193 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
194 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
195 case ISD::OR: return LowerANDOR(Op, DAG);
196 case ISD::RET: return LowerRET(Op, DAG);
197 case ISD::SELECT: return LowerSELECT(Op, DAG);
198 case ISD::SETCC: return LowerSETCC(Op, DAG);
203 //===----------------------------------------------------------------------===//
204 // Lower helper functions
205 //===----------------------------------------------------------------------===//
207 // AddLiveIn - This helper function adds the specified physical register to the
208 // MachineFunction as a live in value. It also creates a corresponding
209 // virtual register for it.
211 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
213 assert(RC->contains(PReg) && "Not the correct regclass!");
214 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
215 MF.getRegInfo().addLiveIn(PReg, VReg);
219 // Get fp branch code (not opcode) from condition code.
220 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
221 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
222 return Mips::BRANCH_T;
224 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
225 return Mips::BRANCH_F;
227 return Mips::BRANCH_INVALID;
230 static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) {
233 llvm_unreachable("Unknown branch code");
234 case Mips::BRANCH_T : return Mips::BC1T;
235 case Mips::BRANCH_F : return Mips::BC1F;
236 case Mips::BRANCH_TL : return Mips::BC1TL;
237 case Mips::BRANCH_FL : return Mips::BC1FL;
241 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
243 default: llvm_unreachable("Unknown fp condition code!");
245 case ISD::SETOEQ: return Mips::FCOND_EQ;
246 case ISD::SETUNE: return Mips::FCOND_OGL;
248 case ISD::SETOLT: return Mips::FCOND_OLT;
250 case ISD::SETOGT: return Mips::FCOND_OGT;
252 case ISD::SETOLE: return Mips::FCOND_OLE;
254 case ISD::SETOGE: return Mips::FCOND_OGE;
255 case ISD::SETULT: return Mips::FCOND_ULT;
256 case ISD::SETULE: return Mips::FCOND_ULE;
257 case ISD::SETUGT: return Mips::FCOND_UGT;
258 case ISD::SETUGE: return Mips::FCOND_UGE;
259 case ISD::SETUO: return Mips::FCOND_UN;
260 case ISD::SETO: return Mips::FCOND_OR;
262 case ISD::SETONE: return Mips::FCOND_NEQ;
263 case ISD::SETUEQ: return Mips::FCOND_UEQ;
268 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
269 MachineBasicBlock *BB) const {
270 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
271 bool isFPCmp = false;
272 DebugLoc dl = MI->getDebugLoc();
274 switch (MI->getOpcode()) {
275 default: assert(false && "Unexpected instr type to insert");
276 case Mips::Select_FCC:
277 case Mips::Select_FCC_S32:
278 case Mips::Select_FCC_D32:
279 isFPCmp = true; // FALL THROUGH
280 case Mips::Select_CC:
281 case Mips::Select_CC_S32:
282 case Mips::Select_CC_D32: {
283 // To "insert" a SELECT_CC instruction, we actually have to insert the
284 // diamond control-flow pattern. The incoming instruction knows the
285 // destination vreg to set, the condition code register to branch on, the
286 // true/false values to select between, and a branch opcode to use.
287 const BasicBlock *LLVM_BB = BB->getBasicBlock();
288 MachineFunction::iterator It = BB;
295 // bNE r1, r0, copy1MBB
296 // fallthrough --> copy0MBB
297 MachineBasicBlock *thisMBB = BB;
298 MachineFunction *F = BB->getParent();
299 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
300 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
302 // Emit the right instruction according to the type of the operands compared
304 // Find the condiction code present in the setcc operation.
305 Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm();
306 // Get the branch opcode from the branch code.
307 unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC));
308 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
310 BuildMI(BB, dl, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
311 .addReg(Mips::ZERO).addMBB(sinkMBB);
313 F->insert(It, copy0MBB);
314 F->insert(It, sinkMBB);
315 // Update machine-CFG edges by first adding all successors of the current
316 // block to the new block which will contain the Phi node for the select.
317 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
318 e = BB->succ_end(); i != e; ++i)
319 sinkMBB->addSuccessor(*i);
320 // Next, remove all successors of the current block, and add the true
321 // and fallthrough blocks as its successors.
322 while(!BB->succ_empty())
323 BB->removeSuccessor(BB->succ_begin());
324 BB->addSuccessor(copy0MBB);
325 BB->addSuccessor(sinkMBB);
329 // # fallthrough to sinkMBB
332 // Update machine-CFG edges
333 BB->addSuccessor(sinkMBB);
336 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
339 BuildMI(BB, dl, TII->get(Mips::PHI), MI->getOperand(0).getReg())
340 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
341 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
343 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
349 //===----------------------------------------------------------------------===//
350 // Misc Lower Operation implementation
351 //===----------------------------------------------------------------------===//
353 SDValue MipsTargetLowering::
354 LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG)
356 if (!Subtarget->isMips1())
359 MachineFunction &MF = DAG.getMachineFunction();
360 unsigned CCReg = AddLiveIn(MF, Mips::FCR31, Mips::CCRRegisterClass);
362 SDValue Chain = DAG.getEntryNode();
363 DebugLoc dl = Op.getDebugLoc();
364 SDValue Src = Op.getOperand(0);
366 // Set the condition register
367 SDValue CondReg = DAG.getCopyFromReg(Chain, dl, CCReg, MVT::i32);
368 CondReg = DAG.getCopyToReg(Chain, dl, Mips::AT, CondReg);
369 CondReg = DAG.getCopyFromReg(CondReg, dl, Mips::AT, MVT::i32);
371 SDValue Cst = DAG.getConstant(3, MVT::i32);
372 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i32, CondReg, Cst);
373 Cst = DAG.getConstant(2, MVT::i32);
374 SDValue Xor = DAG.getNode(ISD::XOR, dl, MVT::i32, Or, Cst);
376 SDValue InFlag(0, 0);
377 CondReg = DAG.getCopyToReg(Chain, dl, Mips::FCR31, Xor, InFlag);
379 // Emit the round instruction and bit convert to integer
380 SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, MVT::f32,
381 Src, CondReg.getValue(1));
382 SDValue BitCvt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Trunc);
386 SDValue MipsTargetLowering::
387 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG)
389 SDValue Chain = Op.getOperand(0);
390 SDValue Size = Op.getOperand(1);
391 DebugLoc dl = Op.getDebugLoc();
393 // Get a reference from Mips stack pointer
394 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32);
396 // Subtract the dynamic size from the actual stack size to
397 // obtain the new stack size.
398 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
400 // The Sub result contains the new stack start address, so it
401 // must be placed in the stack pointer register.
402 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub);
404 // This node always has two return values: a new stack pointer
406 SDValue Ops[2] = { Sub, Chain };
407 return DAG.getMergeValues(Ops, 2, dl);
410 SDValue MipsTargetLowering::
411 LowerANDOR(SDValue Op, SelectionDAG &DAG)
413 SDValue LHS = Op.getOperand(0);
414 SDValue RHS = Op.getOperand(1);
415 DebugLoc dl = Op.getDebugLoc();
417 if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp)
420 SDValue True = DAG.getConstant(1, MVT::i32);
421 SDValue False = DAG.getConstant(0, MVT::i32);
423 SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
424 LHS, True, False, LHS.getOperand(2));
425 SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
426 RHS, True, False, RHS.getOperand(2));
428 return DAG.getNode(Op.getOpcode(), dl, MVT::i32, LSEL, RSEL);
431 SDValue MipsTargetLowering::
432 LowerBRCOND(SDValue Op, SelectionDAG &DAG)
434 // The first operand is the chain, the second is the condition, the third is
435 // the block to branch to if the condition is true.
436 SDValue Chain = Op.getOperand(0);
437 SDValue Dest = Op.getOperand(2);
438 DebugLoc dl = Op.getDebugLoc();
440 if (Op.getOperand(1).getOpcode() != MipsISD::FPCmp)
443 SDValue CondRes = Op.getOperand(1);
444 SDValue CCNode = CondRes.getOperand(2);
446 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
447 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
449 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
453 SDValue MipsTargetLowering::
454 LowerSETCC(SDValue Op, SelectionDAG &DAG)
456 // The operands to this are the left and right operands to compare (ops #0,
457 // and #1) and the condition code to compare them with (op #2) as a
459 SDValue LHS = Op.getOperand(0);
460 SDValue RHS = Op.getOperand(1);
461 DebugLoc dl = Op.getDebugLoc();
463 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
465 return DAG.getNode(MipsISD::FPCmp, dl, Op.getValueType(), LHS, RHS,
466 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
469 SDValue MipsTargetLowering::
470 LowerSELECT(SDValue Op, SelectionDAG &DAG)
472 SDValue Cond = Op.getOperand(0);
473 SDValue True = Op.getOperand(1);
474 SDValue False = Op.getOperand(2);
475 DebugLoc dl = Op.getDebugLoc();
477 // if the incomming condition comes from a integer compare, the select
478 // operation must be SelectCC or a conditional move if the subtarget
480 if (Cond.getOpcode() != MipsISD::FPCmp) {
481 if (Subtarget->hasCondMov() && !True.getValueType().isFloatingPoint())
483 return DAG.getNode(MipsISD::SelectCC, dl, True.getValueType(),
487 // if the incomming condition comes from fpcmp, the select
488 // operation must use FPSelectCC.
489 SDValue CCNode = Cond.getOperand(2);
490 return DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
491 Cond, True, False, CCNode);
494 SDValue MipsTargetLowering::
495 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
497 // FIXME there isn't actually debug info here
498 DebugLoc dl = Op.getDebugLoc();
499 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
500 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
502 if (!Subtarget->hasABICall()) {
503 SDVTList VTs = DAG.getVTList(MVT::i32);
504 // %hi/%lo relocation
505 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GA, 1);
506 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
507 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
509 } else { // Abicall relocations, TODO: make this cleaner.
510 SDValue ResNode = DAG.getLoad(MVT::i32, dl,
511 DAG.getEntryNode(), GA, NULL, 0);
512 // On functions and global targets not internal linked only
513 // a load from got/GP is necessary for PIC to work.
514 if (!GV->hasLocalLinkage() || isa<Function>(GV))
516 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
517 return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo);
520 llvm_unreachable("Dont know how to handle GlobalAddress");
524 SDValue MipsTargetLowering::
525 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
527 llvm_unreachable("TLS not implemented for MIPS.");
528 return SDValue(); // Not reached
531 SDValue MipsTargetLowering::
532 LowerJumpTable(SDValue Op, SelectionDAG &DAG)
536 // FIXME there isn't actually debug info here
537 DebugLoc dl = Op.getDebugLoc();
539 MVT PtrVT = Op.getValueType();
540 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
541 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
543 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
544 SDVTList VTs = DAG.getVTList(MVT::i32);
545 SDValue Ops[] = { JTI };
546 HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, Ops, 1);
547 } else // Emit Load from Global Pointer
548 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, NULL, 0);
550 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTI);
551 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
556 SDValue MipsTargetLowering::
557 LowerConstantPool(SDValue Op, SelectionDAG &DAG)
560 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
561 Constant *C = N->getConstVal();
562 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
563 // FIXME there isn't actually debug info here
564 DebugLoc dl = Op.getDebugLoc();
567 // FIXME: we should reference the constant pool using small data sections,
568 // but the asm printer currently doens't support this feature without
569 // hacking it. This feature should come soon so we can uncomment the
571 //if (!Subtarget->hasABICall() &&
572 // IsInSmallSection(getTargetData()->getTypeAllocSize(C->getType()))) {
573 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
574 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
575 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
576 //} else { // %hi/%lo relocation
577 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CP);
578 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP);
579 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
585 //===----------------------------------------------------------------------===//
586 // Calling Convention Implementation
588 // The lower operations present on calling convention works on this order:
589 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
590 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
591 // LowerRET (virt regs --> phys regs)
592 // LowerCALL (phys regs --> virt regs)
594 //===----------------------------------------------------------------------===//
596 #include "MipsGenCallingConv.inc"
598 //===----------------------------------------------------------------------===//
599 // TODO: Implement a generic logic using tblgen that can support this.
600 // Mips O32 ABI rules:
602 // i32 - Passed in A0, A1, A2, A3 and stack
603 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
604 // an argument. Otherwise, passed in A1, A2, A3 and stack.
605 // f64 - Only passed in two aliased f32 registers if no int reg has been used
606 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
607 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
609 //===----------------------------------------------------------------------===//
611 static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
612 MVT LocVT, CCValAssign::LocInfo LocInfo,
613 ISD::ArgFlagsTy ArgFlags, CCState &State) {
615 static const unsigned IntRegsSize=4, FloatRegsSize=2;
617 static const unsigned IntRegs[] = {
618 Mips::A0, Mips::A1, Mips::A2, Mips::A3
620 static const unsigned F32Regs[] = {
623 static const unsigned F64Regs[] = {
628 unsigned UnallocIntReg = State.getFirstUnallocated(IntRegs, IntRegsSize);
629 bool IntRegUsed = (IntRegs[UnallocIntReg] != (unsigned (Mips::A0)));
631 // Promote i8 and i16
632 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
634 if (ArgFlags.isSExt())
635 LocInfo = CCValAssign::SExt;
636 else if (ArgFlags.isZExt())
637 LocInfo = CCValAssign::ZExt;
639 LocInfo = CCValAssign::AExt;
642 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && IntRegUsed)) {
643 Reg = State.AllocateReg(IntRegs, IntRegsSize);
648 if (ValVT.isFloatingPoint() && !IntRegUsed) {
649 if (ValVT == MVT::f32)
650 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
652 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
655 if (ValVT == MVT::f64 && IntRegUsed) {
656 if (UnallocIntReg != IntRegsSize) {
657 // If we hit register A3 as the first not allocated, we must
658 // mark it as allocated (shadow) and use the stack instead.
659 if (IntRegs[UnallocIntReg] != (unsigned (Mips::A3)))
661 for (;UnallocIntReg < IntRegsSize; ++UnallocIntReg)
662 State.AllocateReg(UnallocIntReg);
668 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
669 unsigned Offset = State.AllocateStack(SizeInBytes, SizeInBytes);
670 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
672 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
674 return false; // CC must always match
677 //===----------------------------------------------------------------------===//
678 // CALL Calling Convention Implementation
679 //===----------------------------------------------------------------------===//
681 /// LowerCALL - functions arguments are copied from virtual regs to
682 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
683 /// TODO: isVarArg, isTailCall.
684 SDValue MipsTargetLowering::
685 LowerCALL(SDValue Op, SelectionDAG &DAG)
687 MachineFunction &MF = DAG.getMachineFunction();
689 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
690 SDValue Chain = TheCall->getChain();
691 SDValue Callee = TheCall->getCallee();
692 bool isVarArg = TheCall->isVarArg();
693 unsigned CC = TheCall->getCallingConv();
694 DebugLoc dl = TheCall->getDebugLoc();
696 MachineFrameInfo *MFI = MF.getFrameInfo();
698 // Analyze operands of the call, assigning locations to each operand.
699 SmallVector<CCValAssign, 16> ArgLocs;
700 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, *DAG.getContext());
702 // To meet O32 ABI, Mips must always allocate 16 bytes on
703 // the stack (even if less than 4 are used as arguments)
704 if (Subtarget->isABI_O32()) {
705 int VTsize = MVT(MVT::i32).getSizeInBits()/8;
706 MFI->CreateFixedObject(VTsize, (VTsize*3));
707 CCInfo.AnalyzeCallOperands(TheCall, CC_MipsO32);
709 CCInfo.AnalyzeCallOperands(TheCall, CC_Mips);
711 // Get a count of how many bytes are to be pushed on the stack.
712 unsigned NumBytes = CCInfo.getNextStackOffset();
713 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
715 // With EABI is it possible to have 16 args on registers.
716 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
717 SmallVector<SDValue, 8> MemOpChains;
719 // First/LastArgStackLoc contains the first/last
720 // "at stack" argument location.
721 int LastArgStackLoc = 0;
722 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
724 // Walk the register/memloc assignments, inserting copies/loads.
725 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
726 SDValue Arg = TheCall->getArg(i);
727 CCValAssign &VA = ArgLocs[i];
729 // Promote the value if needed.
730 switch (VA.getLocInfo()) {
731 default: llvm_unreachable("Unknown loc info!");
732 case CCValAssign::Full:
733 if (Subtarget->isABI_O32() && VA.isRegLoc()) {
734 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
735 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Arg);
736 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
737 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
738 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
739 DAG.getConstant(0, getPointerTy()));
740 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
741 DAG.getConstant(1, getPointerTy()));
742 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
743 RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi));
748 case CCValAssign::SExt:
749 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
751 case CCValAssign::ZExt:
752 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
754 case CCValAssign::AExt:
755 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
759 // Arguments that can be passed on register must be kept at
762 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
766 // Register can't get to this point...
767 assert(VA.isMemLoc());
769 // Create the frame index object for this incoming parameter
770 // This guarantees that when allocating Local Area the firsts
771 // 16 bytes which are alwayes reserved won't be overwritten
772 // if O32 ABI is used. For EABI the first address is zero.
773 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
774 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
777 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
779 // emit ISD::STORE whichs stores the
780 // parameter value to a stack Location
781 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0));
784 // Transform all store nodes into one single node because all store
785 // nodes are independent of each other.
786 if (!MemOpChains.empty())
787 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
788 &MemOpChains[0], MemOpChains.size());
790 // Build a sequence of copy-to-reg nodes chained together with token
791 // chain and flag operands which copy the outgoing args into registers.
792 // The InFlag in necessary since all emited instructions must be
795 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
796 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
797 RegsToPass[i].second, InFlag);
798 InFlag = Chain.getValue(1);
801 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
802 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
803 // node so that legalize doesn't hack it.
804 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
805 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
806 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
807 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
809 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
810 // = Chain, Callee, Reg#1, Reg#2, ...
812 // Returns a chain & a flag for retval copy to use.
813 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
814 SmallVector<SDValue, 8> Ops;
815 Ops.push_back(Chain);
816 Ops.push_back(Callee);
818 // Add argument registers to the end of the list so that they are
819 // known live into the call.
820 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
821 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
822 RegsToPass[i].second.getValueType()));
824 if (InFlag.getNode())
825 Ops.push_back(InFlag);
827 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
828 InFlag = Chain.getValue(1);
830 // Create the CALLSEQ_END node.
831 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
832 DAG.getIntPtrConstant(0, true), InFlag);
833 InFlag = Chain.getValue(1);
835 // Create a stack location to hold GP when PIC is used. This stack
836 // location is used on function prologue to save GP and also after all
837 // emited CALL's to restore GP.
838 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
839 // Function can have an arbitrary number of calls, so
840 // hold the LastArgStackLoc with the biggest offset.
842 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
843 if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
844 LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
845 // Create the frame index only once. SPOffset here can be anything
846 // (this will be fixed on processFunctionBeforeFrameFinalized)
847 if (MipsFI->getGPStackOffset() == -1) {
848 FI = MFI->CreateFixedObject(4, 0);
851 MipsFI->setGPStackOffset(LastArgStackLoc);
855 FI = MipsFI->getGPFI();
856 SDValue FIN = DAG.getFrameIndex(FI,getPointerTy());
857 SDValue GPLoad = DAG.getLoad(MVT::i32, dl, Chain, FIN, NULL, 0);
858 Chain = GPLoad.getValue(1);
859 Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, MVT::i32),
860 GPLoad, SDValue(0,0));
861 InFlag = Chain.getValue(1);
864 // Handle result values, copying them out of physregs into vregs that we
866 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG), Op.getResNo());
869 /// LowerCallResult - Lower the result values of an ISD::CALL into the
870 /// appropriate copies out of appropriate physical registers. This assumes that
871 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
872 /// being lowered. Returns a SDNode with the same number of values as the
874 SDNode *MipsTargetLowering::
875 LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
876 unsigned CallingConv, SelectionDAG &DAG) {
878 bool isVarArg = TheCall->isVarArg();
879 DebugLoc dl = TheCall->getDebugLoc();
881 // Assign locations to each value returned by this call.
882 SmallVector<CCValAssign, 16> RVLocs;
883 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(),
884 RVLocs, *DAG.getContext());
886 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
887 SmallVector<SDValue, 8> ResultVals;
889 // Copy all of the result registers out of their specified physreg.
890 for (unsigned i = 0; i != RVLocs.size(); ++i) {
891 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
892 RVLocs[i].getValVT(), InFlag).getValue(1);
893 InFlag = Chain.getValue(2);
894 ResultVals.push_back(Chain.getValue(0));
897 ResultVals.push_back(Chain);
899 // Merge everything together with a MERGE_VALUES node.
900 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
901 &ResultVals[0], ResultVals.size()).getNode();
904 //===----------------------------------------------------------------------===//
905 // FORMAL_ARGUMENTS Calling Convention Implementation
906 //===----------------------------------------------------------------------===//
908 /// LowerFORMAL_ARGUMENTS - transform physical registers into
909 /// virtual registers and generate load operations for
910 /// arguments places on the stack.
912 SDValue MipsTargetLowering::
913 LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG)
915 SDValue Root = Op.getOperand(0);
916 MachineFunction &MF = DAG.getMachineFunction();
917 MachineFrameInfo *MFI = MF.getFrameInfo();
918 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
919 DebugLoc dl = Op.getDebugLoc();
921 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
922 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
924 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
926 // Assign locations to all of the incoming arguments.
927 SmallVector<CCValAssign, 16> ArgLocs;
928 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, *DAG.getContext());
930 if (Subtarget->isABI_O32())
931 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_MipsO32);
933 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_Mips);
935 SmallVector<SDValue, 16> ArgValues;
938 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
940 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
941 CCValAssign &VA = ArgLocs[i];
943 // Arguments stored on registers
945 MVT RegVT = VA.getLocVT();
946 TargetRegisterClass *RC = 0;
948 if (RegVT == MVT::i32)
949 RC = Mips::CPURegsRegisterClass;
950 else if (RegVT == MVT::f32)
951 RC = Mips::FGR32RegisterClass;
952 else if (RegVT == MVT::f64) {
953 if (!Subtarget->isSingleFloat())
954 RC = Mips::AFGR64RegisterClass;
956 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
958 // Transform the arguments stored on
959 // physical registers into virtual ones
960 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
961 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT);
963 // If this is an 8 or 16-bit value, it has been passed promoted
964 // to 32 bits. Insert an assert[sz]ext to capture this, then
965 // truncate to the right size.
966 if (VA.getLocInfo() != CCValAssign::Full) {
968 if (VA.getLocInfo() == CCValAssign::SExt)
969 Opcode = ISD::AssertSext;
970 else if (VA.getLocInfo() == CCValAssign::ZExt)
971 Opcode = ISD::AssertZext;
973 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
974 DAG.getValueType(VA.getValVT()));
975 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
978 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64
979 if (Subtarget->isABI_O32()) {
980 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32)
981 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
982 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) {
983 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
984 VA.getLocReg()+1, RC);
985 SDValue ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg2, RegVT);
986 SDValue Hi = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
987 SDValue Lo = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue2);
988 ArgValue = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::f64, Lo, Hi);
992 ArgValues.push_back(ArgValue);
994 // To meet ABI, when VARARGS are passed on registers, the registers
995 // must have their values written to the caller stack frame.
996 if ((isVarArg) && (Subtarget->isABI_O32())) {
997 if (StackPtr.getNode() == 0)
998 StackPtr = DAG.getRegister(StackReg, getPointerTy());
1000 // The stack pointer offset is relative to the caller stack frame.
1001 // Since the real stack size is unknown here, a negative SPOffset
1002 // is used so there's a way to adjust these offsets when the stack
1003 // size get known (on EliminateFrameIndex). A dummy SPOffset is
1004 // used instead of a direct negative address (which is recorded to
1005 // be used on emitPrologue) to avoid mis-calc of the first stack
1006 // offset on PEI::calculateFrameObjectOffsets.
1007 // Arguments are always 32-bit.
1008 int FI = MFI->CreateFixedObject(4, 0);
1009 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
1010 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
1012 // emit ISD::STORE whichs stores the
1013 // parameter value to a stack Location
1014 ArgValues.push_back(DAG.getStore(Root, dl, ArgValue, PtrOff, NULL, 0));
1017 } else { // VA.isRegLoc()
1020 assert(VA.isMemLoc());
1022 // The stack pointer offset is relative to the caller stack frame.
1023 // Since the real stack size is unknown here, a negative SPOffset
1024 // is used so there's a way to adjust these offsets when the stack
1025 // size get known (on EliminateFrameIndex). A dummy SPOffset is
1026 // used instead of a direct negative address (which is recorded to
1027 // be used on emitPrologue) to avoid mis-calc of the first stack
1028 // offset on PEI::calculateFrameObjectOffsets.
1029 // Arguments are always 32-bit.
1030 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1031 int FI = MFI->CreateFixedObject(ArgSize, 0);
1032 MipsFI->recordLoadArgsFI(FI, -(ArgSize+
1033 (FirstStackArgLoc + VA.getLocMemOffset())));
1035 // Create load nodes to retrieve arguments from the stack
1036 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1037 ArgValues.push_back(DAG.getLoad(VA.getValVT(), dl, Root, FIN, NULL, 0));
1041 // The mips ABIs for returning structs by value requires that we copy
1042 // the sret argument into $v0 for the return. Save the argument into
1043 // a virtual register so that we can access it from the return points.
1044 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1045 unsigned Reg = MipsFI->getSRetReturnReg();
1047 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
1048 MipsFI->setSRetReturnReg(Reg);
1050 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, ArgValues[0]);
1051 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Root);
1054 ArgValues.push_back(Root);
1056 // Return the new list of results.
1057 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1058 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
1061 //===----------------------------------------------------------------------===//
1062 // Return Value Calling Convention Implementation
1063 //===----------------------------------------------------------------------===//
1065 SDValue MipsTargetLowering::
1066 LowerRET(SDValue Op, SelectionDAG &DAG)
1068 // CCValAssign - represent the assignment of
1069 // the return value to a location
1070 SmallVector<CCValAssign, 16> RVLocs;
1071 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
1072 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1073 DebugLoc dl = Op.getDebugLoc();
1075 // CCState - Info about the registers and stack slot.
1076 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs, *DAG.getContext());
1078 // Analize return values of ISD::RET
1079 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_Mips);
1081 // If this is the first return lowered for this function, add
1082 // the regs to the liveout set for the function.
1083 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1084 for (unsigned i = 0; i != RVLocs.size(); ++i)
1085 if (RVLocs[i].isRegLoc())
1086 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1089 // The chain is always operand #0
1090 SDValue Chain = Op.getOperand(0);
1093 // Copy the result values into the output registers.
1094 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1095 CCValAssign &VA = RVLocs[i];
1096 assert(VA.isRegLoc() && "Can only return in registers!");
1098 // ISD::RET => ret chain, (regnum1,val1), ...
1099 // So i*2+1 index only the regnums
1100 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1101 Op.getOperand(i*2+1), Flag);
1103 // guarantee that all emitted copies are
1104 // stuck together, avoiding something bad
1105 Flag = Chain.getValue(1);
1108 // The mips ABIs for returning structs by value requires that we copy
1109 // the sret argument into $v0 for the return. We saved the argument into
1110 // a virtual register in the entry block, so now we copy the value out
1112 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1113 MachineFunction &MF = DAG.getMachineFunction();
1114 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1115 unsigned Reg = MipsFI->getSRetReturnReg();
1118 llvm_unreachable("sret virtual register not created in the entry block");
1119 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1121 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
1122 Flag = Chain.getValue(1);
1125 // Return on Mips is always a "jr $ra"
1127 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1128 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
1130 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1131 Chain, DAG.getRegister(Mips::RA, MVT::i32));
1134 //===----------------------------------------------------------------------===//
1135 // Mips Inline Assembly Support
1136 //===----------------------------------------------------------------------===//
1138 /// getConstraintType - Given a constraint letter, return the type of
1139 /// constraint it is for this target.
1140 MipsTargetLowering::ConstraintType MipsTargetLowering::
1141 getConstraintType(const std::string &Constraint) const
1143 // Mips specific constrainy
1144 // GCC config/mips/constraints.md
1146 // 'd' : An address register. Equivalent to r
1147 // unless generating MIPS16 code.
1148 // 'y' : Equivalent to r; retained for
1149 // backwards compatibility.
1150 // 'f' : Floating Point registers.
1151 if (Constraint.size() == 1) {
1152 switch (Constraint[0]) {
1157 return C_RegisterClass;
1161 return TargetLowering::getConstraintType(Constraint);
1164 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1165 /// return a list of registers that can be used to satisfy the constraint.
1166 /// This should only be used for C_RegisterClass constraints.
1167 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
1168 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
1170 if (Constraint.size() == 1) {
1171 switch (Constraint[0]) {
1173 return std::make_pair(0U, Mips::CPURegsRegisterClass);
1176 return std::make_pair(0U, Mips::FGR32RegisterClass);
1178 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1179 return std::make_pair(0U, Mips::AFGR64RegisterClass);
1182 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1185 /// Given a register class constraint, like 'r', if this corresponds directly
1186 /// to an LLVM register class, return a register of 0 and the register class
1188 std::vector<unsigned> MipsTargetLowering::
1189 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1192 if (Constraint.size() != 1)
1193 return std::vector<unsigned>();
1195 switch (Constraint[0]) {
1198 // GCC Mips Constraint Letters
1201 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
1202 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
1203 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
1207 if (VT == MVT::f32) {
1208 if (Subtarget->isSingleFloat())
1209 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
1210 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
1211 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
1212 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
1213 Mips::F30, Mips::F31, 0);
1215 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
1216 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
1217 Mips::F28, Mips::F30, 0);
1221 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1222 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
1223 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
1224 Mips::D14, Mips::D15, 0);
1226 return std::vector<unsigned>();
1230 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1231 // The Mips target isn't yet aware of offsets.