1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
17 #include "MipsISelLowering.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsTargetMachine.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/SelectionDAGISel.h"
30 #include "llvm/CodeGen/ValueTypes.h"
31 #include "llvm/Support/Debug.h"
37 const char *MipsTargetLowering::
38 getTargetNodeName(unsigned Opcode) const
42 case MipsISD::JmpLink : return "MipsISD::JmpLink";
43 case MipsISD::Hi : return "MipsISD::Hi";
44 case MipsISD::Lo : return "MipsISD::Lo";
45 case MipsISD::Ret : return "MipsISD::Ret";
46 default : return NULL;
51 MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
53 // Mips does not have i1 type, so use i32 for
54 // setcc operations results (slt, sgt, ...).
55 setSetCCResultContents(ZeroOrOneSetCCResult);
57 // JumpTable targets must use GOT when using PIC_
58 setUsesGlobalOffsetTable(true);
60 // Set up the register classes
61 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
64 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
65 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
66 setOperationAction(ISD::RET, MVT::Other, Custom);
67 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
69 // Load extented operations for i1 types must be promoted
70 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
71 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
72 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
74 // Mips does not have these NodeTypes below.
75 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
76 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
77 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
78 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
79 setOperationAction(ISD::SELECT, MVT::i32, Expand);
80 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
82 // Mips not supported intrinsics.
83 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
84 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
85 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
86 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
88 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
89 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
90 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
91 setOperationAction(ISD::ROTL , MVT::i32, Expand);
92 setOperationAction(ISD::ROTR , MVT::i32, Expand);
93 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
95 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
96 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
97 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
99 // We don't have line number support yet.
100 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
101 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
102 setOperationAction(ISD::LABEL, MVT::Other, Expand);
104 // Use the default for now
105 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
106 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
108 setStackPointerRegisterToSaveRestore(Mips::SP);
109 computeRegisterProperties();
114 MipsTargetLowering::getSetCCResultType(const SDOperand &) const {
119 SDOperand MipsTargetLowering::
120 LowerOperation(SDOperand Op, SelectionDAG &DAG)
122 switch (Op.getOpcode())
124 case ISD::CALL: return LowerCALL(Op, DAG);
125 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
126 case ISD::RET: return LowerRET(Op, DAG);
127 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
128 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
129 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
134 //===----------------------------------------------------------------------===//
135 // Lower helper functions
136 //===----------------------------------------------------------------------===//
138 // AddLiveIn - This helper function adds the specified physical register to the
139 // MachineFunction as a live in value. It also creates a corresponding
140 // virtual register for it.
142 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
144 assert(RC->contains(PReg) && "Not the correct regclass!");
145 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
146 MF.getRegInfo().addLiveIn(PReg, VReg);
150 //===----------------------------------------------------------------------===//
151 // Misc Lower Operation implementation
152 //===----------------------------------------------------------------------===//
153 SDOperand MipsTargetLowering::
154 LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG)
157 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
158 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
159 bool isPIC = (getTargetMachine().getRelocationModel() == Reloc::PIC_);
163 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::i32);
164 SDOperand Ops[] = { GA };
165 HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
166 } else // Emit Load from Global Pointer
167 HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0);
169 // On functions and global targets not internal linked only
170 // a load from got/GP is necessary for PIC to work.
171 if ((isPIC) && ((!GV->hasInternalLinkage()) || (isa<Function>(GV))))
174 SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
175 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
180 SDOperand MipsTargetLowering::
181 LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG)
183 assert(0 && "TLS not implemented for MIPS.");
186 SDOperand MipsTargetLowering::
187 LowerJumpTable(SDOperand Op, SelectionDAG &DAG)
192 MVT::ValueType PtrVT = Op.getValueType();
193 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
194 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
196 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
197 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::i32);
198 SDOperand Ops[] = { JTI };
199 HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
200 } else // Emit Load from Global Pointer
201 HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), JTI, NULL, 0);
203 SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, JTI);
204 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
209 //===----------------------------------------------------------------------===//
210 // Calling Convention Implementation
212 // The lower operations present on calling convention works on this order:
213 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
214 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
215 // LowerRET (virt regs --> phys regs)
216 // LowerCALL (phys regs --> virt regs)
218 //===----------------------------------------------------------------------===//
220 #include "MipsGenCallingConv.inc"
222 //===----------------------------------------------------------------------===//
223 // CALL Calling Convention Implementation
224 //===----------------------------------------------------------------------===//
226 /// Mips custom CALL implementation
227 SDOperand MipsTargetLowering::
228 LowerCALL(SDOperand Op, SelectionDAG &DAG)
230 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
232 // By now, only CallingConv::C implemented
236 assert(0 && "Unsupported calling convention");
237 case CallingConv::Fast:
239 return LowerCCCCallTo(Op, DAG, CallingConv);
243 /// LowerCCCCallTo - functions arguments are copied from virtual
244 /// regs to (physical regs)/(stack frame), CALLSEQ_START and
245 /// CALLSEQ_END are emitted.
246 /// TODO: isVarArg, isTailCall, sret.
247 SDOperand MipsTargetLowering::
248 LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
250 MachineFunction &MF = DAG.getMachineFunction();
251 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
253 SDOperand Chain = Op.getOperand(0);
254 SDOperand Callee = Op.getOperand(4);
255 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
257 MachineFrameInfo *MFI = MF.getFrameInfo();
259 // Analyze operands of the call, assigning locations to each operand.
260 SmallVector<CCValAssign, 16> ArgLocs;
261 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
263 // To meet ABI, Mips must always allocate 16 bytes on
264 // the stack (even if less than 4 are used as arguments)
265 int VTsize = MVT::getSizeInBits(MVT::i32)/8;
266 MFI->CreateFixedObject(VTsize, (VTsize*3));
268 CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips);
270 // Get a count of how many bytes are to be pushed on the stack.
271 unsigned NumBytes = CCInfo.getNextStackOffset();
272 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
275 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
276 SmallVector<SDOperand, 8> MemOpChains;
281 // Walk the register/memloc assignments, inserting copies/loads.
282 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
283 CCValAssign &VA = ArgLocs[i];
285 // Arguments start after the 5 first operands of ISD::CALL
286 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
288 // Promote the value if needed.
289 switch (VA.getLocInfo()) {
290 default: assert(0 && "Unknown loc info!");
291 case CCValAssign::Full: break;
292 case CCValAssign::SExt:
293 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
295 case CCValAssign::ZExt:
296 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
298 case CCValAssign::AExt:
299 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
303 // Arguments that can be passed on register must be kept at
306 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
309 assert(VA.isMemLoc());
311 if (StackPtr.Val == 0)
312 StackPtr = DAG.getRegister(StackReg, getPointerTy());
314 // Create the frame index object for this incoming parameter
315 // This guarantees that when allocating Local Area the firsts
316 // 16 bytes which are alwayes reserved won't be overwritten.
317 LastStackLoc = (16 + VA.getLocMemOffset());
318 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
321 SDOperand PtrOff = DAG.getFrameIndex(FI,getPointerTy());
323 // emit ISD::STORE whichs stores the
324 // parameter value to a stack Location
325 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
329 // Transform all store nodes into one single node because
330 // all store nodes are independent of each other.
331 if (!MemOpChains.empty())
332 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
333 &MemOpChains[0], MemOpChains.size());
335 // Build a sequence of copy-to-reg nodes chained together with token
336 // chain and flag operands which copy the outgoing args into registers.
337 // The InFlag in necessary since all emited instructions must be
340 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
341 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first,
342 RegsToPass[i].second, InFlag);
343 InFlag = Chain.getValue(1);
346 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
347 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
348 // node so that legalize doesn't hack it.
349 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
350 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
351 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
352 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
355 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
356 // = Chain, Callee, Reg#1, Reg#2, ...
358 // Returns a chain & a flag for retval copy to use.
359 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
360 SmallVector<SDOperand, 8> Ops;
361 Ops.push_back(Chain);
362 Ops.push_back(Callee);
364 // Add argument registers to the end of the list so that they are
365 // known live into the call.
366 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
367 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
368 RegsToPass[i].second.getValueType()));
371 Ops.push_back(InFlag);
373 Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size());
374 InFlag = Chain.getValue(1);
376 // Create a stack location to hold GP when PIC is used. This stack
377 // location is used on function prologue to save GP and also after all
378 // emited CALL's to restore GP.
379 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
380 // Function can have an arbitrary number of calls, so
381 // hold the LastStackLoc with the biggest offset.
383 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
384 if (LastStackLoc >= MipsFI->getGPStackOffset()) {
385 LastStackLoc = (!LastStackLoc) ? (16) : (LastStackLoc+4);
386 // Create the frame index only once. SPOffset here can be anything
387 // (this will be fixed on processFunctionBeforeFrameFinalized)
388 if (MipsFI->getGPStackOffset() == -1) {
389 FI = MFI->CreateFixedObject(4, 0);
392 MipsFI->setGPStackOffset(LastStackLoc);
396 FI = MipsFI->getGPFI();
397 SDOperand FIN = DAG.getFrameIndex(FI,getPointerTy());
398 SDOperand GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0);
399 Chain = GPLoad.getValue(1);
400 Chain = DAG.getCopyToReg(Chain, DAG.getRegister(Mips::GP, MVT::i32),
401 GPLoad, SDOperand(0,0));
404 // Create the CALLSEQ_END node.
405 Chain = DAG.getCALLSEQ_END(Chain,
406 DAG.getConstant(NumBytes, getPointerTy()),
407 DAG.getConstant(0, getPointerTy()),
409 InFlag = Chain.getValue(1);
411 // Handle result values, copying them out of physregs into vregs that we
413 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
416 /// LowerCallResult - Lower the result values of an ISD::CALL into the
417 /// appropriate copies out of appropriate physical registers. This assumes that
418 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
419 /// being lowered. Returns a SDNode with the same number of values as the
421 SDNode *MipsTargetLowering::
422 LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
423 unsigned CallingConv, SelectionDAG &DAG) {
425 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
427 // Assign locations to each value returned by this call.
428 SmallVector<CCValAssign, 16> RVLocs;
429 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
431 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
432 SmallVector<SDOperand, 8> ResultVals;
434 // Copy all of the result registers out of their specified physreg.
435 for (unsigned i = 0; i != RVLocs.size(); ++i) {
436 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
437 RVLocs[i].getValVT(), InFlag).getValue(1);
438 InFlag = Chain.getValue(2);
439 ResultVals.push_back(Chain.getValue(0));
442 ResultVals.push_back(Chain);
444 // Merge everything together with a MERGE_VALUES node.
445 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
446 &ResultVals[0], ResultVals.size()).Val;
449 //===----------------------------------------------------------------------===//
450 // FORMAL_ARGUMENTS Calling Convention Implementation
451 //===----------------------------------------------------------------------===//
453 /// Mips custom FORMAL_ARGUMENTS implementation
454 SDOperand MipsTargetLowering::
455 LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG)
457 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
461 assert(0 && "Unsupported calling convention");
463 return LowerCCCArguments(Op, DAG);
467 /// LowerCCCArguments - transform physical registers into
468 /// virtual registers and generate load operations for
469 /// arguments places on the stack.
470 /// TODO: isVarArg, sret
471 SDOperand MipsTargetLowering::
472 LowerCCCArguments(SDOperand Op, SelectionDAG &DAG)
474 SDOperand Root = Op.getOperand(0);
475 MachineFunction &MF = DAG.getMachineFunction();
476 MachineFrameInfo *MFI = MF.getFrameInfo();
477 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
479 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
480 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
482 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
484 // GP holds the GOT address on PIC calls.
485 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
486 AddLiveIn(MF, Mips::GP, Mips::CPURegsRegisterClass);
488 // Assign locations to all of the incoming arguments.
489 SmallVector<CCValAssign, 16> ArgLocs;
490 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
492 CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips);
493 SmallVector<SDOperand, 8> ArgValues;
496 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
498 CCValAssign &VA = ArgLocs[i];
500 // Arguments stored on registers
502 MVT::ValueType RegVT = VA.getLocVT();
503 TargetRegisterClass *RC;
505 if (RegVT == MVT::i32)
506 RC = Mips::CPURegsRegisterClass;
508 assert(0 && "support only Mips::CPURegsRegisterClass");
510 // Transform the arguments stored on
511 // physical registers into virtual ones
512 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
513 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
515 // If this is an 8 or 16-bit value, it is really passed promoted
516 // to 32 bits. Insert an assert[sz]ext to capture this, then
517 // truncate to the right size.
518 if (VA.getLocInfo() == CCValAssign::SExt)
519 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
520 DAG.getValueType(VA.getValVT()));
521 else if (VA.getLocInfo() == CCValAssign::ZExt)
522 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
523 DAG.getValueType(VA.getValVT()));
525 if (VA.getLocInfo() != CCValAssign::Full)
526 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
528 ArgValues.push_back(ArgValue);
530 // To meet ABI, when VARARGS are passed on registers, the registers
531 // must have their values written to the caller stack frame.
534 if (StackPtr.Val == 0)
535 StackPtr = DAG.getRegister(StackReg, getPointerTy());
537 // The stack pointer offset is relative to the caller stack frame.
538 // Since the real stack size is unknown here, a negative SPOffset
539 // is used so there's a way to adjust these offsets when the stack
540 // size get known (on EliminateFrameIndex). A dummy SPOffset is
541 // used instead of a direct negative address (which is recorded to
542 // be used on emitPrologue) to avoid mis-calc of the first stack
543 // offset on PEI::calculateFrameObjectOffsets.
544 // Arguments are always 32-bit.
545 int FI = MFI->CreateFixedObject(4, 0);
546 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
547 SDOperand PtrOff = DAG.getFrameIndex(FI, getPointerTy());
549 // emit ISD::STORE whichs stores the
550 // parameter value to a stack Location
551 ArgValues.push_back(DAG.getStore(Root, ArgValue, PtrOff, NULL, 0));
556 assert(VA.isMemLoc());
558 // The stack pointer offset is relative to the caller stack frame.
559 // Since the real stack size is unknown here, a negative SPOffset
560 // is used so there's a way to adjust these offsets when the stack
561 // size get known (on EliminateFrameIndex). A dummy SPOffset is
562 // used instead of a direct negative address (which is recorded to
563 // be used on emitPrologue) to avoid mis-calc of the first stack
564 // offset on PEI::calculateFrameObjectOffsets.
565 // Arguments are always 32-bit.
566 int FI = MFI->CreateFixedObject(4, 0);
567 MipsFI->recordLoadArgsFI(FI, -(4+(16+VA.getLocMemOffset())));
569 // Create load nodes to retrieve arguments from the stack
570 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
571 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
574 ArgValues.push_back(Root);
576 // Return the new list of results.
577 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
578 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
581 //===----------------------------------------------------------------------===//
582 // Return Value Calling Convention Implementation
583 //===----------------------------------------------------------------------===//
585 SDOperand MipsTargetLowering::
586 LowerRET(SDOperand Op, SelectionDAG &DAG)
588 // CCValAssign - represent the assignment of
589 // the return value to a location
590 SmallVector<CCValAssign, 16> RVLocs;
591 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
592 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
594 // CCState - Info about the registers and stack slot.
595 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
597 // Analize return values of ISD::RET
598 CCInfo.AnalyzeReturn(Op.Val, RetCC_Mips);
600 // If this is the first return lowered for this function, add
601 // the regs to the liveout set for the function.
602 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
603 for (unsigned i = 0; i != RVLocs.size(); ++i)
604 if (RVLocs[i].isRegLoc())
605 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
608 // The chain is always operand #0
609 SDOperand Chain = Op.getOperand(0);
612 // Copy the result values into the output registers.
613 for (unsigned i = 0; i != RVLocs.size(); ++i) {
614 CCValAssign &VA = RVLocs[i];
615 assert(VA.isRegLoc() && "Can only return in registers!");
617 // ISD::RET => ret chain, (regnum1,val1), ...
618 // So i*2+1 index only the regnums
619 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
621 // guarantee that all emitted copies are
622 // stuck together, avoiding something bad
623 Flag = Chain.getValue(1);
626 // Return on Mips is always a "jr $ra"
628 return DAG.getNode(MipsISD::Ret, MVT::Other,
629 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
631 return DAG.getNode(MipsISD::Ret, MVT::Other,
632 Chain, DAG.getRegister(Mips::RA, MVT::i32));
635 //===----------------------------------------------------------------------===//
636 // Mips Inline Assembly Support
637 //===----------------------------------------------------------------------===//
639 /// getConstraintType - Given a constraint letter, return the type of
640 /// constraint it is for this target.
641 MipsTargetLowering::ConstraintType MipsTargetLowering::
642 getConstraintType(const std::string &Constraint) const
644 if (Constraint.size() == 1) {
645 // Mips specific constrainy
646 // GCC config/mips/constraints.md
648 // 'd' : An address register. Equivalent to r
649 // unless generating MIPS16 code.
650 // 'y' : Equivalent to r; retained for
651 // backwards compatibility.
653 switch (Constraint[0]) {
657 return C_RegisterClass;
661 return TargetLowering::getConstraintType(Constraint);
664 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
665 getRegForInlineAsmConstraint(const std::string &Constraint,
666 MVT::ValueType VT) const
668 if (Constraint.size() == 1) {
669 switch (Constraint[0]) {
671 return std::make_pair(0U, Mips::CPURegsRegisterClass);
675 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
678 std::vector<unsigned> MipsTargetLowering::
679 getRegClassForInlineAsmConstraint(const std::string &Constraint,
680 MVT::ValueType VT) const
682 if (Constraint.size() != 1)
683 return std::vector<unsigned>();
685 switch (Constraint[0]) {
688 // GCC Mips Constraint Letters
691 return make_vector<unsigned>(Mips::V0, Mips::V1, Mips::A0,
692 Mips::A1, Mips::A2, Mips::A3,
693 Mips::T0, Mips::T1, Mips::T2,
694 Mips::T3, Mips::T4, Mips::T5,
695 Mips::T6, Mips::T7, Mips::S0,
696 Mips::S1, Mips::S2, Mips::S3,
697 Mips::S4, Mips::S5, Mips::S6,
698 Mips::S7, Mips::T8, Mips::T9, 0);
701 return std::vector<unsigned>();