1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
17 #include "MipsISelLowering.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsTargetMachine.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
36 const char *MipsTargetLowering::
37 getTargetNodeName(unsigned Opcode) const
41 case MipsISD::JmpLink : return "MipsISD::JmpLink";
42 case MipsISD::Hi : return "MipsISD::Hi";
43 case MipsISD::Lo : return "MipsISD::Lo";
44 case MipsISD::GPRel : return "MipsISD::GPRel";
45 case MipsISD::Ret : return "MipsISD::Ret";
46 case MipsISD::CMov : return "MipsISD::CMov";
47 case MipsISD::SelectCC : return "MipsISD::SelectCC";
48 case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC";
49 case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
50 case MipsISD::FPCmp : return "MipsISD::FPCmp";
51 case MipsISD::FPRound : return "MipsISD::FPRound";
52 default : return NULL;
57 MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
59 Subtarget = &TM.getSubtarget<MipsSubtarget>();
61 // Mips does not have i1 type, so use i32 for
62 // setcc operations results (slt, sgt, ...).
63 setBooleanContents(ZeroOrOneBooleanContent);
65 // JumpTable targets must use GOT when using PIC_
66 setUsesGlobalOffsetTable(true);
68 // Set up the register classes
69 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
70 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
72 // When dealing with single precision only, use libcalls
73 if (!Subtarget->isSingleFloat())
74 if (!Subtarget->isFP64bit())
75 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
78 addLegalFPImmediate(APFloat(+0.0f));
80 // Load extented operations for i1 types must be promoted
81 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
82 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
83 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
85 // Used by legalize types to correctly generate the setcc result.
86 // Without this, every float setcc comes with a AND/OR with the result,
87 // we don't want this, since the fpcmp result goes to a flag register,
88 // which is used implicitly by brcond and select operations.
89 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
91 // Mips Custom Operations
92 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
93 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
94 setOperationAction(ISD::RET, MVT::Other, Custom);
95 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
96 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
97 setOperationAction(ISD::SELECT, MVT::f32, Custom);
98 setOperationAction(ISD::SELECT, MVT::f64, Custom);
99 setOperationAction(ISD::SELECT, MVT::i32, Custom);
100 setOperationAction(ISD::SETCC, MVT::f32, Custom);
101 setOperationAction(ISD::SETCC, MVT::f64, Custom);
102 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
103 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
104 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
106 // We custom lower AND/OR to handle the case where the DAG contain 'ands/ors'
107 // with operands comming from setcc fp comparions. This is necessary since
108 // the result from these setcc are in a flag registers (FCR31).
109 setOperationAction(ISD::AND, MVT::i32, Custom);
110 setOperationAction(ISD::OR, MVT::i32, Custom);
112 // Operations not directly supported by Mips.
113 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
114 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
115 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
116 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
117 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
119 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
120 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
121 setOperationAction(ISD::ROTL, MVT::i32, Expand);
122 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
123 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
124 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
125 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
126 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
128 // We don't have line number support yet.
129 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
130 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
131 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
132 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
134 // Use the default for now
135 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
136 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
137 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
139 if (Subtarget->isSingleFloat())
140 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
142 if (!Subtarget->hasSEInReg()) {
143 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
144 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
147 if (!Subtarget->hasBitCount())
148 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
150 if (!Subtarget->hasSwap())
151 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
153 setStackPointerRegisterToSaveRestore(Mips::SP);
154 computeRegisterProperties();
157 MVT MipsTargetLowering::getSetCCResultType(MVT VT) const {
161 /// getFunctionAlignment - Return the Log2 alignment of this function.
162 unsigned MipsTargetLowering::getFunctionAlignment(const Function *) const {
166 SDValue MipsTargetLowering::
167 LowerOperation(SDValue Op, SelectionDAG &DAG)
169 switch (Op.getOpcode())
171 case ISD::AND: return LowerANDOR(Op, DAG);
172 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
173 case ISD::CALL: return LowerCALL(Op, DAG);
174 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
175 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
176 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
177 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
178 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
179 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
180 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
181 case ISD::OR: return LowerANDOR(Op, DAG);
182 case ISD::RET: return LowerRET(Op, DAG);
183 case ISD::SELECT: return LowerSELECT(Op, DAG);
184 case ISD::SETCC: return LowerSETCC(Op, DAG);
189 //===----------------------------------------------------------------------===//
190 // Lower helper functions
191 //===----------------------------------------------------------------------===//
193 // AddLiveIn - This helper function adds the specified physical register to the
194 // MachineFunction as a live in value. It also creates a corresponding
195 // virtual register for it.
197 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
199 assert(RC->contains(PReg) && "Not the correct regclass!");
200 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
201 MF.getRegInfo().addLiveIn(PReg, VReg);
205 // A address must be loaded from a small section if its size is less than the
206 // small section size threshold. Data in this section must be addressed using
208 bool MipsTargetLowering::IsInSmallSection(unsigned Size) {
209 return (Size > 0 && (Size <= Subtarget->getSSectionThreshold()));
212 // Discover if this global address can be placed into small data/bss section.
213 bool MipsTargetLowering::IsGlobalInSmallSection(GlobalValue *GV)
215 const TargetData *TD = getTargetData();
216 const GlobalVariable *GVA = dyn_cast<GlobalVariable>(GV);
221 const Type *Ty = GV->getType()->getElementType();
222 unsigned Size = TD->getTypeAllocSize(Ty);
224 // if this is a internal constant string, there is a special
225 // section for it, but not in small data/bss.
226 if (GVA->hasInitializer() && GV->hasLocalLinkage()) {
227 Constant *C = GVA->getInitializer();
228 const ConstantArray *CVA = dyn_cast<ConstantArray>(C);
229 if (CVA && CVA->isCString())
233 return IsInSmallSection(Size);
236 // Get fp branch code (not opcode) from condition code.
237 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
238 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
239 return Mips::BRANCH_T;
241 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
242 return Mips::BRANCH_F;
244 return Mips::BRANCH_INVALID;
247 static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) {
250 assert(0 && "Unknown branch code");
251 case Mips::BRANCH_T : return Mips::BC1T;
252 case Mips::BRANCH_F : return Mips::BC1F;
253 case Mips::BRANCH_TL : return Mips::BC1TL;
254 case Mips::BRANCH_FL : return Mips::BC1FL;
258 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
260 default: assert(0 && "Unknown fp condition code!");
262 case ISD::SETOEQ: return Mips::FCOND_EQ;
263 case ISD::SETUNE: return Mips::FCOND_OGL;
265 case ISD::SETOLT: return Mips::FCOND_OLT;
267 case ISD::SETOGT: return Mips::FCOND_OGT;
269 case ISD::SETOLE: return Mips::FCOND_OLE;
271 case ISD::SETOGE: return Mips::FCOND_OGE;
272 case ISD::SETULT: return Mips::FCOND_ULT;
273 case ISD::SETULE: return Mips::FCOND_ULE;
274 case ISD::SETUGT: return Mips::FCOND_UGT;
275 case ISD::SETUGE: return Mips::FCOND_UGE;
276 case ISD::SETUO: return Mips::FCOND_UN;
277 case ISD::SETO: return Mips::FCOND_OR;
279 case ISD::SETONE: return Mips::FCOND_NEQ;
280 case ISD::SETUEQ: return Mips::FCOND_UEQ;
285 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
286 MachineBasicBlock *BB) const {
287 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
288 bool isFPCmp = false;
289 DebugLoc dl = MI->getDebugLoc();
291 switch (MI->getOpcode()) {
292 default: assert(false && "Unexpected instr type to insert");
293 case Mips::Select_FCC:
294 case Mips::Select_FCC_S32:
295 case Mips::Select_FCC_D32:
296 isFPCmp = true; // FALL THROUGH
297 case Mips::Select_CC:
298 case Mips::Select_CC_S32:
299 case Mips::Select_CC_D32: {
300 // To "insert" a SELECT_CC instruction, we actually have to insert the
301 // diamond control-flow pattern. The incoming instruction knows the
302 // destination vreg to set, the condition code register to branch on, the
303 // true/false values to select between, and a branch opcode to use.
304 const BasicBlock *LLVM_BB = BB->getBasicBlock();
305 MachineFunction::iterator It = BB;
312 // bNE r1, r0, copy1MBB
313 // fallthrough --> copy0MBB
314 MachineBasicBlock *thisMBB = BB;
315 MachineFunction *F = BB->getParent();
316 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
317 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
319 // Emit the right instruction according to the type of the operands compared
321 // Find the condiction code present in the setcc operation.
322 Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm();
323 // Get the branch opcode from the branch code.
324 unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC));
325 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
327 BuildMI(BB, dl, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
328 .addReg(Mips::ZERO).addMBB(sinkMBB);
330 F->insert(It, copy0MBB);
331 F->insert(It, sinkMBB);
332 // Update machine-CFG edges by first adding all successors of the current
333 // block to the new block which will contain the Phi node for the select.
334 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
335 e = BB->succ_end(); i != e; ++i)
336 sinkMBB->addSuccessor(*i);
337 // Next, remove all successors of the current block, and add the true
338 // and fallthrough blocks as its successors.
339 while(!BB->succ_empty())
340 BB->removeSuccessor(BB->succ_begin());
341 BB->addSuccessor(copy0MBB);
342 BB->addSuccessor(sinkMBB);
346 // # fallthrough to sinkMBB
349 // Update machine-CFG edges
350 BB->addSuccessor(sinkMBB);
353 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
356 BuildMI(BB, dl, TII->get(Mips::PHI), MI->getOperand(0).getReg())
357 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
358 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
360 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
366 //===----------------------------------------------------------------------===//
367 // Misc Lower Operation implementation
368 //===----------------------------------------------------------------------===//
370 SDValue MipsTargetLowering::
371 LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG)
373 if (!Subtarget->isMips1())
376 MachineFunction &MF = DAG.getMachineFunction();
377 unsigned CCReg = AddLiveIn(MF, Mips::FCR31, Mips::CCRRegisterClass);
379 SDValue Chain = DAG.getEntryNode();
380 DebugLoc dl = Op.getDebugLoc();
381 SDValue Src = Op.getOperand(0);
383 // Set the condition register
384 SDValue CondReg = DAG.getCopyFromReg(Chain, dl, CCReg, MVT::i32);
385 CondReg = DAG.getCopyToReg(Chain, dl, Mips::AT, CondReg);
386 CondReg = DAG.getCopyFromReg(CondReg, dl, Mips::AT, MVT::i32);
388 SDValue Cst = DAG.getConstant(3, MVT::i32);
389 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i32, CondReg, Cst);
390 Cst = DAG.getConstant(2, MVT::i32);
391 SDValue Xor = DAG.getNode(ISD::XOR, dl, MVT::i32, Or, Cst);
393 SDValue InFlag(0, 0);
394 CondReg = DAG.getCopyToReg(Chain, dl, Mips::FCR31, Xor, InFlag);
396 // Emit the round instruction and bit convert to integer
397 SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, MVT::f32,
398 Src, CondReg.getValue(1));
399 SDValue BitCvt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Trunc);
403 SDValue MipsTargetLowering::
404 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG)
406 SDValue Chain = Op.getOperand(0);
407 SDValue Size = Op.getOperand(1);
408 DebugLoc dl = Op.getDebugLoc();
410 // Get a reference from Mips stack pointer
411 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32);
413 // Subtract the dynamic size from the actual stack size to
414 // obtain the new stack size.
415 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
417 // The Sub result contains the new stack start address, so it
418 // must be placed in the stack pointer register.
419 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub);
421 // This node always has two return values: a new stack pointer
423 SDValue Ops[2] = { Sub, Chain };
424 return DAG.getMergeValues(Ops, 2, dl);
427 SDValue MipsTargetLowering::
428 LowerANDOR(SDValue Op, SelectionDAG &DAG)
430 SDValue LHS = Op.getOperand(0);
431 SDValue RHS = Op.getOperand(1);
432 DebugLoc dl = Op.getDebugLoc();
434 if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp)
437 SDValue True = DAG.getConstant(1, MVT::i32);
438 SDValue False = DAG.getConstant(0, MVT::i32);
440 SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
441 LHS, True, False, LHS.getOperand(2));
442 SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
443 RHS, True, False, RHS.getOperand(2));
445 return DAG.getNode(Op.getOpcode(), dl, MVT::i32, LSEL, RSEL);
448 SDValue MipsTargetLowering::
449 LowerBRCOND(SDValue Op, SelectionDAG &DAG)
451 // The first operand is the chain, the second is the condition, the third is
452 // the block to branch to if the condition is true.
453 SDValue Chain = Op.getOperand(0);
454 SDValue Dest = Op.getOperand(2);
455 DebugLoc dl = Op.getDebugLoc();
457 if (Op.getOperand(1).getOpcode() != MipsISD::FPCmp)
460 SDValue CondRes = Op.getOperand(1);
461 SDValue CCNode = CondRes.getOperand(2);
463 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
464 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
466 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
470 SDValue MipsTargetLowering::
471 LowerSETCC(SDValue Op, SelectionDAG &DAG)
473 // The operands to this are the left and right operands to compare (ops #0,
474 // and #1) and the condition code to compare them with (op #2) as a
476 SDValue LHS = Op.getOperand(0);
477 SDValue RHS = Op.getOperand(1);
478 DebugLoc dl = Op.getDebugLoc();
480 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
482 return DAG.getNode(MipsISD::FPCmp, dl, Op.getValueType(), LHS, RHS,
483 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
486 SDValue MipsTargetLowering::
487 LowerSELECT(SDValue Op, SelectionDAG &DAG)
489 SDValue Cond = Op.getOperand(0);
490 SDValue True = Op.getOperand(1);
491 SDValue False = Op.getOperand(2);
492 DebugLoc dl = Op.getDebugLoc();
494 // if the incomming condition comes from a integer compare, the select
495 // operation must be SelectCC or a conditional move if the subtarget
497 if (Cond.getOpcode() != MipsISD::FPCmp) {
498 if (Subtarget->hasCondMov() && !True.getValueType().isFloatingPoint())
500 return DAG.getNode(MipsISD::SelectCC, dl, True.getValueType(),
504 // if the incomming condition comes from fpcmp, the select
505 // operation must use FPSelectCC.
506 SDValue CCNode = Cond.getOperand(2);
507 return DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
508 Cond, True, False, CCNode);
511 SDValue MipsTargetLowering::
512 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
514 // FIXME there isn't actually debug info here
515 DebugLoc dl = Op.getDebugLoc();
516 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
517 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
519 if (!Subtarget->hasABICall()) {
520 SDVTList VTs = DAG.getVTList(MVT::i32);
521 SDValue Ops[] = { GA };
522 // %gp_rel relocation
523 if (!isa<Function>(GV) && IsGlobalInSmallSection(GV)) {
524 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, Ops, 1);
525 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
526 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
528 // %hi/%lo relocation
529 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, Ops, 1);
530 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
531 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
533 } else { // Abicall relocations, TODO: make this cleaner.
534 SDValue ResNode = DAG.getLoad(MVT::i32, dl,
535 DAG.getEntryNode(), GA, NULL, 0);
536 // On functions and global targets not internal linked only
537 // a load from got/GP is necessary for PIC to work.
538 if (!GV->hasLocalLinkage() || isa<Function>(GV))
540 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
541 return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo);
544 assert(0 && "Dont know how to handle GlobalAddress");
548 SDValue MipsTargetLowering::
549 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
551 assert(0 && "TLS not implemented for MIPS.");
552 return SDValue(); // Not reached
555 SDValue MipsTargetLowering::
556 LowerJumpTable(SDValue Op, SelectionDAG &DAG)
560 // FIXME there isn't actually debug info here
561 DebugLoc dl = Op.getDebugLoc();
563 MVT PtrVT = Op.getValueType();
564 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
565 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
567 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
568 SDVTList VTs = DAG.getVTList(MVT::i32);
569 SDValue Ops[] = { JTI };
570 HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, Ops, 1);
571 } else // Emit Load from Global Pointer
572 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, NULL, 0);
574 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTI);
575 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
580 SDValue MipsTargetLowering::
581 LowerConstantPool(SDValue Op, SelectionDAG &DAG)
584 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
585 Constant *C = N->getConstVal();
586 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
587 // FIXME there isn't actually debug info here
588 DebugLoc dl = Op.getDebugLoc();
591 // FIXME: we should reference the constant pool using small data sections,
592 // but the asm printer currently doens't support this feature without
593 // hacking it. This feature should come soon so we can uncomment the
595 //if (!Subtarget->hasABICall() &&
596 // IsInSmallSection(getTargetData()->getTypeAllocSize(C->getType()))) {
597 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
598 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
599 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
600 //} else { // %hi/%lo relocation
601 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CP);
602 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP);
603 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
609 //===----------------------------------------------------------------------===//
610 // Calling Convention Implementation
612 // The lower operations present on calling convention works on this order:
613 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
614 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
615 // LowerRET (virt regs --> phys regs)
616 // LowerCALL (phys regs --> virt regs)
618 //===----------------------------------------------------------------------===//
620 #include "MipsGenCallingConv.inc"
622 //===----------------------------------------------------------------------===//
623 // TODO: Implement a generic logic using tblgen that can support this.
624 // Mips O32 ABI rules:
626 // i32 - Passed in A0, A1, A2, A3 and stack
627 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
628 // an argument. Otherwise, passed in A1, A2, A3 and stack.
629 // f64 - Only passed in two aliased f32 registers if no int reg has been used
630 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
631 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
633 //===----------------------------------------------------------------------===//
635 static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
636 MVT LocVT, CCValAssign::LocInfo LocInfo,
637 ISD::ArgFlagsTy ArgFlags, CCState &State) {
639 static const unsigned IntRegsSize=4, FloatRegsSize=2;
641 static const unsigned IntRegs[] = {
642 Mips::A0, Mips::A1, Mips::A2, Mips::A3
644 static const unsigned F32Regs[] = {
647 static const unsigned F64Regs[] = {
652 unsigned UnallocIntReg = State.getFirstUnallocated(IntRegs, IntRegsSize);
653 bool IntRegUsed = (IntRegs[UnallocIntReg] != (unsigned (Mips::A0)));
655 // Promote i8 and i16
656 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
658 if (ArgFlags.isSExt())
659 LocInfo = CCValAssign::SExt;
660 else if (ArgFlags.isZExt())
661 LocInfo = CCValAssign::ZExt;
663 LocInfo = CCValAssign::AExt;
666 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && IntRegUsed)) {
667 Reg = State.AllocateReg(IntRegs, IntRegsSize);
672 if (ValVT.isFloatingPoint() && !IntRegUsed) {
673 if (ValVT == MVT::f32)
674 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
676 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
679 if (ValVT == MVT::f64 && IntRegUsed) {
680 if (UnallocIntReg != IntRegsSize) {
681 // If we hit register A3 as the first not allocated, we must
682 // mark it as allocated (shadow) and use the stack instead.
683 if (IntRegs[UnallocIntReg] != (unsigned (Mips::A3)))
685 for (;UnallocIntReg < IntRegsSize; ++UnallocIntReg)
686 State.AllocateReg(UnallocIntReg);
692 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
693 unsigned Offset = State.AllocateStack(SizeInBytes, SizeInBytes);
694 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
696 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
698 return false; // CC must always match
701 //===----------------------------------------------------------------------===//
702 // CALL Calling Convention Implementation
703 //===----------------------------------------------------------------------===//
705 /// LowerCALL - functions arguments are copied from virtual regs to
706 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
707 /// TODO: isVarArg, isTailCall.
708 SDValue MipsTargetLowering::
709 LowerCALL(SDValue Op, SelectionDAG &DAG)
711 MachineFunction &MF = DAG.getMachineFunction();
713 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
714 SDValue Chain = TheCall->getChain();
715 SDValue Callee = TheCall->getCallee();
716 bool isVarArg = TheCall->isVarArg();
717 unsigned CC = TheCall->getCallingConv();
718 DebugLoc dl = TheCall->getDebugLoc();
720 MachineFrameInfo *MFI = MF.getFrameInfo();
722 // Analyze operands of the call, assigning locations to each operand.
723 SmallVector<CCValAssign, 16> ArgLocs;
724 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, DAG.getContext());
726 // To meet O32 ABI, Mips must always allocate 16 bytes on
727 // the stack (even if less than 4 are used as arguments)
728 if (Subtarget->isABI_O32()) {
729 int VTsize = MVT(MVT::i32).getSizeInBits()/8;
730 MFI->CreateFixedObject(VTsize, (VTsize*3));
731 CCInfo.AnalyzeCallOperands(TheCall, CC_MipsO32);
733 CCInfo.AnalyzeCallOperands(TheCall, CC_Mips);
735 // Get a count of how many bytes are to be pushed on the stack.
736 unsigned NumBytes = CCInfo.getNextStackOffset();
737 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
739 // With EABI is it possible to have 16 args on registers.
740 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
741 SmallVector<SDValue, 8> MemOpChains;
743 // First/LastArgStackLoc contains the first/last
744 // "at stack" argument location.
745 int LastArgStackLoc = 0;
746 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
748 // Walk the register/memloc assignments, inserting copies/loads.
749 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
750 SDValue Arg = TheCall->getArg(i);
751 CCValAssign &VA = ArgLocs[i];
753 // Promote the value if needed.
754 switch (VA.getLocInfo()) {
755 default: assert(0 && "Unknown loc info!");
756 case CCValAssign::Full:
757 if (Subtarget->isABI_O32() && VA.isRegLoc()) {
758 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
759 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Arg);
760 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
761 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
762 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
763 DAG.getConstant(0, getPointerTy()));
764 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
765 DAG.getConstant(1, getPointerTy()));
766 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
767 RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi));
772 case CCValAssign::SExt:
773 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
775 case CCValAssign::ZExt:
776 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
778 case CCValAssign::AExt:
779 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
783 // Arguments that can be passed on register must be kept at
786 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
790 // Register can't get to this point...
791 assert(VA.isMemLoc());
793 // Create the frame index object for this incoming parameter
794 // This guarantees that when allocating Local Area the firsts
795 // 16 bytes which are alwayes reserved won't be overwritten
796 // if O32 ABI is used. For EABI the first address is zero.
797 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
798 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
801 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
803 // emit ISD::STORE whichs stores the
804 // parameter value to a stack Location
805 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0));
808 // Transform all store nodes into one single node because all store
809 // nodes are independent of each other.
810 if (!MemOpChains.empty())
811 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
812 &MemOpChains[0], MemOpChains.size());
814 // Build a sequence of copy-to-reg nodes chained together with token
815 // chain and flag operands which copy the outgoing args into registers.
816 // The InFlag in necessary since all emited instructions must be
819 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
820 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
821 RegsToPass[i].second, InFlag);
822 InFlag = Chain.getValue(1);
825 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
826 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
827 // node so that legalize doesn't hack it.
828 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
829 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
830 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
831 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
833 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
834 // = Chain, Callee, Reg#1, Reg#2, ...
836 // Returns a chain & a flag for retval copy to use.
837 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
838 SmallVector<SDValue, 8> Ops;
839 Ops.push_back(Chain);
840 Ops.push_back(Callee);
842 // Add argument registers to the end of the list so that they are
843 // known live into the call.
844 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
845 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
846 RegsToPass[i].second.getValueType()));
848 if (InFlag.getNode())
849 Ops.push_back(InFlag);
851 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
852 InFlag = Chain.getValue(1);
854 // Create the CALLSEQ_END node.
855 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
856 DAG.getIntPtrConstant(0, true), InFlag);
857 InFlag = Chain.getValue(1);
859 // Create a stack location to hold GP when PIC is used. This stack
860 // location is used on function prologue to save GP and also after all
861 // emited CALL's to restore GP.
862 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
863 // Function can have an arbitrary number of calls, so
864 // hold the LastArgStackLoc with the biggest offset.
866 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
867 if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
868 LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
869 // Create the frame index only once. SPOffset here can be anything
870 // (this will be fixed on processFunctionBeforeFrameFinalized)
871 if (MipsFI->getGPStackOffset() == -1) {
872 FI = MFI->CreateFixedObject(4, 0);
875 MipsFI->setGPStackOffset(LastArgStackLoc);
879 FI = MipsFI->getGPFI();
880 SDValue FIN = DAG.getFrameIndex(FI,getPointerTy());
881 SDValue GPLoad = DAG.getLoad(MVT::i32, dl, Chain, FIN, NULL, 0);
882 Chain = GPLoad.getValue(1);
883 Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, MVT::i32),
884 GPLoad, SDValue(0,0));
885 InFlag = Chain.getValue(1);
888 // Handle result values, copying them out of physregs into vregs that we
890 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG), Op.getResNo());
893 /// LowerCallResult - Lower the result values of an ISD::CALL into the
894 /// appropriate copies out of appropriate physical registers. This assumes that
895 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
896 /// being lowered. Returns a SDNode with the same number of values as the
898 SDNode *MipsTargetLowering::
899 LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
900 unsigned CallingConv, SelectionDAG &DAG) {
902 bool isVarArg = TheCall->isVarArg();
903 DebugLoc dl = TheCall->getDebugLoc();
905 // Assign locations to each value returned by this call.
906 SmallVector<CCValAssign, 16> RVLocs;
907 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(),
908 RVLocs, DAG.getContext());
910 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
911 SmallVector<SDValue, 8> ResultVals;
913 // Copy all of the result registers out of their specified physreg.
914 for (unsigned i = 0; i != RVLocs.size(); ++i) {
915 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
916 RVLocs[i].getValVT(), InFlag).getValue(1);
917 InFlag = Chain.getValue(2);
918 ResultVals.push_back(Chain.getValue(0));
921 ResultVals.push_back(Chain);
923 // Merge everything together with a MERGE_VALUES node.
924 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
925 &ResultVals[0], ResultVals.size()).getNode();
928 //===----------------------------------------------------------------------===//
929 // FORMAL_ARGUMENTS Calling Convention Implementation
930 //===----------------------------------------------------------------------===//
932 /// LowerFORMAL_ARGUMENTS - transform physical registers into
933 /// virtual registers and generate load operations for
934 /// arguments places on the stack.
936 SDValue MipsTargetLowering::
937 LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG)
939 SDValue Root = Op.getOperand(0);
940 MachineFunction &MF = DAG.getMachineFunction();
941 MachineFrameInfo *MFI = MF.getFrameInfo();
942 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
943 DebugLoc dl = Op.getDebugLoc();
945 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
946 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
948 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
950 // Assign locations to all of the incoming arguments.
951 SmallVector<CCValAssign, 16> ArgLocs;
952 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, DAG.getContext());
954 if (Subtarget->isABI_O32())
955 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_MipsO32);
957 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_Mips);
959 SmallVector<SDValue, 16> ArgValues;
962 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
964 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
965 CCValAssign &VA = ArgLocs[i];
967 // Arguments stored on registers
969 MVT RegVT = VA.getLocVT();
970 TargetRegisterClass *RC = 0;
972 if (RegVT == MVT::i32)
973 RC = Mips::CPURegsRegisterClass;
974 else if (RegVT == MVT::f32)
975 RC = Mips::FGR32RegisterClass;
976 else if (RegVT == MVT::f64) {
977 if (!Subtarget->isSingleFloat())
978 RC = Mips::AFGR64RegisterClass;
980 assert(0 && "RegVT not supported by FORMAL_ARGUMENTS Lowering");
982 // Transform the arguments stored on
983 // physical registers into virtual ones
984 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
985 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT);
987 // If this is an 8 or 16-bit value, it has been passed promoted
988 // to 32 bits. Insert an assert[sz]ext to capture this, then
989 // truncate to the right size.
990 if (VA.getLocInfo() != CCValAssign::Full) {
992 if (VA.getLocInfo() == CCValAssign::SExt)
993 Opcode = ISD::AssertSext;
994 else if (VA.getLocInfo() == CCValAssign::ZExt)
995 Opcode = ISD::AssertZext;
997 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
998 DAG.getValueType(VA.getValVT()));
999 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1002 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64
1003 if (Subtarget->isABI_O32()) {
1004 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32)
1005 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
1006 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) {
1007 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
1008 VA.getLocReg()+1, RC);
1009 SDValue ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg2, RegVT);
1010 SDValue Hi = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
1011 SDValue Lo = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue2);
1012 ArgValue = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::f64, Lo, Hi);
1016 ArgValues.push_back(ArgValue);
1018 // To meet ABI, when VARARGS are passed on registers, the registers
1019 // must have their values written to the caller stack frame.
1020 if ((isVarArg) && (Subtarget->isABI_O32())) {
1021 if (StackPtr.getNode() == 0)
1022 StackPtr = DAG.getRegister(StackReg, getPointerTy());
1024 // The stack pointer offset is relative to the caller stack frame.
1025 // Since the real stack size is unknown here, a negative SPOffset
1026 // is used so there's a way to adjust these offsets when the stack
1027 // size get known (on EliminateFrameIndex). A dummy SPOffset is
1028 // used instead of a direct negative address (which is recorded to
1029 // be used on emitPrologue) to avoid mis-calc of the first stack
1030 // offset on PEI::calculateFrameObjectOffsets.
1031 // Arguments are always 32-bit.
1032 int FI = MFI->CreateFixedObject(4, 0);
1033 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
1034 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
1036 // emit ISD::STORE whichs stores the
1037 // parameter value to a stack Location
1038 ArgValues.push_back(DAG.getStore(Root, dl, ArgValue, PtrOff, NULL, 0));
1041 } else { // VA.isRegLoc()
1044 assert(VA.isMemLoc());
1046 // The stack pointer offset is relative to the caller stack frame.
1047 // Since the real stack size is unknown here, a negative SPOffset
1048 // is used so there's a way to adjust these offsets when the stack
1049 // size get known (on EliminateFrameIndex). A dummy SPOffset is
1050 // used instead of a direct negative address (which is recorded to
1051 // be used on emitPrologue) to avoid mis-calc of the first stack
1052 // offset on PEI::calculateFrameObjectOffsets.
1053 // Arguments are always 32-bit.
1054 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1055 int FI = MFI->CreateFixedObject(ArgSize, 0);
1056 MipsFI->recordLoadArgsFI(FI, -(ArgSize+
1057 (FirstStackArgLoc + VA.getLocMemOffset())));
1059 // Create load nodes to retrieve arguments from the stack
1060 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1061 ArgValues.push_back(DAG.getLoad(VA.getValVT(), dl, Root, FIN, NULL, 0));
1065 // The mips ABIs for returning structs by value requires that we copy
1066 // the sret argument into $v0 for the return. Save the argument into
1067 // a virtual register so that we can access it from the return points.
1068 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1069 unsigned Reg = MipsFI->getSRetReturnReg();
1071 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
1072 MipsFI->setSRetReturnReg(Reg);
1074 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, ArgValues[0]);
1075 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Root);
1078 ArgValues.push_back(Root);
1080 // Return the new list of results.
1081 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1082 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
1085 //===----------------------------------------------------------------------===//
1086 // Return Value Calling Convention Implementation
1087 //===----------------------------------------------------------------------===//
1089 SDValue MipsTargetLowering::
1090 LowerRET(SDValue Op, SelectionDAG &DAG)
1092 // CCValAssign - represent the assignment of
1093 // the return value to a location
1094 SmallVector<CCValAssign, 16> RVLocs;
1095 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
1096 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1097 DebugLoc dl = Op.getDebugLoc();
1099 // CCState - Info about the registers and stack slot.
1100 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs, DAG.getContext());
1102 // Analize return values of ISD::RET
1103 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_Mips);
1105 // If this is the first return lowered for this function, add
1106 // the regs to the liveout set for the function.
1107 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1108 for (unsigned i = 0; i != RVLocs.size(); ++i)
1109 if (RVLocs[i].isRegLoc())
1110 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1113 // The chain is always operand #0
1114 SDValue Chain = Op.getOperand(0);
1117 // Copy the result values into the output registers.
1118 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1119 CCValAssign &VA = RVLocs[i];
1120 assert(VA.isRegLoc() && "Can only return in registers!");
1122 // ISD::RET => ret chain, (regnum1,val1), ...
1123 // So i*2+1 index only the regnums
1124 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1125 Op.getOperand(i*2+1), Flag);
1127 // guarantee that all emitted copies are
1128 // stuck together, avoiding something bad
1129 Flag = Chain.getValue(1);
1132 // The mips ABIs for returning structs by value requires that we copy
1133 // the sret argument into $v0 for the return. We saved the argument into
1134 // a virtual register in the entry block, so now we copy the value out
1136 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1137 MachineFunction &MF = DAG.getMachineFunction();
1138 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1139 unsigned Reg = MipsFI->getSRetReturnReg();
1142 assert(0 && "sret virtual register not created in the entry block");
1143 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1145 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
1146 Flag = Chain.getValue(1);
1149 // Return on Mips is always a "jr $ra"
1151 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1152 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
1154 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1155 Chain, DAG.getRegister(Mips::RA, MVT::i32));
1158 //===----------------------------------------------------------------------===//
1159 // Mips Inline Assembly Support
1160 //===----------------------------------------------------------------------===//
1162 /// getConstraintType - Given a constraint letter, return the type of
1163 /// constraint it is for this target.
1164 MipsTargetLowering::ConstraintType MipsTargetLowering::
1165 getConstraintType(const std::string &Constraint) const
1167 // Mips specific constrainy
1168 // GCC config/mips/constraints.md
1170 // 'd' : An address register. Equivalent to r
1171 // unless generating MIPS16 code.
1172 // 'y' : Equivalent to r; retained for
1173 // backwards compatibility.
1174 // 'f' : Floating Point registers.
1175 if (Constraint.size() == 1) {
1176 switch (Constraint[0]) {
1181 return C_RegisterClass;
1185 return TargetLowering::getConstraintType(Constraint);
1188 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1189 /// return a list of registers that can be used to satisfy the constraint.
1190 /// This should only be used for C_RegisterClass constraints.
1191 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
1192 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
1194 if (Constraint.size() == 1) {
1195 switch (Constraint[0]) {
1197 return std::make_pair(0U, Mips::CPURegsRegisterClass);
1200 return std::make_pair(0U, Mips::FGR32RegisterClass);
1202 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1203 return std::make_pair(0U, Mips::AFGR64RegisterClass);
1206 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1209 /// Given a register class constraint, like 'r', if this corresponds directly
1210 /// to an LLVM register class, return a register of 0 and the register class
1212 std::vector<unsigned> MipsTargetLowering::
1213 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1216 if (Constraint.size() != 1)
1217 return std::vector<unsigned>();
1219 switch (Constraint[0]) {
1222 // GCC Mips Constraint Letters
1225 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
1226 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
1227 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
1231 if (VT == MVT::f32) {
1232 if (Subtarget->isSingleFloat())
1233 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
1234 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
1235 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
1236 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
1237 Mips::F30, Mips::F31, 0);
1239 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
1240 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
1241 Mips::F28, Mips::F30, 0);
1245 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1246 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
1247 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
1248 Mips::D14, Mips::D15, 0);
1250 return std::vector<unsigned>();
1254 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1255 // The Mips target isn't yet aware of offsets.