1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Bruno Cardoso Lopes and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
17 #include "MipsISelLowering.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsTargetMachine.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/SelectionDAGISel.h"
29 #include "llvm/CodeGen/SSARegMap.h"
30 #include "llvm/CodeGen/ValueTypes.h"
31 #include "llvm/Support/Debug.h"
37 const char *MipsTargetLowering::
38 getTargetNodeName(unsigned Opcode) const
42 case MipsISD::JmpLink : return "MipsISD::JmpLink";
43 case MipsISD::Hi : return "MipsISD::Hi";
44 case MipsISD::Lo : return "MipsISD::Lo";
45 case MipsISD::Ret : return "MipsISD::Ret";
46 default : return NULL;
51 MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
53 // Mips does not have i1 type, so use i32 for
54 // setcc operations results (slt, sgt, ...).
55 setSetCCResultType(MVT::i32);
56 setSetCCResultContents(ZeroOrOneSetCCResult);
58 // Set up the register classes
59 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
62 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
63 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
64 setOperationAction(ISD::RET, MVT::Other, Custom);
66 // Load extented operations for i1 types must be promoted
67 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
68 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
69 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
71 // Store operations for i1 types must be promoted
72 setStoreXAction(MVT::i1, Promote);
74 // Mips does not have these NodeTypes below.
75 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
76 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
77 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
78 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
79 setOperationAction(ISD::SELECT, MVT::i32, Expand);
80 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
82 // Mips not supported intrinsics.
83 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
84 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
85 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
87 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
88 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
89 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
90 setOperationAction(ISD::ROTL , MVT::i32, Expand);
91 setOperationAction(ISD::ROTR , MVT::i32, Expand);
92 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
94 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
95 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
96 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
98 // We don't have line number support yet.
99 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
100 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
101 setOperationAction(ISD::LABEL, MVT::Other, Expand);
103 // Use the default for now
104 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
105 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
107 setStackPointerRegisterToSaveRestore(Mips::SP);
108 computeRegisterProperties();
112 SDOperand MipsTargetLowering::
113 LowerOperation(SDOperand Op, SelectionDAG &DAG)
115 switch (Op.getOpcode())
117 case ISD::CALL: return LowerCALL(Op, DAG);
118 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
119 case ISD::RET: return LowerRET(Op, DAG);
120 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
121 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
126 //===----------------------------------------------------------------------===//
127 // Lower helper functions
128 //===----------------------------------------------------------------------===//
130 // AddLiveIn - This helper function adds the specified physical register to the
131 // MachineFunction as a live in value. It also creates a corresponding
132 // virtual register for it.
134 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
136 assert(RC->contains(PReg) && "Not the correct regclass!");
137 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
138 MF.addLiveIn(PReg, VReg);
142 //===----------------------------------------------------------------------===//
143 // Misc Lower Operation implementation
144 //===----------------------------------------------------------------------===//
145 SDOperand MipsTargetLowering::
146 LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG)
149 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
150 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
151 bool isPIC = (getTargetMachine().getRelocationModel() == Reloc::PIC_);
155 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::i32);
156 SDOperand Ops[] = { GA };
157 HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
158 } else // Emit Load from Global Pointer
159 HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0);
161 // On functions and global targets not internal linked only
162 // a load from got/GP is necessary for PIC to work.
163 if ((isPIC) && ((!GV->hasInternalLinkage()) || (isa<Function>(GV))))
166 SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
167 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
172 SDOperand MipsTargetLowering::
173 LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG)
175 assert(0 && "TLS not implemented for MIPS.");
178 //===----------------------------------------------------------------------===//
179 // Calling Convention Implementation
181 // The lower operations present on calling convention works on this order:
182 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
183 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
184 // LowerRET (virt regs --> phys regs)
185 // LowerCALL (phys regs --> virt regs)
187 //===----------------------------------------------------------------------===//
189 #include "MipsGenCallingConv.inc"
191 //===----------------------------------------------------------------------===//
192 // CALL Calling Convention Implementation
193 //===----------------------------------------------------------------------===//
195 /// Mips custom CALL implementation
196 SDOperand MipsTargetLowering::
197 LowerCALL(SDOperand Op, SelectionDAG &DAG)
199 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
201 // By now, only CallingConv::C implemented
205 assert(0 && "Unsupported calling convention");
206 case CallingConv::Fast:
208 return LowerCCCCallTo(Op, DAG, CallingConv);
212 /// LowerCCCCallTo - functions arguments are copied from virtual
213 /// regs to (physical regs)/(stack frame), CALLSEQ_START and
214 /// CALLSEQ_END are emitted.
215 /// TODO: isVarArg, isTailCall, sret.
216 SDOperand MipsTargetLowering::
217 LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
219 MachineFunction &MF = DAG.getMachineFunction();
220 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
222 SDOperand Chain = Op.getOperand(0);
223 SDOperand Callee = Op.getOperand(4);
224 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
226 MachineFrameInfo *MFI = MF.getFrameInfo();
228 // Analyze operands of the call, assigning locations to each operand.
229 SmallVector<CCValAssign, 16> ArgLocs;
230 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
232 // To meet ABI, Mips must always allocate 16 bytes on
233 // the stack (even if less than 4 are used as arguments)
234 int VTsize = MVT::getSizeInBits(MVT::i32)/8;
235 MFI->CreateFixedObject(VTsize, (VTsize*3));
237 CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips);
239 // Get a count of how many bytes are to be pushed on the stack.
240 unsigned NumBytes = CCInfo.getNextStackOffset();
241 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
244 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
245 SmallVector<SDOperand, 8> MemOpChains;
250 // Walk the register/memloc assignments, inserting copies/loads.
251 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
252 CCValAssign &VA = ArgLocs[i];
254 // Arguments start after the 5 first operands of ISD::CALL
255 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
257 // Promote the value if needed.
258 switch (VA.getLocInfo()) {
259 default: assert(0 && "Unknown loc info!");
260 case CCValAssign::Full: break;
261 case CCValAssign::SExt:
262 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
264 case CCValAssign::ZExt:
265 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
267 case CCValAssign::AExt:
268 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
272 // Arguments that can be passed on register must be kept at
275 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
278 assert(VA.isMemLoc());
280 if (StackPtr.Val == 0)
281 StackPtr = DAG.getRegister(StackReg, getPointerTy());
283 // Create the frame index object for this incoming parameter
284 // This guarantees that when allocating Local Area the firsts
285 // 16 bytes which are alwayes reserved won't be overwritten.
286 LastStackLoc = (16 + VA.getLocMemOffset());
287 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
290 SDOperand PtrOff = DAG.getFrameIndex(FI,getPointerTy());
292 // emit ISD::STORE whichs stores the
293 // parameter value to a stack Location
294 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
298 // Transform all store nodes into one single node because
299 // all store nodes are independent of each other.
300 if (!MemOpChains.empty())
301 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
302 &MemOpChains[0], MemOpChains.size());
304 // Build a sequence of copy-to-reg nodes chained together with token
305 // chain and flag operands which copy the outgoing args into registers.
306 // The InFlag in necessary since all emited instructions must be
309 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
310 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first,
311 RegsToPass[i].second, InFlag);
312 InFlag = Chain.getValue(1);
315 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
316 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
317 // node so that legalize doesn't hack it.
318 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
319 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
320 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
321 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
324 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
325 // = Chain, Callee, Reg#1, Reg#2, ...
327 // Returns a chain & a flag for retval copy to use.
328 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
329 SmallVector<SDOperand, 8> Ops;
330 Ops.push_back(Chain);
331 Ops.push_back(Callee);
333 // Add argument registers to the end of the list so that they are
334 // known live into the call.
335 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
336 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
337 RegsToPass[i].second.getValueType()));
340 Ops.push_back(InFlag);
342 Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size());
343 InFlag = Chain.getValue(1);
345 // Create a stack location to hold GP when PIC is used. This stack
346 // location is used on function prologue to save GP and also after all
347 // emited CALL's to restore GP.
348 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
350 // Function can have an arbitrary number of calls, so
351 // hold the LastStackLoc with the biggest offset.
353 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
354 if (LastStackLoc >= MipsFI->getGPStackOffset()) {
356 LastStackLoc = (!LastStackLoc) ? (16) : (LastStackLoc+4);
357 // Create the frame index only once. SPOffset here can be anything
358 // (this will be fixed on processFunctionBeforeFrameFinalized)
359 if (MipsFI->getGPStackOffset() == -1) {
360 FI = MFI->CreateFixedObject(4, 0);
363 MipsFI->setGPStackOffset(LastStackLoc);
368 FI = MipsFI->getGPFI();
369 SDOperand FIN = DAG.getFrameIndex(FI,getPointerTy());
370 SDOperand GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0);
371 Chain = GPLoad.getValue(1);
372 Chain = DAG.getCopyToReg(Chain, DAG.getRegister(Mips::GP, MVT::i32),
373 GPLoad, SDOperand(0,0));
376 // Create the CALLSEQ_END node.
377 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
379 Ops.push_back(Chain);
380 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
381 Ops.push_back(InFlag);
382 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
383 InFlag = Chain.getValue(1);
385 // Handle result values, copying them out of physregs into vregs that we
387 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
390 /// LowerCallResult - Lower the result values of an ISD::CALL into the
391 /// appropriate copies out of appropriate physical registers. This assumes that
392 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
393 /// being lowered. Returns a SDNode with the same number of values as the
395 SDNode *MipsTargetLowering::
396 LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
397 unsigned CallingConv, SelectionDAG &DAG) {
399 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
401 // Assign locations to each value returned by this call.
402 SmallVector<CCValAssign, 16> RVLocs;
403 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
405 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
406 SmallVector<SDOperand, 8> ResultVals;
408 // Copy all of the result registers out of their specified physreg.
409 for (unsigned i = 0; i != RVLocs.size(); ++i) {
410 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
411 RVLocs[i].getValVT(), InFlag).getValue(1);
412 InFlag = Chain.getValue(2);
413 ResultVals.push_back(Chain.getValue(0));
416 ResultVals.push_back(Chain);
418 // Merge everything together with a MERGE_VALUES node.
419 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
420 &ResultVals[0], ResultVals.size()).Val;
423 //===----------------------------------------------------------------------===//
424 // FORMAL_ARGUMENTS Calling Convention Implementation
425 //===----------------------------------------------------------------------===//
427 /// Mips custom FORMAL_ARGUMENTS implementation
428 SDOperand MipsTargetLowering::
429 LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG)
431 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
435 assert(0 && "Unsupported calling convention");
437 return LowerCCCArguments(Op, DAG);
441 /// LowerCCCArguments - transform physical registers into
442 /// virtual registers and generate load operations for
443 /// arguments places on the stack.
444 /// TODO: isVarArg, sret
445 SDOperand MipsTargetLowering::
446 LowerCCCArguments(SDOperand Op, SelectionDAG &DAG)
448 SDOperand Root = Op.getOperand(0);
449 MachineFunction &MF = DAG.getMachineFunction();
450 MachineFrameInfo *MFI = MF.getFrameInfo();
451 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
453 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
454 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
456 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
458 // Assign locations to all of the incoming arguments.
459 SmallVector<CCValAssign, 16> ArgLocs;
460 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
462 CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips);
463 SmallVector<SDOperand, 8> ArgValues;
466 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
468 CCValAssign &VA = ArgLocs[i];
470 // Arguments stored on registers
472 MVT::ValueType RegVT = VA.getLocVT();
473 TargetRegisterClass *RC;
475 if (RegVT == MVT::i32)
476 RC = Mips::CPURegsRegisterClass;
478 assert(0 && "support only Mips::CPURegsRegisterClass");
480 // Transform the arguments stored on
481 // physical registers into virtual ones
482 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
483 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
485 // If this is an 8 or 16-bit value, it is really passed promoted
486 // to 32 bits. Insert an assert[sz]ext to capture this, then
487 // truncate to the right size.
488 if (VA.getLocInfo() == CCValAssign::SExt)
489 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
490 DAG.getValueType(VA.getValVT()));
491 else if (VA.getLocInfo() == CCValAssign::ZExt)
492 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
493 DAG.getValueType(VA.getValVT()));
495 if (VA.getLocInfo() != CCValAssign::Full)
496 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
498 ArgValues.push_back(ArgValue);
500 // To meet ABI, when VARARGS are passed on registers, the registers
501 // must have their values written to the caller stack frame.
504 if (StackPtr.Val == 0)
505 StackPtr = DAG.getRegister(StackReg, getPointerTy());
507 // The stack pointer offset is relative to the caller stack frame.
508 // Since the real stack size is unknown here, a negative SPOffset
509 // is used so there's a way to adjust these offsets when the stack
510 // size get known (on EliminateFrameIndex). A dummy SPOffset is
511 // used instead of a direct negative address (which is recorded to
512 // be used on emitPrologue) to avoid mis-calc of the first stack
513 // offset on PEI::calculateFrameObjectOffsets.
514 // Arguments are always 32-bit.
515 int FI = MFI->CreateFixedObject(4, 0);
516 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
517 SDOperand PtrOff = DAG.getFrameIndex(FI, getPointerTy());
519 // emit ISD::STORE whichs stores the
520 // parameter value to a stack Location
521 ArgValues.push_back(DAG.getStore(Root, ArgValue, PtrOff, NULL, 0));
526 assert(VA.isMemLoc());
528 // The stack pointer offset is relative to the caller stack frame.
529 // Since the real stack size is unknown here, a negative SPOffset
530 // is used so there's a way to adjust these offsets when the stack
531 // size get known (on EliminateFrameIndex). A dummy SPOffset is
532 // used instead of a direct negative address (which is recorded to
533 // be used on emitPrologue) to avoid mis-calc of the first stack
534 // offset on PEI::calculateFrameObjectOffsets.
535 // Arguments are always 32-bit.
536 int FI = MFI->CreateFixedObject(4, 0);
537 MipsFI->recordLoadArgsFI(FI, -(4+(16+VA.getLocMemOffset())));
539 // Create load nodes to retrieve arguments from the stack
540 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
541 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
544 ArgValues.push_back(Root);
546 // Return the new list of results.
547 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
548 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
551 //===----------------------------------------------------------------------===//
552 // Return Value Calling Convention Implementation
553 //===----------------------------------------------------------------------===//
555 SDOperand MipsTargetLowering::
556 LowerRET(SDOperand Op, SelectionDAG &DAG)
558 // CCValAssign - represent the assignment of
559 // the return value to a location
560 SmallVector<CCValAssign, 16> RVLocs;
561 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
562 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
564 // CCState - Info about the registers and stack slot.
565 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
567 // Analize return values of ISD::RET
568 CCInfo.AnalyzeReturn(Op.Val, RetCC_Mips);
570 // If this is the first return lowered for this function, add
571 // the regs to the liveout set for the function.
572 if (DAG.getMachineFunction().liveout_empty()) {
573 for (unsigned i = 0; i != RVLocs.size(); ++i)
574 if (RVLocs[i].isRegLoc())
575 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg());
578 // The chain is always operand #0
579 SDOperand Chain = Op.getOperand(0);
582 // Copy the result values into the output registers.
583 for (unsigned i = 0; i != RVLocs.size(); ++i) {
584 CCValAssign &VA = RVLocs[i];
585 assert(VA.isRegLoc() && "Can only return in registers!");
587 // ISD::RET => ret chain, (regnum1,val1), ...
588 // So i*2+1 index only the regnums
589 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
591 // guarantee that all emitted copies are
592 // stuck together, avoiding something bad
593 Flag = Chain.getValue(1);
596 // Return on Mips is always a "jr $ra"
598 return DAG.getNode(MipsISD::Ret, MVT::Other,
599 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
601 return DAG.getNode(MipsISD::Ret, MVT::Other,
602 Chain, DAG.getRegister(Mips::RA, MVT::i32));
605 //===----------------------------------------------------------------------===//
606 // Mips Inline Assembly Support
607 //===----------------------------------------------------------------------===//
609 /// getConstraintType - Given a constraint letter, return the type of
610 /// constraint it is for this target.
611 MipsTargetLowering::ConstraintType MipsTargetLowering::
612 getConstraintType(const std::string &Constraint) const
614 if (Constraint.size() == 1) {
615 // Mips specific constrainy
616 // GCC config/mips/constraints.md
618 // 'd' : An address register. Equivalent to r
619 // unless generating MIPS16 code.
620 // 'y' : Equivalent to r; retained for
621 // backwards compatibility.
623 switch (Constraint[0]) {
627 return C_RegisterClass;
631 return TargetLowering::getConstraintType(Constraint);
634 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
635 getRegForInlineAsmConstraint(const std::string &Constraint,
636 MVT::ValueType VT) const
638 if (Constraint.size() == 1) {
639 switch (Constraint[0]) {
641 return std::make_pair(0U, Mips::CPURegsRegisterClass);
645 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
648 std::vector<unsigned> MipsTargetLowering::
649 getRegClassForInlineAsmConstraint(const std::string &Constraint,
650 MVT::ValueType VT) const
652 if (Constraint.size() != 1)
653 return std::vector<unsigned>();
655 switch (Constraint[0]) {
658 // GCC Mips Constraint Letters
661 return make_vector<unsigned>(Mips::V0, Mips::V1, Mips::A0,
662 Mips::A1, Mips::A2, Mips::A3,
663 Mips::T0, Mips::T1, Mips::T2,
664 Mips::T3, Mips::T4, Mips::T5,
665 Mips::T6, Mips::T7, Mips::S0,
666 Mips::S1, Mips::S2, Mips::S3,
667 Mips::S4, Mips::S5, Mips::S6,
668 Mips::S7, Mips::T8, Mips::T9, 0);
671 return std::vector<unsigned>();