1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Bruno Cardoso Lopes and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
17 #include "MipsISelLowering.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsTargetMachine.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/SelectionDAGISel.h"
29 #include "llvm/CodeGen/SSARegMap.h"
30 #include "llvm/CodeGen/ValueTypes.h"
31 #include "llvm/Support/Debug.h"
37 const char *MipsTargetLowering::
38 getTargetNodeName(unsigned Opcode) const
42 case MipsISD::JmpLink : return "MipsISD::JmpLink";
43 case MipsISD::Hi : return "MipsISD::Hi";
44 case MipsISD::Lo : return "MipsISD::Lo";
45 case MipsISD::Ret : return "MipsISD::Ret";
46 case MipsISD::Add : return "MipsISD::Add";
47 default : return NULL;
52 MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
54 // Mips does not have i1 type, so use i32 for
55 // setcc operations results (slt, sgt, ...).
56 setSetCCResultType(MVT::i32);
57 setSetCCResultContents(ZeroOrOneSetCCResult);
59 // Set up the register classes
60 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
63 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
64 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
65 setOperationAction(ISD::RET, MVT::Other, Custom);
67 // Load extented operations for i1 types must be promoted
68 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
69 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
70 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
72 // Store operations for i1 types must be promoted
73 setStoreXAction(MVT::i1, Promote);
75 // Mips does not have these NodeTypes below.
76 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
77 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
78 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
79 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
80 setOperationAction(ISD::SELECT, MVT::i32, Expand);
81 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
83 // Mips not supported intrinsics.
84 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
85 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
86 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
88 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
89 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
90 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
91 setOperationAction(ISD::ROTL , MVT::i32, Expand);
92 setOperationAction(ISD::ROTR , MVT::i32, Expand);
93 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
95 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
96 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
97 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
99 // We don't have line number support yet.
100 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
101 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
102 setOperationAction(ISD::LABEL, MVT::Other, Expand);
104 // Use the default for now
105 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
106 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
108 setOperationAction(ISD::ADJUST_TRAMP, MVT::i32, Expand);
110 setStackPointerRegisterToSaveRestore(Mips::SP);
111 computeRegisterProperties();
115 SDOperand MipsTargetLowering::
116 LowerOperation(SDOperand Op, SelectionDAG &DAG)
118 switch (Op.getOpcode())
120 case ISD::CALL: return LowerCALL(Op, DAG);
121 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
122 case ISD::RET: return LowerRET(Op, DAG);
123 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
124 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
129 //===----------------------------------------------------------------------===//
130 // Lower helper functions
131 //===----------------------------------------------------------------------===//
133 // AddLiveIn - This helper function adds the specified physical register to the
134 // MachineFunction as a live in value. It also creates a corresponding
135 // virtual register for it.
137 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
139 assert(RC->contains(PReg) && "Not the correct regclass!");
140 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
141 MF.addLiveIn(PReg, VReg);
145 //===----------------------------------------------------------------------===//
146 // Misc Lower Operation implementation
147 //===----------------------------------------------------------------------===//
148 SDOperand MipsTargetLowering::
149 LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG)
151 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
153 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
155 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::i32, MVT::Flag);
156 SDOperand Ops[] = { GA };
158 SDOperand Hi = DAG.getNode(MipsISD::Hi, VTs, 2, Ops, 1);
159 SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
161 SDOperand InFlag = Hi.getValue(1);
162 return DAG.getNode(MipsISD::Add, MVT::i32, Lo, Hi, InFlag);
165 SDOperand MipsTargetLowering::
166 LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG)
168 assert(0 && "TLS not implemented for MIPS.");
171 //===----------------------------------------------------------------------===//
172 // Calling Convention Implementation
174 // The lower operations present on calling convention works on this order:
175 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
176 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
177 // LowerRET (virt regs --> phys regs)
178 // LowerCALL (phys regs --> virt regs)
180 //===----------------------------------------------------------------------===//
182 #include "MipsGenCallingConv.inc"
184 //===----------------------------------------------------------------------===//
185 // CALL Calling Convention Implementation
186 //===----------------------------------------------------------------------===//
188 /// Mips custom CALL implementation
189 SDOperand MipsTargetLowering::
190 LowerCALL(SDOperand Op, SelectionDAG &DAG)
192 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
194 // By now, only CallingConv::C implemented
198 assert(0 && "Unsupported calling convention");
199 case CallingConv::Fast:
201 return LowerCCCCallTo(Op, DAG, CallingConv);
205 /// LowerCCCCallTo - functions arguments are copied from virtual
206 /// regs to (physical regs)/(stack frame), CALLSEQ_START and
207 /// CALLSEQ_END are emitted.
208 /// TODO: isVarArg, isTailCall, sret, GOT, linkage types.
209 SDOperand MipsTargetLowering::
210 LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
212 MachineFunction &MF = DAG.getMachineFunction();
213 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
215 SDOperand Chain = Op.getOperand(0);
216 SDOperand Callee = Op.getOperand(4);
217 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
219 MachineFrameInfo *MFI = MF.getFrameInfo();
221 // Analyze operands of the call, assigning locations to each operand.
222 SmallVector<CCValAssign, 16> ArgLocs;
223 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
225 // To meet ABI, Mips must always allocate 16 bytes on
226 // the stack (even if less than 4 are used as arguments)
227 int VTsize = MVT::getSizeInBits(MVT::i32)/8;
228 MFI->CreateFixedObject(VTsize, (VTsize*3));
230 CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips);
232 // Get a count of how many bytes are to be pushed on the stack.
233 unsigned NumBytes = CCInfo.getNextStackOffset();
234 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
237 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
238 SmallVector<SDOperand, 8> MemOpChains;
242 // Walk the register/memloc assignments, inserting copies/loads.
243 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
244 CCValAssign &VA = ArgLocs[i];
246 // Arguments start after the 5 first operands of ISD::CALL
247 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
249 // Promote the value if needed.
250 switch (VA.getLocInfo()) {
251 default: assert(0 && "Unknown loc info!");
252 case CCValAssign::Full: break;
253 case CCValAssign::SExt:
254 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
256 case CCValAssign::ZExt:
257 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
259 case CCValAssign::AExt:
260 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
264 // Arguments that can be passed on register,
265 // must be kept at RegsToPass vector
267 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
270 assert(VA.isMemLoc());
272 if (StackPtr.Val == 0)
273 StackPtr = DAG.getRegister(StackReg, getPointerTy());
275 // Create the frame index object for this incoming parameter
276 // This guarantees that when allocating Local Area the firsts
277 // 16 bytes which are alwayes reserved won't be overwritten.
278 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
279 (16 + VA.getLocMemOffset()));
281 SDOperand PtrOff = DAG.getFrameIndex(FI,getPointerTy());
283 // emit ISD::STORE whichs stores the
284 // parameter value to a stack Location
285 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
289 // Transform all store nodes into one single node because
290 // all store nodes are independent of each other.
291 if (!MemOpChains.empty())
292 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
293 &MemOpChains[0], MemOpChains.size());
295 // Build a sequence of copy-to-reg nodes chained together with token
296 // chain and flag operands which copy the outgoing args into registers.
297 // The InFlag in necessary since all emited instructions must be
300 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
301 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first,
302 RegsToPass[i].second, InFlag);
303 InFlag = Chain.getValue(1);
306 // If the callee is a GlobalAddress node (quite common, every direct
307 // call is) turn it into a TargetGlobalAddress node so that legalize
309 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
310 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
312 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
313 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
315 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
316 // = Chain, Callee, Reg#1, Reg#2, ...
318 // Returns a chain & a flag for retval copy to use.
319 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
320 SmallVector<SDOperand, 8> Ops;
321 Ops.push_back(Chain);
322 Ops.push_back(Callee);
324 // Add argument registers to the end of the list so that they are
325 // known live into the call.
326 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
327 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
328 RegsToPass[i].second.getValueType()));
331 Ops.push_back(InFlag);
333 Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size());
334 InFlag = Chain.getValue(1);
336 // Create the CALLSEQ_END node.
337 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
339 Ops.push_back(Chain);
340 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
341 Ops.push_back(InFlag);
342 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
343 InFlag = Chain.getValue(1);
345 // Handle result values, copying them out of physregs into vregs that we
347 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
350 /// LowerCallResult - Lower the result values of an ISD::CALL into the
351 /// appropriate copies out of appropriate physical registers. This assumes that
352 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
353 /// being lowered. Returns a SDNode with the same number of values as the
355 SDNode *MipsTargetLowering::
356 LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
357 unsigned CallingConv, SelectionDAG &DAG) {
359 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
361 // Assign locations to each value returned by this call.
362 SmallVector<CCValAssign, 16> RVLocs;
363 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
365 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
366 SmallVector<SDOperand, 8> ResultVals;
368 // Copy all of the result registers out of their specified physreg.
369 for (unsigned i = 0; i != RVLocs.size(); ++i) {
370 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
371 RVLocs[i].getValVT(), InFlag).getValue(1);
372 InFlag = Chain.getValue(2);
373 ResultVals.push_back(Chain.getValue(0));
376 // Merge everything together with a MERGE_VALUES node.
377 ResultVals.push_back(Chain);
378 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
379 &ResultVals[0], ResultVals.size()).Val;
382 //===----------------------------------------------------------------------===//
383 // FORMAL_ARGUMENTS Calling Convention Implementation
384 //===----------------------------------------------------------------------===//
386 /// Mips custom FORMAL_ARGUMENTS implementation
387 SDOperand MipsTargetLowering::
388 LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG)
390 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
394 assert(0 && "Unsupported calling convention");
396 return LowerCCCArguments(Op, DAG);
400 /// LowerCCCArguments - transform physical registers into
401 /// virtual registers and generate load operations for
402 /// arguments places on the stack.
403 /// TODO: isVarArg, sret
404 SDOperand MipsTargetLowering::
405 LowerCCCArguments(SDOperand Op, SelectionDAG &DAG)
407 SDOperand Root = Op.getOperand(0);
408 MachineFunction &MF = DAG.getMachineFunction();
409 MachineFrameInfo *MFI = MF.getFrameInfo();
410 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
412 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
413 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
415 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
417 // Assign locations to all of the incoming arguments.
418 SmallVector<CCValAssign, 16> ArgLocs;
419 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
421 CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips);
422 SmallVector<SDOperand, 8> ArgValues;
425 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
427 CCValAssign &VA = ArgLocs[i];
429 // Arguments stored on registers
431 MVT::ValueType RegVT = VA.getLocVT();
432 TargetRegisterClass *RC;
434 if (RegVT == MVT::i32)
435 RC = Mips::CPURegsRegisterClass;
437 assert(0 && "support only Mips::CPURegsRegisterClass");
439 // Transform the arguments stored on
440 // physical registers into virtual ones
441 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
442 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
444 // If this is an 8 or 16-bit value, it is really passed promoted
445 // to 32 bits. Insert an assert[sz]ext to capture this, then
446 // truncate to the right size.
447 if (VA.getLocInfo() == CCValAssign::SExt)
448 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
449 DAG.getValueType(VA.getValVT()));
450 else if (VA.getLocInfo() == CCValAssign::ZExt)
451 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
452 DAG.getValueType(VA.getValVT()));
454 if (VA.getLocInfo() != CCValAssign::Full)
455 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
457 ArgValues.push_back(ArgValue);
459 // To meet ABI, when VARARGS are passed on registers, the registers
460 // must have their values written to the caller stack frame.
463 if (StackPtr.Val == 0)
464 StackPtr = DAG.getRegister(StackReg, getPointerTy());
466 // The stack pointer offset is relative to the caller stack frame.
467 // Since the real stack size is unknown here, a negative SPOffset
468 // is used so there's a way to adjust these offsets when the stack
469 // size get known (on EliminateFrameIndex). A dummy SPOffset is
470 // used instead of a direct negative address (which is recorded to
471 // be used on emitPrologue) to avoid mis-calc of the first stack
472 // offset on PEI::calculateFrameObjectOffsets.
473 // Arguments are always 32-bit.
474 int FI = MFI->CreateFixedObject(4, 0);
475 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
476 SDOperand PtrOff = DAG.getFrameIndex(FI, getPointerTy());
478 // emit ISD::STORE whichs stores the
479 // parameter value to a stack Location
480 ArgValues.push_back(DAG.getStore(Root, ArgValue, PtrOff, NULL, 0));
485 assert(VA.isMemLoc());
487 // The stack pointer offset is relative to the caller stack frame.
488 // Since the real stack size is unknown here, a negative SPOffset
489 // is used so there's a way to adjust these offsets when the stack
490 // size get known (on EliminateFrameIndex). A dummy SPOffset is
491 // used instead of a direct negative address (which is recorded to
492 // be used on emitPrologue) to avoid mis-calc of the first stack
493 // offset on PEI::calculateFrameObjectOffsets.
494 // Arguments are always 32-bit.
495 int FI = MFI->CreateFixedObject(4, 0);
496 MipsFI->recordLoadArgsFI(FI, -(4+(16+VA.getLocMemOffset())));
498 // Create load nodes to retrieve arguments from the stack
499 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
500 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
503 ArgValues.push_back(Root);
505 // Return the new list of results.
506 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
507 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
510 //===----------------------------------------------------------------------===//
511 // Return Value Calling Convention Implementation
512 //===----------------------------------------------------------------------===//
514 SDOperand MipsTargetLowering::
515 LowerRET(SDOperand Op, SelectionDAG &DAG)
517 // CCValAssign - represent the assignment of
518 // the return value to a location
519 SmallVector<CCValAssign, 16> RVLocs;
520 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
521 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
523 // CCState - Info about the registers and stack slot.
524 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
526 // Analize return values of ISD::RET
527 CCInfo.AnalyzeReturn(Op.Val, RetCC_Mips);
529 // If this is the first return lowered for this function, add
530 // the regs to the liveout set for the function.
531 if (DAG.getMachineFunction().liveout_empty()) {
532 for (unsigned i = 0; i != RVLocs.size(); ++i)
533 if (RVLocs[i].isRegLoc())
534 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg());
537 // The chain is always operand #0
538 SDOperand Chain = Op.getOperand(0);
541 // Copy the result values into the output registers.
542 for (unsigned i = 0; i != RVLocs.size(); ++i) {
543 CCValAssign &VA = RVLocs[i];
544 assert(VA.isRegLoc() && "Can only return in registers!");
546 // ISD::RET => ret chain, (regnum1,val1), ...
547 // So i*2+1 index only the regnums
548 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(),
549 Op.getOperand(i*2+1), Flag);
551 // guarantee that all emitted copies are
552 // stuck together, avoiding something bad
553 Flag = Chain.getValue(1);
556 // Return on Mips is always a "jr $ra"
558 return DAG.getNode(MipsISD::Ret, MVT::Other,
559 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
561 return DAG.getNode(MipsISD::Ret, MVT::Other,
562 Chain, DAG.getRegister(Mips::RA, MVT::i32));
565 //===----------------------------------------------------------------------===//
566 // Mips Inline Assembly Support
567 //===----------------------------------------------------------------------===//
569 /// getConstraintType - Given a constraint letter, return the type of
570 /// constraint it is for this target.
571 MipsTargetLowering::ConstraintType MipsTargetLowering::
572 getConstraintType(const std::string &Constraint) const
574 if (Constraint.size() == 1) {
575 // Mips specific constrainy
576 // GCC config/mips/constraints.md
578 // 'd' : An address register. Equivalent to r
579 // unless generating MIPS16 code.
580 // 'y' : Equivalent to r; retained for
581 // backwards compatibility.
583 switch (Constraint[0]) {
587 return C_RegisterClass;
591 return TargetLowering::getConstraintType(Constraint);
594 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
595 getRegForInlineAsmConstraint(const std::string &Constraint,
596 MVT::ValueType VT) const
598 if (Constraint.size() == 1) {
599 switch (Constraint[0]) {
601 return std::make_pair(0U, Mips::CPURegsRegisterClass);
605 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
608 std::vector<unsigned> MipsTargetLowering::
609 getRegClassForInlineAsmConstraint(const std::string &Constraint,
610 MVT::ValueType VT) const
612 if (Constraint.size() != 1)
613 return std::vector<unsigned>();
615 switch (Constraint[0]) {
618 // GCC Mips Constraint Letters
621 return make_vector<unsigned>(Mips::V0, Mips::V1, Mips::A0,
622 Mips::A1, Mips::A2, Mips::A3,
623 Mips::T0, Mips::T1, Mips::T2,
624 Mips::T3, Mips::T4, Mips::T5,
625 Mips::T6, Mips::T7, Mips::S0,
626 Mips::S1, Mips::S2, Mips::S3,
627 Mips::S4, Mips::S5, Mips::S6,
628 Mips::S7, Mips::T8, Mips::T9, 0);
631 return std::vector<unsigned>();