1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Bruno Cardoso Lopes and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
17 #include "MipsISelLowering.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsTargetMachine.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/SelectionDAGISel.h"
29 #include "llvm/CodeGen/SSARegMap.h"
30 #include "llvm/CodeGen/ValueTypes.h"
31 #include "llvm/Support/Debug.h"
37 const char *MipsTargetLowering::
38 getTargetNodeName(unsigned Opcode) const
42 case MipsISD::JmpLink : return "MipsISD::JmpLink";
43 case MipsISD::Hi : return "MipsISD::Hi";
44 case MipsISD::Lo : return "MipsISD::Lo";
45 case MipsISD::Ret : return "MipsISD::Ret";
46 case MipsISD::Add : return "MipsISD::Add";
47 case MipsISD::LoadAddr : return "MipsISD::LoadAddr";
48 default : return NULL;
53 MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
55 // Mips does not have i1 type, so use i32 for
56 // setcc operations results (slt, sgt, ...).
57 setSetCCResultType(MVT::i32);
58 setSetCCResultContents(ZeroOrOneSetCCResult);
60 // Set up the register classes
61 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
64 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
65 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
66 setOperationAction(ISD::RET, MVT::Other, Custom);
68 // Load extented operations for i1 types must be promoted
69 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
70 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
71 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
73 // Store operations for i1 types must be promoted
74 setStoreXAction(MVT::i1, Promote);
76 // Mips does not have these NodeTypes below.
77 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
78 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
79 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
80 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
81 setOperationAction(ISD::SELECT, MVT::i32, Expand);
82 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
84 // Mips not supported intrinsics.
85 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
86 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
87 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
89 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
90 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
91 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
92 setOperationAction(ISD::ROTL , MVT::i32, Expand);
93 setOperationAction(ISD::ROTR , MVT::i32, Expand);
94 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
96 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
97 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
98 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
100 // We don't have line number support yet.
101 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
102 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
103 setOperationAction(ISD::LABEL, MVT::Other, Expand);
105 // Use the default for now
106 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
107 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
109 setStackPointerRegisterToSaveRestore(Mips::SP);
110 computeRegisterProperties();
114 SDOperand MipsTargetLowering::
115 LowerOperation(SDOperand Op, SelectionDAG &DAG)
117 switch (Op.getOpcode())
119 case ISD::CALL: return LowerCALL(Op, DAG);
120 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
121 case ISD::RET: return LowerRET(Op, DAG);
122 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
123 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
128 //===----------------------------------------------------------------------===//
129 // Lower helper functions
130 //===----------------------------------------------------------------------===//
132 // AddLiveIn - This helper function adds the specified physical register to the
133 // MachineFunction as a live in value. It also creates a corresponding
134 // virtual register for it.
136 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
138 assert(RC->contains(PReg) && "Not the correct regclass!");
139 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
140 MF.addLiveIn(PReg, VReg);
144 //===----------------------------------------------------------------------===//
145 // Misc Lower Operation implementation
146 //===----------------------------------------------------------------------===//
147 SDOperand MipsTargetLowering::
148 LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG)
151 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
153 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
155 // On PIC code global addresses are loaded with "la" instruction
156 if (!(getTargetMachine().getRelocationModel() == Reloc::PIC_)) {
157 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::i32, MVT::Flag);
158 SDOperand Ops[] = { GA };
160 SDOperand Hi = DAG.getNode(MipsISD::Hi, VTs, 2, Ops, 1);
161 SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
163 SDOperand InFlag = Hi.getValue(1);
164 ResNode = DAG.getNode(MipsISD::Add, MVT::i32, Lo, Hi, InFlag);
166 ResNode = DAG.getNode(MipsISD::LoadAddr, MVT::i32, GA);
171 SDOperand MipsTargetLowering::
172 LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG)
174 assert(0 && "TLS not implemented for MIPS.");
177 //===----------------------------------------------------------------------===//
178 // Calling Convention Implementation
180 // The lower operations present on calling convention works on this order:
181 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
182 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
183 // LowerRET (virt regs --> phys regs)
184 // LowerCALL (phys regs --> virt regs)
186 //===----------------------------------------------------------------------===//
188 #include "MipsGenCallingConv.inc"
190 //===----------------------------------------------------------------------===//
191 // CALL Calling Convention Implementation
192 //===----------------------------------------------------------------------===//
194 /// Mips custom CALL implementation
195 SDOperand MipsTargetLowering::
196 LowerCALL(SDOperand Op, SelectionDAG &DAG)
198 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
200 // By now, only CallingConv::C implemented
204 assert(0 && "Unsupported calling convention");
205 case CallingConv::Fast:
207 return LowerCCCCallTo(Op, DAG, CallingConv);
211 /// LowerCCCCallTo - functions arguments are copied from virtual
212 /// regs to (physical regs)/(stack frame), CALLSEQ_START and
213 /// CALLSEQ_END are emitted.
214 /// TODO: isVarArg, isTailCall, sret, GOT, linkage types.
215 SDOperand MipsTargetLowering::
216 LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
218 MachineFunction &MF = DAG.getMachineFunction();
219 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
221 SDOperand Chain = Op.getOperand(0);
222 SDOperand Callee = Op.getOperand(4);
223 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
225 MachineFrameInfo *MFI = MF.getFrameInfo();
227 // Analyze operands of the call, assigning locations to each operand.
228 SmallVector<CCValAssign, 16> ArgLocs;
229 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
231 // To meet ABI, Mips must always allocate 16 bytes on
232 // the stack (even if less than 4 are used as arguments)
233 int VTsize = MVT::getSizeInBits(MVT::i32)/8;
234 MFI->CreateFixedObject(VTsize, (VTsize*3));
236 CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips);
238 // Get a count of how many bytes are to be pushed on the stack.
239 unsigned NumBytes = CCInfo.getNextStackOffset();
240 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
243 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
244 SmallVector<SDOperand, 8> MemOpChains;
247 unsigned LastStackLoc=0;
249 // Walk the register/memloc assignments, inserting copies/loads.
250 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
251 CCValAssign &VA = ArgLocs[i];
253 // Arguments start after the 5 first operands of ISD::CALL
254 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
256 // Promote the value if needed.
257 switch (VA.getLocInfo()) {
258 default: assert(0 && "Unknown loc info!");
259 case CCValAssign::Full: break;
260 case CCValAssign::SExt:
261 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
263 case CCValAssign::ZExt:
264 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
266 case CCValAssign::AExt:
267 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
271 // Arguments that can be passed on register,
272 // must be kept at RegsToPass vector
274 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
277 assert(VA.isMemLoc());
279 if (StackPtr.Val == 0)
280 StackPtr = DAG.getRegister(StackReg, getPointerTy());
282 // Create the frame index object for this incoming parameter
283 // This guarantees that when allocating Local Area the firsts
284 // 16 bytes which are alwayes reserved won't be overwritten.
285 LastStackLoc = (16 + VA.getLocMemOffset());
286 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
289 SDOperand PtrOff = DAG.getFrameIndex(FI,getPointerTy());
291 // emit ISD::STORE whichs stores the
292 // parameter value to a stack Location
293 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
297 // Create a stack location to hold GP when PIC is used
298 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
299 LastStackLoc = (!LastStackLoc) ? (16) : (LastStackLoc+4);
300 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
301 MFI->CreateFixedObject(4, LastStackLoc);
302 MipsFI->setGPStackOffset(LastStackLoc);
305 // Transform all store nodes into one single node because
306 // all store nodes are independent of each other.
307 if (!MemOpChains.empty())
308 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
309 &MemOpChains[0], MemOpChains.size());
311 // Build a sequence of copy-to-reg nodes chained together with token
312 // chain and flag operands which copy the outgoing args into registers.
313 // The InFlag in necessary since all emited instructions must be
316 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
317 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first,
318 RegsToPass[i].second, InFlag);
319 InFlag = Chain.getValue(1);
322 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
323 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
324 // node so that legalize doesn't hack it. Otherwise we have an indirect call,
325 // if PIC is used, the call must use register GP
326 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
327 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
328 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
329 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
331 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
332 // = Chain, Callee, Reg#1, Reg#2, ...
334 // Returns a chain & a flag for retval copy to use.
335 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
336 SmallVector<SDOperand, 8> Ops;
337 Ops.push_back(Chain);
338 Ops.push_back(Callee);
340 // Add argument registers to the end of the list so that they are
341 // known live into the call.
342 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
343 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
344 RegsToPass[i].second.getValueType()));
347 Ops.push_back(InFlag);
349 Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size());
350 InFlag = Chain.getValue(1);
352 // Create the CALLSEQ_END node.
353 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
355 Ops.push_back(Chain);
356 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
357 Ops.push_back(InFlag);
358 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
359 InFlag = Chain.getValue(1);
361 // Handle result values, copying them out of physregs into vregs that we
363 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
366 /// LowerCallResult - Lower the result values of an ISD::CALL into the
367 /// appropriate copies out of appropriate physical registers. This assumes that
368 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
369 /// being lowered. Returns a SDNode with the same number of values as the
371 SDNode *MipsTargetLowering::
372 LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
373 unsigned CallingConv, SelectionDAG &DAG) {
375 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
377 // Assign locations to each value returned by this call.
378 SmallVector<CCValAssign, 16> RVLocs;
379 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
381 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
382 SmallVector<SDOperand, 8> ResultVals;
384 // Copy all of the result registers out of their specified physreg.
385 for (unsigned i = 0; i != RVLocs.size(); ++i) {
386 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
387 RVLocs[i].getValVT(), InFlag).getValue(1);
388 InFlag = Chain.getValue(2);
389 ResultVals.push_back(Chain.getValue(0));
392 // Merge everything together with a MERGE_VALUES node.
393 ResultVals.push_back(Chain);
394 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
395 &ResultVals[0], ResultVals.size()).Val;
398 //===----------------------------------------------------------------------===//
399 // FORMAL_ARGUMENTS Calling Convention Implementation
400 //===----------------------------------------------------------------------===//
402 /// Mips custom FORMAL_ARGUMENTS implementation
403 SDOperand MipsTargetLowering::
404 LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG)
406 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
410 assert(0 && "Unsupported calling convention");
412 return LowerCCCArguments(Op, DAG);
416 /// LowerCCCArguments - transform physical registers into
417 /// virtual registers and generate load operations for
418 /// arguments places on the stack.
419 /// TODO: isVarArg, sret
420 SDOperand MipsTargetLowering::
421 LowerCCCArguments(SDOperand Op, SelectionDAG &DAG)
423 SDOperand Root = Op.getOperand(0);
424 MachineFunction &MF = DAG.getMachineFunction();
425 MachineFrameInfo *MFI = MF.getFrameInfo();
426 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
428 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
429 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
431 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
433 // Assign locations to all of the incoming arguments.
434 SmallVector<CCValAssign, 16> ArgLocs;
435 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
437 CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips);
438 SmallVector<SDOperand, 8> ArgValues;
441 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
443 CCValAssign &VA = ArgLocs[i];
445 // Arguments stored on registers
447 MVT::ValueType RegVT = VA.getLocVT();
448 TargetRegisterClass *RC;
450 if (RegVT == MVT::i32)
451 RC = Mips::CPURegsRegisterClass;
453 assert(0 && "support only Mips::CPURegsRegisterClass");
455 // Transform the arguments stored on
456 // physical registers into virtual ones
457 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
458 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
460 // If this is an 8 or 16-bit value, it is really passed promoted
461 // to 32 bits. Insert an assert[sz]ext to capture this, then
462 // truncate to the right size.
463 if (VA.getLocInfo() == CCValAssign::SExt)
464 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
465 DAG.getValueType(VA.getValVT()));
466 else if (VA.getLocInfo() == CCValAssign::ZExt)
467 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
468 DAG.getValueType(VA.getValVT()));
470 if (VA.getLocInfo() != CCValAssign::Full)
471 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
473 ArgValues.push_back(ArgValue);
475 // To meet ABI, when VARARGS are passed on registers, the registers
476 // must have their values written to the caller stack frame.
479 if (StackPtr.Val == 0)
480 StackPtr = DAG.getRegister(StackReg, getPointerTy());
482 // The stack pointer offset is relative to the caller stack frame.
483 // Since the real stack size is unknown here, a negative SPOffset
484 // is used so there's a way to adjust these offsets when the stack
485 // size get known (on EliminateFrameIndex). A dummy SPOffset is
486 // used instead of a direct negative address (which is recorded to
487 // be used on emitPrologue) to avoid mis-calc of the first stack
488 // offset on PEI::calculateFrameObjectOffsets.
489 // Arguments are always 32-bit.
490 int FI = MFI->CreateFixedObject(4, 0);
491 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
492 SDOperand PtrOff = DAG.getFrameIndex(FI, getPointerTy());
494 // emit ISD::STORE whichs stores the
495 // parameter value to a stack Location
496 ArgValues.push_back(DAG.getStore(Root, ArgValue, PtrOff, NULL, 0));
501 assert(VA.isMemLoc());
503 // The stack pointer offset is relative to the caller stack frame.
504 // Since the real stack size is unknown here, a negative SPOffset
505 // is used so there's a way to adjust these offsets when the stack
506 // size get known (on EliminateFrameIndex). A dummy SPOffset is
507 // used instead of a direct negative address (which is recorded to
508 // be used on emitPrologue) to avoid mis-calc of the first stack
509 // offset on PEI::calculateFrameObjectOffsets.
510 // Arguments are always 32-bit.
511 int FI = MFI->CreateFixedObject(4, 0);
512 MipsFI->recordLoadArgsFI(FI, -(4+(16+VA.getLocMemOffset())));
514 // Create load nodes to retrieve arguments from the stack
515 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
516 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
519 ArgValues.push_back(Root);
521 // Return the new list of results.
522 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
523 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
526 //===----------------------------------------------------------------------===//
527 // Return Value Calling Convention Implementation
528 //===----------------------------------------------------------------------===//
530 SDOperand MipsTargetLowering::
531 LowerRET(SDOperand Op, SelectionDAG &DAG)
533 // CCValAssign - represent the assignment of
534 // the return value to a location
535 SmallVector<CCValAssign, 16> RVLocs;
536 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
537 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
539 // CCState - Info about the registers and stack slot.
540 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
542 // Analize return values of ISD::RET
543 CCInfo.AnalyzeReturn(Op.Val, RetCC_Mips);
545 // If this is the first return lowered for this function, add
546 // the regs to the liveout set for the function.
547 if (DAG.getMachineFunction().liveout_empty()) {
548 for (unsigned i = 0; i != RVLocs.size(); ++i)
549 if (RVLocs[i].isRegLoc())
550 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg());
553 // The chain is always operand #0
554 SDOperand Chain = Op.getOperand(0);
557 // Copy the result values into the output registers.
558 for (unsigned i = 0; i != RVLocs.size(); ++i) {
559 CCValAssign &VA = RVLocs[i];
560 assert(VA.isRegLoc() && "Can only return in registers!");
562 // ISD::RET => ret chain, (regnum1,val1), ...
563 // So i*2+1 index only the regnums
564 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
566 // guarantee that all emitted copies are
567 // stuck together, avoiding something bad
568 Flag = Chain.getValue(1);
571 // Return on Mips is always a "jr $ra"
573 return DAG.getNode(MipsISD::Ret, MVT::Other,
574 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
576 return DAG.getNode(MipsISD::Ret, MVT::Other,
577 Chain, DAG.getRegister(Mips::RA, MVT::i32));
580 //===----------------------------------------------------------------------===//
581 // Mips Inline Assembly Support
582 //===----------------------------------------------------------------------===//
584 /// getConstraintType - Given a constraint letter, return the type of
585 /// constraint it is for this target.
586 MipsTargetLowering::ConstraintType MipsTargetLowering::
587 getConstraintType(const std::string &Constraint) const
589 if (Constraint.size() == 1) {
590 // Mips specific constrainy
591 // GCC config/mips/constraints.md
593 // 'd' : An address register. Equivalent to r
594 // unless generating MIPS16 code.
595 // 'y' : Equivalent to r; retained for
596 // backwards compatibility.
598 switch (Constraint[0]) {
602 return C_RegisterClass;
606 return TargetLowering::getConstraintType(Constraint);
609 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
610 getRegForInlineAsmConstraint(const std::string &Constraint,
611 MVT::ValueType VT) const
613 if (Constraint.size() == 1) {
614 switch (Constraint[0]) {
616 return std::make_pair(0U, Mips::CPURegsRegisterClass);
620 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
623 std::vector<unsigned> MipsTargetLowering::
624 getRegClassForInlineAsmConstraint(const std::string &Constraint,
625 MVT::ValueType VT) const
627 if (Constraint.size() != 1)
628 return std::vector<unsigned>();
630 switch (Constraint[0]) {
633 // GCC Mips Constraint Letters
636 return make_vector<unsigned>(Mips::V0, Mips::V1, Mips::A0,
637 Mips::A1, Mips::A2, Mips::A3,
638 Mips::T0, Mips::T1, Mips::T2,
639 Mips::T3, Mips::T4, Mips::T5,
640 Mips::T6, Mips::T7, Mips::S0,
641 Mips::S1, Mips::S2, Mips::S3,
642 Mips::S4, Mips::S5, Mips::S6,
643 Mips::S7, Mips::T8, Mips::T9, 0);
646 return std::vector<unsigned>();