1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
17 #include "MipsISelLowering.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsTargetMachine.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
39 const char *MipsTargetLowering::
40 getTargetNodeName(unsigned Opcode) const
44 case MipsISD::JmpLink : return "MipsISD::JmpLink";
45 case MipsISD::Hi : return "MipsISD::Hi";
46 case MipsISD::Lo : return "MipsISD::Lo";
47 case MipsISD::GPRel : return "MipsISD::GPRel";
48 case MipsISD::Ret : return "MipsISD::Ret";
49 case MipsISD::SelectCC : return "MipsISD::SelectCC";
50 case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC";
51 case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
52 case MipsISD::FPCmp : return "MipsISD::FPCmp";
53 default : return NULL;
58 MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
60 Subtarget = &TM.getSubtarget<MipsSubtarget>();
62 // Mips does not have i1 type, so use i32 for
63 // setcc operations results (slt, sgt, ...).
64 setSetCCResultContents(ZeroOrOneSetCCResult);
66 // JumpTable targets must use GOT when using PIC_
67 setUsesGlobalOffsetTable(true);
69 // Set up the register classes
70 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
72 // When dealing with single precision only, use libcalls
73 if (!Subtarget->isSingleFloat()) {
74 addRegisterClass(MVT::f32, Mips::AFGR32RegisterClass);
75 if (!Subtarget->isFP64bit())
76 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
78 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
81 addLegalFPImmediate(APFloat(+0.0f));
83 // Load extented operations for i1 types must be promoted
84 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
85 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
86 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
88 // Used by legalize types to correctly generate the setcc result.
89 // Without this, every float setcc comes with a AND with the result,
90 // we don't want this, since the fpcmp result goes to a flag register,
91 // which is used implicitly by brcond and select operations.
92 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
94 // Mips Custom Operations
95 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
96 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
97 setOperationAction(ISD::RET, MVT::Other, Custom);
98 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
99 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
100 setOperationAction(ISD::SELECT, MVT::f32, Custom);
101 setOperationAction(ISD::SELECT, MVT::i32, Custom);
102 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
103 setOperationAction(ISD::SETCC, MVT::f32, Custom);
104 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
106 // We custom lower AND to handle the case where the DAG contain 'ands'
107 // setcc results with fp operands. This is necessary since the result
108 // from these are in a flag register (FCR31).
109 setOperationAction(ISD::AND, MVT::i32, Custom);
111 // Operations not directly supported by Mips.
112 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
113 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
114 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
115 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
116 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
118 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
119 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
120 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
121 setOperationAction(ISD::ROTL, MVT::i32, Expand);
122 setOperationAction(ISD::ROTR, MVT::i32, Expand);
123 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
124 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
125 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
126 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
128 // We don't have line number support yet.
129 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
130 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
131 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
132 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
134 // Use the default for now
135 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
136 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
137 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
139 if (Subtarget->isSingleFloat())
140 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
142 if (!Subtarget->hasSEInReg()) {
143 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
144 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
147 setStackPointerRegisterToSaveRestore(Mips::SP);
148 computeRegisterProperties();
152 MVT MipsTargetLowering::getSetCCResultType(const SDValue &) const {
157 SDValue MipsTargetLowering::
158 LowerOperation(SDValue Op, SelectionDAG &DAG)
160 switch (Op.getOpcode())
162 case ISD::AND: return LowerAND(Op, DAG);
163 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
164 case ISD::CALL: return LowerCALL(Op, DAG);
165 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
166 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
167 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
168 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
169 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
170 case ISD::RET: return LowerRET(Op, DAG);
171 case ISD::SELECT: return LowerSELECT(Op, DAG);
172 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
173 case ISD::SETCC: return LowerSETCC(Op, DAG);
178 //===----------------------------------------------------------------------===//
179 // Lower helper functions
180 //===----------------------------------------------------------------------===//
182 // AddLiveIn - This helper function adds the specified physical register to the
183 // MachineFunction as a live in value. It also creates a corresponding
184 // virtual register for it.
186 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
188 assert(RC->contains(PReg) && "Not the correct regclass!");
189 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
190 MF.getRegInfo().addLiveIn(PReg, VReg);
194 // A address must be loaded from a small section if its size is less than the
195 // small section size threshold. Data in this section must be addressed using
197 bool MipsTargetLowering::IsInSmallSection(unsigned Size) {
198 return (Size > 0 && (Size <= Subtarget->getSSectionThreshold()));
201 // Discover if this global address can be placed into small data/bss section.
202 bool MipsTargetLowering::IsGlobalInSmallSection(GlobalValue *GV)
204 const TargetData *TD = getTargetData();
205 const GlobalVariable *GVA = dyn_cast<GlobalVariable>(GV);
210 const Type *Ty = GV->getType()->getElementType();
211 unsigned Size = TD->getABITypeSize(Ty);
213 // if this is a internal constant string, there is a special
214 // section for it, but not in small data/bss.
215 if (GVA->hasInitializer() && GV->hasInternalLinkage()) {
216 Constant *C = GVA->getInitializer();
217 const ConstantArray *CVA = dyn_cast<ConstantArray>(C);
218 if (CVA && CVA->isCString())
222 return IsInSmallSection(Size);
225 // Get fp branch code (not opcode) from condition code.
226 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
227 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
228 return Mips::BRANCH_T;
230 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
231 return Mips::BRANCH_F;
233 return Mips::BRANCH_INVALID;
236 static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) {
239 assert(0 && "Unknown branch code");
240 case Mips::BRANCH_T : return Mips::BC1T;
241 case Mips::BRANCH_F : return Mips::BC1F;
242 case Mips::BRANCH_TL : return Mips::BC1TL;
243 case Mips::BRANCH_FL : return Mips::BC1FL;
247 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
249 default: assert(0 && "Unknown fp condition code!");
251 case ISD::SETOEQ: return Mips::FCOND_EQ;
252 case ISD::SETUNE: return Mips::FCOND_OGL;
254 case ISD::SETOLT: return Mips::FCOND_OLT;
256 case ISD::SETOGT: return Mips::FCOND_OGT;
258 case ISD::SETOLE: return Mips::FCOND_OLE;
260 case ISD::SETOGE: return Mips::FCOND_OGE;
261 case ISD::SETULT: return Mips::FCOND_ULT;
262 case ISD::SETULE: return Mips::FCOND_ULE;
263 case ISD::SETUGT: return Mips::FCOND_UGT;
264 case ISD::SETUGE: return Mips::FCOND_UGE;
265 case ISD::SETUO: return Mips::FCOND_UN;
266 case ISD::SETO: return Mips::FCOND_OR;
268 case ISD::SETONE: return Mips::FCOND_NEQ;
269 case ISD::SETUEQ: return Mips::FCOND_UEQ;
274 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
275 MachineBasicBlock *BB)
277 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
278 bool isFPCmp = false;
280 switch (MI->getOpcode()) {
281 default: assert(false && "Unexpected instr type to insert");
282 case Mips::Select_FCC:
283 case Mips::Select_FCC_SO32:
284 case Mips::Select_FCC_AS32:
285 case Mips::Select_FCC_D32:
286 isFPCmp = true; // FALL THROUGH
287 case Mips::Select_CC:
288 case Mips::Select_CC_SO32:
289 case Mips::Select_CC_AS32:
290 case Mips::Select_CC_D32: {
291 // To "insert" a SELECT_CC instruction, we actually have to insert the
292 // diamond control-flow pattern. The incoming instruction knows the
293 // destination vreg to set, the condition code register to branch on, the
294 // true/false values to select between, and a branch opcode to use.
295 const BasicBlock *LLVM_BB = BB->getBasicBlock();
296 MachineFunction::iterator It = BB;
303 // bNE r1, r0, copy1MBB
304 // fallthrough --> copy0MBB
305 MachineBasicBlock *thisMBB = BB;
306 MachineFunction *F = BB->getParent();
307 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
308 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
310 // Emit the right instruction according to the type of the operands compared
312 // Find the condiction code present in the setcc operation.
313 Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm();
314 // Get the branch opcode from the branch code.
315 unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC));
316 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
318 BuildMI(BB, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
319 .addReg(Mips::ZERO).addMBB(sinkMBB);
321 F->insert(It, copy0MBB);
322 F->insert(It, sinkMBB);
323 // Update machine-CFG edges by first adding all successors of the current
324 // block to the new block which will contain the Phi node for the select.
325 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
326 e = BB->succ_end(); i != e; ++i)
327 sinkMBB->addSuccessor(*i);
328 // Next, remove all successors of the current block, and add the true
329 // and fallthrough blocks as its successors.
330 while(!BB->succ_empty())
331 BB->removeSuccessor(BB->succ_begin());
332 BB->addSuccessor(copy0MBB);
333 BB->addSuccessor(sinkMBB);
337 // # fallthrough to sinkMBB
340 // Update machine-CFG edges
341 BB->addSuccessor(sinkMBB);
344 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
347 BuildMI(BB, TII->get(Mips::PHI), MI->getOperand(0).getReg())
348 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
349 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
351 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
357 //===----------------------------------------------------------------------===//
358 // Misc Lower Operation implementation
359 //===----------------------------------------------------------------------===//
361 SDValue MipsTargetLowering::
362 LowerAND(SDValue Op, SelectionDAG &DAG)
364 SDValue LHS = Op.getOperand(0);
365 SDValue RHS = Op.getOperand(1);
367 if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp)
370 SDValue True = DAG.getConstant(1, MVT::i32);
371 SDValue False = DAG.getConstant(0, MVT::i32);
373 SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, True.getValueType(),
374 LHS, True, False, LHS.getOperand(2));
375 SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, True.getValueType(),
376 RHS, True, False, RHS.getOperand(2));
378 return DAG.getNode(ISD::AND, MVT::i32, LSEL, RSEL);
381 SDValue MipsTargetLowering::
382 LowerBRCOND(SDValue Op, SelectionDAG &DAG)
384 // The first operand is the chain, the second is the condition, the third is
385 // the block to branch to if the condition is true.
386 SDValue Chain = Op.getOperand(0);
387 SDValue Dest = Op.getOperand(2);
389 if (Op.getOperand(1).getOpcode() != MipsISD::FPCmp)
392 SDValue CondRes = Op.getOperand(1);
393 SDValue CCNode = CondRes.getOperand(2);
394 Mips::CondCode CC = (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getValue();
395 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
397 return DAG.getNode(MipsISD::FPBrcond, Op.getValueType(), Chain, BrCode,
401 SDValue MipsTargetLowering::
402 LowerSETCC(SDValue Op, SelectionDAG &DAG)
404 // The operands to this are the left and right operands to compare (ops #0,
405 // and #1) and the condition code to compare them with (op #2) as a
407 SDValue LHS = Op.getOperand(0);
408 SDValue RHS = Op.getOperand(1);
410 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
412 return DAG.getNode(MipsISD::FPCmp, Op.getValueType(), LHS, RHS,
413 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
416 SDValue MipsTargetLowering::
417 LowerSELECT(SDValue Op, SelectionDAG &DAG)
419 SDValue Cond = Op.getOperand(0);
420 SDValue True = Op.getOperand(1);
421 SDValue False = Op.getOperand(2);
423 // if the incomming condition comes from fpcmp, the select
424 // operation must use FPSelectCC, otherwise SelectCC.
425 if (Cond.getOpcode() != MipsISD::FPCmp)
426 return DAG.getNode(MipsISD::SelectCC, True.getValueType(),
429 SDValue CCNode = Cond.getOperand(2);
430 return DAG.getNode(MipsISD::FPSelectCC, True.getValueType(),
431 Cond, True, False, CCNode);
434 SDValue MipsTargetLowering::
435 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG)
437 SDValue LHS = Op.getOperand(0);
438 SDValue RHS = Op.getOperand(1);
439 SDValue True = Op.getOperand(2);
440 SDValue False = Op.getOperand(3);
441 SDValue CC = Op.getOperand(4);
443 SDValue SetCCRes = DAG.getNode(ISD::SETCC, LHS.getValueType(), LHS, RHS, CC);
444 return DAG.getNode(MipsISD::SelectCC, True.getValueType(),
445 SetCCRes, True, False);
448 SDValue MipsTargetLowering::
449 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
451 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
452 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
454 if (!Subtarget->hasABICall()) {
455 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
456 SDValue Ops[] = { GA };
457 // %gp_rel relocation
458 if (!isa<Function>(GV) && IsGlobalInSmallSection(GV)) {
459 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, VTs, 1, Ops, 1);
460 SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
461 return DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
463 // %hi/%lo relocation
464 SDValue HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
465 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
466 return DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
468 } else { // Abicall relocations, TODO: make this cleaner.
469 SDValue ResNode = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0);
470 // On functions and global targets not internal linked only
471 // a load from got/GP is necessary for PIC to work.
472 if (!GV->hasInternalLinkage() || isa<Function>(GV))
474 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
475 return DAG.getNode(ISD::ADD, MVT::i32, ResNode, Lo);
478 assert(0 && "Dont know how to handle GlobalAddress");
482 SDValue MipsTargetLowering::
483 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
485 assert(0 && "TLS not implemented for MIPS.");
486 return SDValue(); // Not reached
489 SDValue MipsTargetLowering::
490 LowerJumpTable(SDValue Op, SelectionDAG &DAG)
495 MVT PtrVT = Op.getValueType();
496 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
497 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
499 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
500 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
501 SDValue Ops[] = { JTI };
502 HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
503 } else // Emit Load from Global Pointer
504 HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), JTI, NULL, 0);
506 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, JTI);
507 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
512 SDValue MipsTargetLowering::
513 LowerConstantPool(SDValue Op, SelectionDAG &DAG)
516 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
517 Constant *C = N->getConstVal();
518 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
521 // FIXME: we should reference the constant pool using small data sections,
522 // but the asm printer currently doens't support this feature without
523 // hacking it. This feature should come soon so we can uncomment the
525 //if (!Subtarget->hasABICall() &&
526 // IsInSmallSection(getTargetData()->getABITypeSize(C->getType()))) {
527 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
528 // SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
529 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
530 //} else { // %hi/%lo relocation
531 SDValue HiPart = DAG.getNode(MipsISD::Hi, MVT::i32, CP);
532 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, CP);
533 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
539 //===----------------------------------------------------------------------===//
540 // Calling Convention Implementation
542 // The lower operations present on calling convention works on this order:
543 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
544 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
545 // LowerRET (virt regs --> phys regs)
546 // LowerCALL (phys regs --> virt regs)
548 //===----------------------------------------------------------------------===//
550 #include "MipsGenCallingConv.inc"
552 //===----------------------------------------------------------------------===//
553 // CALL Calling Convention Implementation
554 //===----------------------------------------------------------------------===//
556 /// Mips custom CALL implementation
557 SDValue MipsTargetLowering::
558 LowerCALL(SDValue Op, SelectionDAG &DAG)
560 unsigned CallingConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
562 // By now, only CallingConv::C implemented
563 switch (CallingConv) {
565 assert(0 && "Unsupported calling convention");
566 case CallingConv::Fast:
568 return LowerCCCCallTo(Op, DAG, CallingConv);
572 /// LowerCCCCallTo - functions arguments are copied from virtual
573 /// regs to (physical regs)/(stack frame), CALLSEQ_START and
574 /// CALLSEQ_END are emitted.
575 /// TODO: isVarArg, isTailCall.
576 SDValue MipsTargetLowering::
577 LowerCCCCallTo(SDValue Op, SelectionDAG &DAG, unsigned CC)
579 MachineFunction &MF = DAG.getMachineFunction();
581 SDValue Chain = Op.getOperand(0);
582 SDValue Callee = Op.getOperand(4);
583 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
585 MachineFrameInfo *MFI = MF.getFrameInfo();
587 // Analyze operands of the call, assigning locations to each operand.
588 SmallVector<CCValAssign, 16> ArgLocs;
589 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
591 // To meet O32 ABI, Mips must always allocate 16 bytes on
592 // the stack (even if less than 4 are used as arguments)
593 if (Subtarget->isABI_O32()) {
594 int VTsize = MVT(MVT::i32).getSizeInBits()/8;
595 MFI->CreateFixedObject(VTsize, (VTsize*3));
598 CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips);
600 // Get a count of how many bytes are to be pushed on the stack.
601 unsigned NumBytes = CCInfo.getNextStackOffset();
602 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
605 // With EABI is it possible to have 16 args on registers.
606 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
607 SmallVector<SDValue, 8> MemOpChains;
609 // First/LastArgStackLoc contains the first/last
610 // "at stack" argument location.
611 int LastArgStackLoc = 0;
612 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
614 // Walk the register/memloc assignments, inserting copies/loads.
615 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
616 CCValAssign &VA = ArgLocs[i];
618 // Arguments start after the 5 first operands of ISD::CALL
619 SDValue Arg = Op.getOperand(5+2*VA.getValNo());
621 // Promote the value if needed.
622 switch (VA.getLocInfo()) {
623 default: assert(0 && "Unknown loc info!");
624 case CCValAssign::Full: break;
625 case CCValAssign::SExt:
626 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
628 case CCValAssign::ZExt:
629 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
631 case CCValAssign::AExt:
632 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
636 // Arguments that can be passed on register must be kept at
639 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
643 // Register cant get to this point...
644 assert(VA.isMemLoc());
646 // Create the frame index object for this incoming parameter
647 // This guarantees that when allocating Local Area the firsts
648 // 16 bytes which are alwayes reserved won't be overwritten
649 // if O32 ABI is used. For EABI the first address is zero.
650 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
651 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
654 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
656 // emit ISD::STORE whichs stores the
657 // parameter value to a stack Location
658 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
661 // Transform all store nodes into one single node because all store
662 // nodes are independent of each other.
663 if (!MemOpChains.empty())
664 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
665 &MemOpChains[0], MemOpChains.size());
667 // Build a sequence of copy-to-reg nodes chained together with token
668 // chain and flag operands which copy the outgoing args into registers.
669 // The InFlag in necessary since all emited instructions must be
672 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
673 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first,
674 RegsToPass[i].second, InFlag);
675 InFlag = Chain.getValue(1);
678 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
679 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
680 // node so that legalize doesn't hack it.
681 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
682 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
683 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
684 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
687 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
688 // = Chain, Callee, Reg#1, Reg#2, ...
690 // Returns a chain & a flag for retval copy to use.
691 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
692 SmallVector<SDValue, 8> Ops;
693 Ops.push_back(Chain);
694 Ops.push_back(Callee);
696 // Add argument registers to the end of the list so that they are
697 // known live into the call.
698 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
699 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
700 RegsToPass[i].second.getValueType()));
703 Ops.push_back(InFlag);
705 Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size());
706 InFlag = Chain.getValue(1);
708 // Create the CALLSEQ_END node.
709 Chain = DAG.getCALLSEQ_END(Chain,
710 DAG.getConstant(NumBytes, getPointerTy()),
711 DAG.getConstant(0, getPointerTy()),
713 InFlag = Chain.getValue(1);
715 // Create a stack location to hold GP when PIC is used. This stack
716 // location is used on function prologue to save GP and also after all
717 // emited CALL's to restore GP.
718 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
719 // Function can have an arbitrary number of calls, so
720 // hold the LastArgStackLoc with the biggest offset.
722 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
723 if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
724 LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
725 // Create the frame index only once. SPOffset here can be anything
726 // (this will be fixed on processFunctionBeforeFrameFinalized)
727 if (MipsFI->getGPStackOffset() == -1) {
728 FI = MFI->CreateFixedObject(4, 0);
731 MipsFI->setGPStackOffset(LastArgStackLoc);
735 FI = MipsFI->getGPFI();
736 SDValue FIN = DAG.getFrameIndex(FI,getPointerTy());
737 SDValue GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0);
738 Chain = GPLoad.getValue(1);
739 Chain = DAG.getCopyToReg(Chain, DAG.getRegister(Mips::GP, MVT::i32),
740 GPLoad, SDValue(0,0));
741 InFlag = Chain.getValue(1);
744 // Handle result values, copying them out of physregs into vregs that we
746 return SDValue(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
749 /// LowerCallResult - Lower the result values of an ISD::CALL into the
750 /// appropriate copies out of appropriate physical registers. This assumes that
751 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
752 /// being lowered. Returns a SDNode with the same number of values as the
754 SDNode *MipsTargetLowering::
755 LowerCallResult(SDValue Chain, SDValue InFlag, SDNode *TheCall,
756 unsigned CallingConv, SelectionDAG &DAG) {
758 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
760 // Assign locations to each value returned by this call.
761 SmallVector<CCValAssign, 16> RVLocs;
762 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
764 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
765 SmallVector<SDValue, 8> ResultVals;
767 // Copy all of the result registers out of their specified physreg.
768 for (unsigned i = 0; i != RVLocs.size(); ++i) {
769 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
770 RVLocs[i].getValVT(), InFlag).getValue(1);
771 InFlag = Chain.getValue(2);
772 ResultVals.push_back(Chain.getValue(0));
775 ResultVals.push_back(Chain);
777 // Merge everything together with a MERGE_VALUES node.
778 return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0],
779 ResultVals.size()).Val;
782 //===----------------------------------------------------------------------===//
783 // FORMAL_ARGUMENTS Calling Convention Implementation
784 //===----------------------------------------------------------------------===//
786 /// Mips custom FORMAL_ARGUMENTS implementation
787 SDValue MipsTargetLowering::
788 LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG)
790 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
794 assert(0 && "Unsupported calling convention");
796 return LowerCCCArguments(Op, DAG);
800 /// LowerCCCArguments - transform physical registers into
801 /// virtual registers and generate load operations for
802 /// arguments places on the stack.
804 SDValue MipsTargetLowering::
805 LowerCCCArguments(SDValue Op, SelectionDAG &DAG)
807 SDValue Root = Op.getOperand(0);
808 MachineFunction &MF = DAG.getMachineFunction();
809 MachineFrameInfo *MFI = MF.getFrameInfo();
810 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
812 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
813 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
815 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
817 // GP must be live into PIC and non-PIC call target.
818 AddLiveIn(MF, Mips::GP, Mips::CPURegsRegisterClass);
820 // Assign locations to all of the incoming arguments.
821 SmallVector<CCValAssign, 16> ArgLocs;
822 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
824 CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips);
825 SmallVector<SDValue, 16> ArgValues;
828 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
830 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
832 CCValAssign &VA = ArgLocs[i];
834 // Arguments stored on registers
836 MVT RegVT = VA.getLocVT();
837 TargetRegisterClass *RC = 0;
839 if (RegVT == MVT::i32)
840 RC = Mips::CPURegsRegisterClass;
841 else if (RegVT == MVT::f32) {
842 if (Subtarget->isSingleFloat())
843 RC = Mips::FGR32RegisterClass;
845 RC = Mips::AFGR32RegisterClass;
846 } else if (RegVT == MVT::f64) {
847 if (!Subtarget->isSingleFloat())
848 RC = Mips::AFGR64RegisterClass;
850 assert(0 && "RegVT not supported by FORMAL_ARGUMENTS Lowering");
852 // Transform the arguments stored on
853 // physical registers into virtual ones
854 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
855 SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
857 // If this is an 8 or 16-bit value, it is really passed promoted
858 // to 32 bits. Insert an assert[sz]ext to capture this, then
859 // truncate to the right size.
860 if (VA.getLocInfo() == CCValAssign::SExt)
861 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
862 DAG.getValueType(VA.getValVT()));
863 else if (VA.getLocInfo() == CCValAssign::ZExt)
864 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
865 DAG.getValueType(VA.getValVT()));
867 if (VA.getLocInfo() != CCValAssign::Full)
868 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
870 ArgValues.push_back(ArgValue);
872 // To meet ABI, when VARARGS are passed on registers, the registers
873 // must have their values written to the caller stack frame.
874 if ((isVarArg) && (Subtarget->isABI_O32())) {
875 if (StackPtr.Val == 0)
876 StackPtr = DAG.getRegister(StackReg, getPointerTy());
878 // The stack pointer offset is relative to the caller stack frame.
879 // Since the real stack size is unknown here, a negative SPOffset
880 // is used so there's a way to adjust these offsets when the stack
881 // size get known (on EliminateFrameIndex). A dummy SPOffset is
882 // used instead of a direct negative address (which is recorded to
883 // be used on emitPrologue) to avoid mis-calc of the first stack
884 // offset on PEI::calculateFrameObjectOffsets.
885 // Arguments are always 32-bit.
886 int FI = MFI->CreateFixedObject(4, 0);
887 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
888 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
890 // emit ISD::STORE whichs stores the
891 // parameter value to a stack Location
892 ArgValues.push_back(DAG.getStore(Root, ArgValue, PtrOff, NULL, 0));
895 } else { // VA.isRegLoc()
898 assert(VA.isMemLoc());
900 // The stack pointer offset is relative to the caller stack frame.
901 // Since the real stack size is unknown here, a negative SPOffset
902 // is used so there's a way to adjust these offsets when the stack
903 // size get known (on EliminateFrameIndex). A dummy SPOffset is
904 // used instead of a direct negative address (which is recorded to
905 // be used on emitPrologue) to avoid mis-calc of the first stack
906 // offset on PEI::calculateFrameObjectOffsets.
907 // Arguments are always 32-bit.
908 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
909 int FI = MFI->CreateFixedObject(ArgSize, 0);
910 MipsFI->recordLoadArgsFI(FI, -(ArgSize+
911 (FirstStackArgLoc + VA.getLocMemOffset())));
913 // Create load nodes to retrieve arguments from the stack
914 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
915 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
919 // The mips ABIs for returning structs by value requires that we copy
920 // the sret argument into $v0 for the return. Save the argument into
921 // a virtual register so that we can access it from the return points.
922 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
923 unsigned Reg = MipsFI->getSRetReturnReg();
925 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
926 MipsFI->setSRetReturnReg(Reg);
928 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
929 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root);
932 ArgValues.push_back(Root);
934 // Return the new list of results.
935 return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
936 ArgValues.size()).getValue(Op.ResNo);
939 //===----------------------------------------------------------------------===//
940 // Return Value Calling Convention Implementation
941 //===----------------------------------------------------------------------===//
943 SDValue MipsTargetLowering::
944 LowerRET(SDValue Op, SelectionDAG &DAG)
946 // CCValAssign - represent the assignment of
947 // the return value to a location
948 SmallVector<CCValAssign, 16> RVLocs;
949 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
950 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
952 // CCState - Info about the registers and stack slot.
953 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
955 // Analize return values of ISD::RET
956 CCInfo.AnalyzeReturn(Op.Val, RetCC_Mips);
958 // If this is the first return lowered for this function, add
959 // the regs to the liveout set for the function.
960 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
961 for (unsigned i = 0; i != RVLocs.size(); ++i)
962 if (RVLocs[i].isRegLoc())
963 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
966 // The chain is always operand #0
967 SDValue Chain = Op.getOperand(0);
970 // Copy the result values into the output registers.
971 for (unsigned i = 0; i != RVLocs.size(); ++i) {
972 CCValAssign &VA = RVLocs[i];
973 assert(VA.isRegLoc() && "Can only return in registers!");
975 // ISD::RET => ret chain, (regnum1,val1), ...
976 // So i*2+1 index only the regnums
977 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
979 // guarantee that all emitted copies are
980 // stuck together, avoiding something bad
981 Flag = Chain.getValue(1);
984 // The mips ABIs for returning structs by value requires that we copy
985 // the sret argument into $v0 for the return. We saved the argument into
986 // a virtual register in the entry block, so now we copy the value out
988 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
989 MachineFunction &MF = DAG.getMachineFunction();
990 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
991 unsigned Reg = MipsFI->getSRetReturnReg();
994 assert(0 && "sret virtual register not created in the entry block");
995 SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
997 Chain = DAG.getCopyToReg(Chain, Mips::V0, Val, Flag);
998 Flag = Chain.getValue(1);
1001 // Return on Mips is always a "jr $ra"
1003 return DAG.getNode(MipsISD::Ret, MVT::Other,
1004 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
1006 return DAG.getNode(MipsISD::Ret, MVT::Other,
1007 Chain, DAG.getRegister(Mips::RA, MVT::i32));
1010 //===----------------------------------------------------------------------===//
1011 // Mips Inline Assembly Support
1012 //===----------------------------------------------------------------------===//
1014 /// getConstraintType - Given a constraint letter, return the type of
1015 /// constraint it is for this target.
1016 MipsTargetLowering::ConstraintType MipsTargetLowering::
1017 getConstraintType(const std::string &Constraint) const
1019 // Mips specific constrainy
1020 // GCC config/mips/constraints.md
1022 // 'd' : An address register. Equivalent to r
1023 // unless generating MIPS16 code.
1024 // 'y' : Equivalent to r; retained for
1025 // backwards compatibility.
1026 // 'f' : Floating Point registers.
1027 if (Constraint.size() == 1) {
1028 switch (Constraint[0]) {
1033 return C_RegisterClass;
1037 return TargetLowering::getConstraintType(Constraint);
1040 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1041 /// return a list of registers that can be used to satisfy the constraint.
1042 /// This should only be used for C_RegisterClass constraints.
1043 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
1044 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
1046 if (Constraint.size() == 1) {
1047 switch (Constraint[0]) {
1049 return std::make_pair(0U, Mips::CPURegsRegisterClass);
1051 if (VT == MVT::f32) {
1052 if (Subtarget->isSingleFloat())
1053 return std::make_pair(0U, Mips::FGR32RegisterClass);
1055 return std::make_pair(0U, Mips::AFGR32RegisterClass);
1058 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1059 return std::make_pair(0U, Mips::AFGR64RegisterClass);
1062 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1065 /// Given a register class constraint, like 'r', if this corresponds directly
1066 /// to an LLVM register class, return a register of 0 and the register class
1068 std::vector<unsigned> MipsTargetLowering::
1069 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1072 if (Constraint.size() != 1)
1073 return std::vector<unsigned>();
1075 switch (Constraint[0]) {
1078 // GCC Mips Constraint Letters
1081 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
1082 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
1083 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
1087 if (VT == MVT::f32) {
1088 if (Subtarget->isSingleFloat())
1089 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
1090 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
1091 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
1092 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
1093 Mips::F30, Mips::F31, 0);
1095 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
1096 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
1097 Mips::F28, Mips::F30, 0);
1101 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1102 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
1103 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
1104 Mips::D14, Mips::D15, 0);
1106 return std::vector<unsigned>();