1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
17 #include "MipsISelLowering.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsTargetMachine.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
39 const char *MipsTargetLowering::
40 getTargetNodeName(unsigned Opcode) const
44 case MipsISD::JmpLink : return "MipsISD::JmpLink";
45 case MipsISD::Hi : return "MipsISD::Hi";
46 case MipsISD::Lo : return "MipsISD::Lo";
47 case MipsISD::GPRel : return "MipsISD::GPRel";
48 case MipsISD::Ret : return "MipsISD::Ret";
49 case MipsISD::SelectCC : return "MipsISD::SelectCC";
50 case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC";
51 case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
52 case MipsISD::FPCmp : return "MipsISD::FPCmp";
53 default : return NULL;
58 MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
60 Subtarget = &TM.getSubtarget<MipsSubtarget>();
62 // Mips does not have i1 type, so use i32 for
63 // setcc operations results (slt, sgt, ...).
64 setSetCCResultContents(ZeroOrOneSetCCResult);
66 // JumpTable targets must use GOT when using PIC_
67 setUsesGlobalOffsetTable(true);
69 // Set up the register classes
70 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
72 // When dealing with single precision only, use libcalls
73 if (!Subtarget->isSingleFloat()) {
74 addRegisterClass(MVT::f32, Mips::AFGR32RegisterClass);
75 if (!Subtarget->isFP64bit())
76 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
78 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
81 addLegalFPImmediate(APFloat(+0.0f));
83 // Load extented operations for i1 types must be promoted
84 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
85 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
86 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
88 // Used by legalize types to correctly generate the setcc result.
89 // Without this, every float setcc comes with a AND/OR with the result,
90 // we don't want this, since the fpcmp result goes to a flag register,
91 // which is used implicitly by brcond and select operations.
92 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
94 // Mips Custom Operations
95 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
96 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
97 setOperationAction(ISD::RET, MVT::Other, Custom);
98 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
99 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
100 setOperationAction(ISD::SELECT, MVT::f32, Custom);
101 setOperationAction(ISD::SELECT, MVT::i32, Custom);
102 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
103 setOperationAction(ISD::SETCC, MVT::f32, Custom);
104 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
105 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
107 // We custom lower AND/OR to handle the case where the DAG contain 'ands/ors'
108 // with operands comming from setcc fp comparions. This is necessary since
109 // the result from these setcc are in a flag registers (FCR31).
110 setOperationAction(ISD::AND, MVT::i32, Custom);
111 setOperationAction(ISD::OR, MVT::i32, Custom);
113 // Operations not directly supported by Mips.
114 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
115 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
116 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
117 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
118 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
120 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
121 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
122 setOperationAction(ISD::ROTL, MVT::i32, Expand);
123 setOperationAction(ISD::ROTR, MVT::i32, Expand);
124 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
125 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
126 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
127 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
128 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
130 // We don't have line number support yet.
131 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
132 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
133 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
134 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
136 // Use the default for now
137 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
138 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
139 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
141 if (Subtarget->isSingleFloat())
142 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
144 if (!Subtarget->hasSEInReg()) {
145 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
146 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
149 if (!Subtarget->hasBitCount())
150 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
152 setStackPointerRegisterToSaveRestore(Mips::SP);
153 computeRegisterProperties();
157 MVT MipsTargetLowering::getSetCCResultType(const SDValue &) const {
162 SDValue MipsTargetLowering::
163 LowerOperation(SDValue Op, SelectionDAG &DAG)
165 switch (Op.getOpcode())
167 case ISD::AND: return LowerANDOR(Op, DAG);
168 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
169 case ISD::CALL: return LowerCALL(Op, DAG);
170 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
171 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
172 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
173 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
174 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
175 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
176 case ISD::OR: return LowerANDOR(Op, DAG);
177 case ISD::RET: return LowerRET(Op, DAG);
178 case ISD::SELECT: return LowerSELECT(Op, DAG);
179 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
180 case ISD::SETCC: return LowerSETCC(Op, DAG);
185 //===----------------------------------------------------------------------===//
186 // Lower helper functions
187 //===----------------------------------------------------------------------===//
189 // AddLiveIn - This helper function adds the specified physical register to the
190 // MachineFunction as a live in value. It also creates a corresponding
191 // virtual register for it.
193 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
195 assert(RC->contains(PReg) && "Not the correct regclass!");
196 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
197 MF.getRegInfo().addLiveIn(PReg, VReg);
201 // A address must be loaded from a small section if its size is less than the
202 // small section size threshold. Data in this section must be addressed using
204 bool MipsTargetLowering::IsInSmallSection(unsigned Size) {
205 return (Size > 0 && (Size <= Subtarget->getSSectionThreshold()));
208 // Discover if this global address can be placed into small data/bss section.
209 bool MipsTargetLowering::IsGlobalInSmallSection(GlobalValue *GV)
211 const TargetData *TD = getTargetData();
212 const GlobalVariable *GVA = dyn_cast<GlobalVariable>(GV);
217 const Type *Ty = GV->getType()->getElementType();
218 unsigned Size = TD->getABITypeSize(Ty);
220 // if this is a internal constant string, there is a special
221 // section for it, but not in small data/bss.
222 if (GVA->hasInitializer() && GV->hasInternalLinkage()) {
223 Constant *C = GVA->getInitializer();
224 const ConstantArray *CVA = dyn_cast<ConstantArray>(C);
225 if (CVA && CVA->isCString())
229 return IsInSmallSection(Size);
232 // Get fp branch code (not opcode) from condition code.
233 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
234 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
235 return Mips::BRANCH_T;
237 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
238 return Mips::BRANCH_F;
240 return Mips::BRANCH_INVALID;
243 static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) {
246 assert(0 && "Unknown branch code");
247 case Mips::BRANCH_T : return Mips::BC1T;
248 case Mips::BRANCH_F : return Mips::BC1F;
249 case Mips::BRANCH_TL : return Mips::BC1TL;
250 case Mips::BRANCH_FL : return Mips::BC1FL;
254 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
256 default: assert(0 && "Unknown fp condition code!");
258 case ISD::SETOEQ: return Mips::FCOND_EQ;
259 case ISD::SETUNE: return Mips::FCOND_OGL;
261 case ISD::SETOLT: return Mips::FCOND_OLT;
263 case ISD::SETOGT: return Mips::FCOND_OGT;
265 case ISD::SETOLE: return Mips::FCOND_OLE;
267 case ISD::SETOGE: return Mips::FCOND_OGE;
268 case ISD::SETULT: return Mips::FCOND_ULT;
269 case ISD::SETULE: return Mips::FCOND_ULE;
270 case ISD::SETUGT: return Mips::FCOND_UGT;
271 case ISD::SETUGE: return Mips::FCOND_UGE;
272 case ISD::SETUO: return Mips::FCOND_UN;
273 case ISD::SETO: return Mips::FCOND_OR;
275 case ISD::SETONE: return Mips::FCOND_NEQ;
276 case ISD::SETUEQ: return Mips::FCOND_UEQ;
281 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
282 MachineBasicBlock *BB)
284 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
285 bool isFPCmp = false;
287 switch (MI->getOpcode()) {
288 default: assert(false && "Unexpected instr type to insert");
289 case Mips::Select_FCC:
290 case Mips::Select_FCC_SO32:
291 case Mips::Select_FCC_AS32:
292 case Mips::Select_FCC_D32:
293 isFPCmp = true; // FALL THROUGH
294 case Mips::Select_CC:
295 case Mips::Select_CC_SO32:
296 case Mips::Select_CC_AS32:
297 case Mips::Select_CC_D32: {
298 // To "insert" a SELECT_CC instruction, we actually have to insert the
299 // diamond control-flow pattern. The incoming instruction knows the
300 // destination vreg to set, the condition code register to branch on, the
301 // true/false values to select between, and a branch opcode to use.
302 const BasicBlock *LLVM_BB = BB->getBasicBlock();
303 MachineFunction::iterator It = BB;
310 // bNE r1, r0, copy1MBB
311 // fallthrough --> copy0MBB
312 MachineBasicBlock *thisMBB = BB;
313 MachineFunction *F = BB->getParent();
314 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
315 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
317 // Emit the right instruction according to the type of the operands compared
319 // Find the condiction code present in the setcc operation.
320 Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm();
321 // Get the branch opcode from the branch code.
322 unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC));
323 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
325 BuildMI(BB, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
326 .addReg(Mips::ZERO).addMBB(sinkMBB);
328 F->insert(It, copy0MBB);
329 F->insert(It, sinkMBB);
330 // Update machine-CFG edges by first adding all successors of the current
331 // block to the new block which will contain the Phi node for the select.
332 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
333 e = BB->succ_end(); i != e; ++i)
334 sinkMBB->addSuccessor(*i);
335 // Next, remove all successors of the current block, and add the true
336 // and fallthrough blocks as its successors.
337 while(!BB->succ_empty())
338 BB->removeSuccessor(BB->succ_begin());
339 BB->addSuccessor(copy0MBB);
340 BB->addSuccessor(sinkMBB);
344 // # fallthrough to sinkMBB
347 // Update machine-CFG edges
348 BB->addSuccessor(sinkMBB);
351 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
354 BuildMI(BB, TII->get(Mips::PHI), MI->getOperand(0).getReg())
355 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
356 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
358 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
364 //===----------------------------------------------------------------------===//
365 // Misc Lower Operation implementation
366 //===----------------------------------------------------------------------===//
368 SDValue MipsTargetLowering::
369 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG)
371 SDValue Chain = Op.getOperand(0);
372 SDValue Size = Op.getOperand(1);
374 // Get a reference from Mips stack pointer
375 SDValue StackPointer = DAG.getCopyFromReg(Chain, Mips::SP, MVT::i32);
377 // Subtract the dynamic size from the actual stack size to
378 // obtain the new stack size.
379 SDValue Sub = DAG.getNode(ISD::SUB, MVT::i32, StackPointer, Size);
381 // The Sub result contains the new stack start address, so it
382 // must be placed in the stack pointer register.
383 Chain = DAG.getCopyToReg(StackPointer.getValue(1), Mips::SP, Sub);
385 // This node always has two return values: a new stack pointer
387 SDValue Ops[2] = { Sub, Chain };
388 return DAG.getMergeValues(Ops, 2);
391 SDValue MipsTargetLowering::
392 LowerANDOR(SDValue Op, SelectionDAG &DAG)
394 SDValue LHS = Op.getOperand(0);
395 SDValue RHS = Op.getOperand(1);
397 if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp)
400 SDValue True = DAG.getConstant(1, MVT::i32);
401 SDValue False = DAG.getConstant(0, MVT::i32);
403 SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, True.getValueType(),
404 LHS, True, False, LHS.getOperand(2));
405 SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, True.getValueType(),
406 RHS, True, False, RHS.getOperand(2));
408 return DAG.getNode(Op.getOpcode(), MVT::i32, LSEL, RSEL);
411 SDValue MipsTargetLowering::
412 LowerBRCOND(SDValue Op, SelectionDAG &DAG)
414 // The first operand is the chain, the second is the condition, the third is
415 // the block to branch to if the condition is true.
416 SDValue Chain = Op.getOperand(0);
417 SDValue Dest = Op.getOperand(2);
419 if (Op.getOperand(1).getOpcode() != MipsISD::FPCmp)
422 SDValue CondRes = Op.getOperand(1);
423 SDValue CCNode = CondRes.getOperand(2);
424 Mips::CondCode CC = (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getValue();
425 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
427 return DAG.getNode(MipsISD::FPBrcond, Op.getValueType(), Chain, BrCode,
431 SDValue MipsTargetLowering::
432 LowerSETCC(SDValue Op, SelectionDAG &DAG)
434 // The operands to this are the left and right operands to compare (ops #0,
435 // and #1) and the condition code to compare them with (op #2) as a
437 SDValue LHS = Op.getOperand(0);
438 SDValue RHS = Op.getOperand(1);
440 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
442 return DAG.getNode(MipsISD::FPCmp, Op.getValueType(), LHS, RHS,
443 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
446 SDValue MipsTargetLowering::
447 LowerSELECT(SDValue Op, SelectionDAG &DAG)
449 SDValue Cond = Op.getOperand(0);
450 SDValue True = Op.getOperand(1);
451 SDValue False = Op.getOperand(2);
453 // if the incomming condition comes from fpcmp, the select
454 // operation must use FPSelectCC, otherwise SelectCC.
455 if (Cond.getOpcode() != MipsISD::FPCmp)
456 return DAG.getNode(MipsISD::SelectCC, True.getValueType(),
459 SDValue CCNode = Cond.getOperand(2);
460 return DAG.getNode(MipsISD::FPSelectCC, True.getValueType(),
461 Cond, True, False, CCNode);
464 SDValue MipsTargetLowering::
465 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG)
467 SDValue LHS = Op.getOperand(0);
468 SDValue RHS = Op.getOperand(1);
469 SDValue True = Op.getOperand(2);
470 SDValue False = Op.getOperand(3);
471 SDValue CC = Op.getOperand(4);
473 SDValue SetCCRes = DAG.getNode(ISD::SETCC, LHS.getValueType(), LHS, RHS, CC);
474 return DAG.getNode(MipsISD::SelectCC, True.getValueType(),
475 SetCCRes, True, False);
478 SDValue MipsTargetLowering::
479 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
481 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
482 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
484 if (!Subtarget->hasABICall()) {
485 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
486 SDValue Ops[] = { GA };
487 // %gp_rel relocation
488 if (!isa<Function>(GV) && IsGlobalInSmallSection(GV)) {
489 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, VTs, 1, Ops, 1);
490 SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
491 return DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
493 // %hi/%lo relocation
494 SDValue HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
495 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
496 return DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
498 } else { // Abicall relocations, TODO: make this cleaner.
499 SDValue ResNode = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0);
500 // On functions and global targets not internal linked only
501 // a load from got/GP is necessary for PIC to work.
502 if (!GV->hasInternalLinkage() || isa<Function>(GV))
504 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
505 return DAG.getNode(ISD::ADD, MVT::i32, ResNode, Lo);
508 assert(0 && "Dont know how to handle GlobalAddress");
512 SDValue MipsTargetLowering::
513 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
515 assert(0 && "TLS not implemented for MIPS.");
516 return SDValue(); // Not reached
519 SDValue MipsTargetLowering::
520 LowerJumpTable(SDValue Op, SelectionDAG &DAG)
525 MVT PtrVT = Op.getValueType();
526 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
527 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
529 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
530 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
531 SDValue Ops[] = { JTI };
532 HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
533 } else // Emit Load from Global Pointer
534 HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), JTI, NULL, 0);
536 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, JTI);
537 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
542 SDValue MipsTargetLowering::
543 LowerConstantPool(SDValue Op, SelectionDAG &DAG)
546 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
547 Constant *C = N->getConstVal();
548 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
551 // FIXME: we should reference the constant pool using small data sections,
552 // but the asm printer currently doens't support this feature without
553 // hacking it. This feature should come soon so we can uncomment the
555 //if (!Subtarget->hasABICall() &&
556 // IsInSmallSection(getTargetData()->getABITypeSize(C->getType()))) {
557 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
558 // SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
559 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
560 //} else { // %hi/%lo relocation
561 SDValue HiPart = DAG.getNode(MipsISD::Hi, MVT::i32, CP);
562 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, CP);
563 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
569 //===----------------------------------------------------------------------===//
570 // Calling Convention Implementation
572 // The lower operations present on calling convention works on this order:
573 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
574 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
575 // LowerRET (virt regs --> phys regs)
576 // LowerCALL (phys regs --> virt regs)
578 //===----------------------------------------------------------------------===//
580 #include "MipsGenCallingConv.inc"
582 //===----------------------------------------------------------------------===//
583 // CALL Calling Convention Implementation
584 //===----------------------------------------------------------------------===//
586 /// LowerCCCCallTo - functions arguments are copied from virtual
587 /// regs to (physical regs)/(stack frame), CALLSEQ_START and
588 /// CALLSEQ_END are emitted.
589 /// TODO: isVarArg, isTailCall.
590 SDValue MipsTargetLowering::
591 LowerCALL(SDValue Op, SelectionDAG &DAG)
593 MachineFunction &MF = DAG.getMachineFunction();
595 SDValue Chain = Op.getOperand(0);
596 SDValue Callee = Op.getOperand(4);
597 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
598 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
600 MachineFrameInfo *MFI = MF.getFrameInfo();
602 // Analyze operands of the call, assigning locations to each operand.
603 SmallVector<CCValAssign, 16> ArgLocs;
604 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
606 // To meet O32 ABI, Mips must always allocate 16 bytes on
607 // the stack (even if less than 4 are used as arguments)
608 if (Subtarget->isABI_O32()) {
609 int VTsize = MVT(MVT::i32).getSizeInBits()/8;
610 MFI->CreateFixedObject(VTsize, (VTsize*3));
613 CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips);
615 // Get a count of how many bytes are to be pushed on the stack.
616 unsigned NumBytes = CCInfo.getNextStackOffset();
617 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
620 // With EABI is it possible to have 16 args on registers.
621 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
622 SmallVector<SDValue, 8> MemOpChains;
624 // First/LastArgStackLoc contains the first/last
625 // "at stack" argument location.
626 int LastArgStackLoc = 0;
627 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
629 // Walk the register/memloc assignments, inserting copies/loads.
630 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
631 CCValAssign &VA = ArgLocs[i];
633 // Arguments start after the 5 first operands of ISD::CALL
634 SDValue Arg = Op.getOperand(5+2*VA.getValNo());
636 // Promote the value if needed.
637 switch (VA.getLocInfo()) {
638 default: assert(0 && "Unknown loc info!");
639 case CCValAssign::Full: break;
640 case CCValAssign::SExt:
641 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
643 case CCValAssign::ZExt:
644 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
646 case CCValAssign::AExt:
647 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
651 // Arguments that can be passed on register must be kept at
654 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
658 // Register cant get to this point...
659 assert(VA.isMemLoc());
661 // Create the frame index object for this incoming parameter
662 // This guarantees that when allocating Local Area the firsts
663 // 16 bytes which are alwayes reserved won't be overwritten
664 // if O32 ABI is used. For EABI the first address is zero.
665 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
666 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
669 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
671 // emit ISD::STORE whichs stores the
672 // parameter value to a stack Location
673 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
676 // Transform all store nodes into one single node because all store
677 // nodes are independent of each other.
678 if (!MemOpChains.empty())
679 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
680 &MemOpChains[0], MemOpChains.size());
682 // Build a sequence of copy-to-reg nodes chained together with token
683 // chain and flag operands which copy the outgoing args into registers.
684 // The InFlag in necessary since all emited instructions must be
687 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
688 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first,
689 RegsToPass[i].second, InFlag);
690 InFlag = Chain.getValue(1);
693 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
694 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
695 // node so that legalize doesn't hack it.
696 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
697 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
698 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
699 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
702 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
703 // = Chain, Callee, Reg#1, Reg#2, ...
705 // Returns a chain & a flag for retval copy to use.
706 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
707 SmallVector<SDValue, 8> Ops;
708 Ops.push_back(Chain);
709 Ops.push_back(Callee);
711 // Add argument registers to the end of the list so that they are
712 // known live into the call.
713 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
714 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
715 RegsToPass[i].second.getValueType()));
718 Ops.push_back(InFlag);
720 Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size());
721 InFlag = Chain.getValue(1);
723 // Create the CALLSEQ_END node.
724 Chain = DAG.getCALLSEQ_END(Chain,
725 DAG.getConstant(NumBytes, getPointerTy()),
726 DAG.getConstant(0, getPointerTy()),
728 InFlag = Chain.getValue(1);
730 // Create a stack location to hold GP when PIC is used. This stack
731 // location is used on function prologue to save GP and also after all
732 // emited CALL's to restore GP.
733 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
734 // Function can have an arbitrary number of calls, so
735 // hold the LastArgStackLoc with the biggest offset.
737 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
738 if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
739 LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
740 // Create the frame index only once. SPOffset here can be anything
741 // (this will be fixed on processFunctionBeforeFrameFinalized)
742 if (MipsFI->getGPStackOffset() == -1) {
743 FI = MFI->CreateFixedObject(4, 0);
746 MipsFI->setGPStackOffset(LastArgStackLoc);
750 FI = MipsFI->getGPFI();
751 SDValue FIN = DAG.getFrameIndex(FI,getPointerTy());
752 SDValue GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0);
753 Chain = GPLoad.getValue(1);
754 Chain = DAG.getCopyToReg(Chain, DAG.getRegister(Mips::GP, MVT::i32),
755 GPLoad, SDValue(0,0));
756 InFlag = Chain.getValue(1);
759 // Handle result values, copying them out of physregs into vregs that we
761 return SDValue(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
764 /// LowerCallResult - Lower the result values of an ISD::CALL into the
765 /// appropriate copies out of appropriate physical registers. This assumes that
766 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
767 /// being lowered. Returns a SDNode with the same number of values as the
769 SDNode *MipsTargetLowering::
770 LowerCallResult(SDValue Chain, SDValue InFlag, SDNode *TheCall,
771 unsigned CallingConv, SelectionDAG &DAG) {
773 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
775 // Assign locations to each value returned by this call.
776 SmallVector<CCValAssign, 16> RVLocs;
777 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
779 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
780 SmallVector<SDValue, 8> ResultVals;
782 // Copy all of the result registers out of their specified physreg.
783 for (unsigned i = 0; i != RVLocs.size(); ++i) {
784 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
785 RVLocs[i].getValVT(), InFlag).getValue(1);
786 InFlag = Chain.getValue(2);
787 ResultVals.push_back(Chain.getValue(0));
790 ResultVals.push_back(Chain);
792 // Merge everything together with a MERGE_VALUES node.
793 return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0],
794 ResultVals.size()).Val;
797 //===----------------------------------------------------------------------===//
798 // FORMAL_ARGUMENTS Calling Convention Implementation
799 //===----------------------------------------------------------------------===//
801 /// LowerFORMAL_ARGUMENTS - transform physical registers into
802 /// virtual registers and generate load operations for
803 /// arguments places on the stack.
805 SDValue MipsTargetLowering::
806 LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG)
808 SDValue Root = Op.getOperand(0);
809 MachineFunction &MF = DAG.getMachineFunction();
810 MachineFrameInfo *MFI = MF.getFrameInfo();
811 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
813 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
814 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
816 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
818 // GP must be live into PIC and non-PIC call target.
819 AddLiveIn(MF, Mips::GP, Mips::CPURegsRegisterClass);
821 // Assign locations to all of the incoming arguments.
822 SmallVector<CCValAssign, 16> ArgLocs;
823 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
825 CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips);
826 SmallVector<SDValue, 16> ArgValues;
829 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
831 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
833 CCValAssign &VA = ArgLocs[i];
835 // Arguments stored on registers
837 MVT RegVT = VA.getLocVT();
838 TargetRegisterClass *RC = 0;
840 if (RegVT == MVT::i32)
841 RC = Mips::CPURegsRegisterClass;
842 else if (RegVT == MVT::f32) {
843 if (Subtarget->isSingleFloat())
844 RC = Mips::FGR32RegisterClass;
846 RC = Mips::AFGR32RegisterClass;
847 } else if (RegVT == MVT::f64) {
848 if (!Subtarget->isSingleFloat())
849 RC = Mips::AFGR64RegisterClass;
851 assert(0 && "RegVT not supported by FORMAL_ARGUMENTS Lowering");
853 // Transform the arguments stored on
854 // physical registers into virtual ones
855 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
856 SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
858 // If this is an 8 or 16-bit value, it is really passed promoted
859 // to 32 bits. Insert an assert[sz]ext to capture this, then
860 // truncate to the right size.
861 if (VA.getLocInfo() == CCValAssign::SExt)
862 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
863 DAG.getValueType(VA.getValVT()));
864 else if (VA.getLocInfo() == CCValAssign::ZExt)
865 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
866 DAG.getValueType(VA.getValVT()));
868 if (VA.getLocInfo() != CCValAssign::Full)
869 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
871 ArgValues.push_back(ArgValue);
873 // To meet ABI, when VARARGS are passed on registers, the registers
874 // must have their values written to the caller stack frame.
875 if ((isVarArg) && (Subtarget->isABI_O32())) {
876 if (StackPtr.Val == 0)
877 StackPtr = DAG.getRegister(StackReg, getPointerTy());
879 // The stack pointer offset is relative to the caller stack frame.
880 // Since the real stack size is unknown here, a negative SPOffset
881 // is used so there's a way to adjust these offsets when the stack
882 // size get known (on EliminateFrameIndex). A dummy SPOffset is
883 // used instead of a direct negative address (which is recorded to
884 // be used on emitPrologue) to avoid mis-calc of the first stack
885 // offset on PEI::calculateFrameObjectOffsets.
886 // Arguments are always 32-bit.
887 int FI = MFI->CreateFixedObject(4, 0);
888 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
889 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
891 // emit ISD::STORE whichs stores the
892 // parameter value to a stack Location
893 ArgValues.push_back(DAG.getStore(Root, ArgValue, PtrOff, NULL, 0));
896 } else { // VA.isRegLoc()
899 assert(VA.isMemLoc());
901 // The stack pointer offset is relative to the caller stack frame.
902 // Since the real stack size is unknown here, a negative SPOffset
903 // is used so there's a way to adjust these offsets when the stack
904 // size get known (on EliminateFrameIndex). A dummy SPOffset is
905 // used instead of a direct negative address (which is recorded to
906 // be used on emitPrologue) to avoid mis-calc of the first stack
907 // offset on PEI::calculateFrameObjectOffsets.
908 // Arguments are always 32-bit.
909 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
910 int FI = MFI->CreateFixedObject(ArgSize, 0);
911 MipsFI->recordLoadArgsFI(FI, -(ArgSize+
912 (FirstStackArgLoc + VA.getLocMemOffset())));
914 // Create load nodes to retrieve arguments from the stack
915 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
916 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
920 // The mips ABIs for returning structs by value requires that we copy
921 // the sret argument into $v0 for the return. Save the argument into
922 // a virtual register so that we can access it from the return points.
923 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
924 unsigned Reg = MipsFI->getSRetReturnReg();
926 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
927 MipsFI->setSRetReturnReg(Reg);
929 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
930 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root);
933 ArgValues.push_back(Root);
935 // Return the new list of results.
936 return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
937 ArgValues.size()).getValue(Op.ResNo);
940 //===----------------------------------------------------------------------===//
941 // Return Value Calling Convention Implementation
942 //===----------------------------------------------------------------------===//
944 SDValue MipsTargetLowering::
945 LowerRET(SDValue Op, SelectionDAG &DAG)
947 // CCValAssign - represent the assignment of
948 // the return value to a location
949 SmallVector<CCValAssign, 16> RVLocs;
950 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
951 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
953 // CCState - Info about the registers and stack slot.
954 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
956 // Analize return values of ISD::RET
957 CCInfo.AnalyzeReturn(Op.Val, RetCC_Mips);
959 // If this is the first return lowered for this function, add
960 // the regs to the liveout set for the function.
961 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
962 for (unsigned i = 0; i != RVLocs.size(); ++i)
963 if (RVLocs[i].isRegLoc())
964 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
967 // The chain is always operand #0
968 SDValue Chain = Op.getOperand(0);
971 // Copy the result values into the output registers.
972 for (unsigned i = 0; i != RVLocs.size(); ++i) {
973 CCValAssign &VA = RVLocs[i];
974 assert(VA.isRegLoc() && "Can only return in registers!");
976 // ISD::RET => ret chain, (regnum1,val1), ...
977 // So i*2+1 index only the regnums
978 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
980 // guarantee that all emitted copies are
981 // stuck together, avoiding something bad
982 Flag = Chain.getValue(1);
985 // The mips ABIs for returning structs by value requires that we copy
986 // the sret argument into $v0 for the return. We saved the argument into
987 // a virtual register in the entry block, so now we copy the value out
989 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
990 MachineFunction &MF = DAG.getMachineFunction();
991 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
992 unsigned Reg = MipsFI->getSRetReturnReg();
995 assert(0 && "sret virtual register not created in the entry block");
996 SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
998 Chain = DAG.getCopyToReg(Chain, Mips::V0, Val, Flag);
999 Flag = Chain.getValue(1);
1002 // Return on Mips is always a "jr $ra"
1004 return DAG.getNode(MipsISD::Ret, MVT::Other,
1005 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
1007 return DAG.getNode(MipsISD::Ret, MVT::Other,
1008 Chain, DAG.getRegister(Mips::RA, MVT::i32));
1011 //===----------------------------------------------------------------------===//
1012 // Mips Inline Assembly Support
1013 //===----------------------------------------------------------------------===//
1015 /// getConstraintType - Given a constraint letter, return the type of
1016 /// constraint it is for this target.
1017 MipsTargetLowering::ConstraintType MipsTargetLowering::
1018 getConstraintType(const std::string &Constraint) const
1020 // Mips specific constrainy
1021 // GCC config/mips/constraints.md
1023 // 'd' : An address register. Equivalent to r
1024 // unless generating MIPS16 code.
1025 // 'y' : Equivalent to r; retained for
1026 // backwards compatibility.
1027 // 'f' : Floating Point registers.
1028 if (Constraint.size() == 1) {
1029 switch (Constraint[0]) {
1034 return C_RegisterClass;
1038 return TargetLowering::getConstraintType(Constraint);
1041 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1042 /// return a list of registers that can be used to satisfy the constraint.
1043 /// This should only be used for C_RegisterClass constraints.
1044 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
1045 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
1047 if (Constraint.size() == 1) {
1048 switch (Constraint[0]) {
1050 return std::make_pair(0U, Mips::CPURegsRegisterClass);
1052 if (VT == MVT::f32) {
1053 if (Subtarget->isSingleFloat())
1054 return std::make_pair(0U, Mips::FGR32RegisterClass);
1056 return std::make_pair(0U, Mips::AFGR32RegisterClass);
1059 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1060 return std::make_pair(0U, Mips::AFGR64RegisterClass);
1063 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1066 /// Given a register class constraint, like 'r', if this corresponds directly
1067 /// to an LLVM register class, return a register of 0 and the register class
1069 std::vector<unsigned> MipsTargetLowering::
1070 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1073 if (Constraint.size() != 1)
1074 return std::vector<unsigned>();
1076 switch (Constraint[0]) {
1079 // GCC Mips Constraint Letters
1082 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
1083 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
1084 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
1088 if (VT == MVT::f32) {
1089 if (Subtarget->isSingleFloat())
1090 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
1091 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
1092 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
1093 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
1094 Mips::F30, Mips::F31, 0);
1096 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
1097 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
1098 Mips::F28, Mips::F30, 0);
1102 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1103 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
1104 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
1105 Mips::D14, Mips::D15, 0);
1107 return std::vector<unsigned>();