1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-lower"
16 #include "MipsISelLowering.h"
17 #include "InstPrinter/MipsInstPrinter.h"
18 #include "MCTargetDesc/MipsBaseInfo.h"
19 #include "MipsMachineFunction.h"
20 #include "MipsSubtarget.h"
21 #include "MipsTargetMachine.h"
22 #include "MipsTargetObjectFile.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/SelectionDAGISel.h"
30 #include "llvm/CodeGen/ValueTypes.h"
31 #include "llvm/IR/CallingConv.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/GlobalVariable.h"
34 #include "llvm/IR/Intrinsics.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/raw_ostream.h"
42 STATISTIC(NumTailCalls, "Number of tail calls");
45 EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
46 cl::desc("MIPS: Enable tail calls."), cl::init(false));
49 LargeGOT("mxgot", cl::Hidden,
50 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
53 Mips16HardFloat("mips16-hard-float", cl::NotHidden,
54 cl::desc("MIPS: mips16 hard float enable."),
57 static cl::opt<bool> DontExpandCondPseudos16(
58 "mips16-dont-expand-cond-pseudo",
60 cl::desc("Dont expand conditional move related "
61 "pseudos for Mips 16"),
65 static const uint16_t O32IntRegs[4] = {
66 Mips::A0, Mips::A1, Mips::A2, Mips::A3
69 static const uint16_t Mips64IntRegs[8] = {
70 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
71 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64
74 static const uint16_t Mips64DPRegs[8] = {
75 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
76 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
79 // If I is a shifted mask, set the size (Size) and the first bit of the
80 // mask (Pos), and return true.
81 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
82 static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
83 if (!isShiftedMask_64(I))
86 Size = CountPopulation_64(I);
87 Pos = CountTrailingZeros_64(I);
91 static SDValue GetGlobalReg(SelectionDAG &DAG, EVT Ty) {
92 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
93 return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
96 static SDValue getTargetNode(SDValue Op, SelectionDAG &DAG, unsigned Flag) {
97 EVT Ty = Op.getValueType();
99 if (GlobalAddressSDNode *N = dyn_cast<GlobalAddressSDNode>(Op))
100 return DAG.getTargetGlobalAddress(N->getGlobal(), Op.getDebugLoc(), Ty, 0,
102 if (ExternalSymbolSDNode *N = dyn_cast<ExternalSymbolSDNode>(Op))
103 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
104 if (BlockAddressSDNode *N = dyn_cast<BlockAddressSDNode>(Op))
105 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
106 if (JumpTableSDNode *N = dyn_cast<JumpTableSDNode>(Op))
107 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
108 if (ConstantPoolSDNode *N = dyn_cast<ConstantPoolSDNode>(Op))
109 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
110 N->getOffset(), Flag);
112 llvm_unreachable("Unexpected node type.");
116 static SDValue getAddrNonPIC(SDValue Op, SelectionDAG &DAG) {
117 DebugLoc DL = Op.getDebugLoc();
118 EVT Ty = Op.getValueType();
119 SDValue Hi = getTargetNode(Op, DAG, MipsII::MO_ABS_HI);
120 SDValue Lo = getTargetNode(Op, DAG, MipsII::MO_ABS_LO);
121 return DAG.getNode(ISD::ADD, DL, Ty,
122 DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
123 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
126 static SDValue getAddrLocal(SDValue Op, SelectionDAG &DAG, bool HasMips64) {
127 DebugLoc DL = Op.getDebugLoc();
128 EVT Ty = Op.getValueType();
129 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
130 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, GetGlobalReg(DAG, Ty),
131 getTargetNode(Op, DAG, GOTFlag));
132 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
133 MachinePointerInfo::getGOT(), false, false, false,
135 unsigned LoFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
136 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, getTargetNode(Op, DAG, LoFlag));
137 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
140 static SDValue getAddrGlobal(SDValue Op, SelectionDAG &DAG, unsigned Flag) {
141 DebugLoc DL = Op.getDebugLoc();
142 EVT Ty = Op.getValueType();
143 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, GetGlobalReg(DAG, Ty),
144 getTargetNode(Op, DAG, Flag));
145 return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Tgt,
146 MachinePointerInfo::getGOT(), false, false, false, 0);
149 static SDValue getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG,
150 unsigned HiFlag, unsigned LoFlag) {
151 DebugLoc DL = Op.getDebugLoc();
152 EVT Ty = Op.getValueType();
153 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, Ty, getTargetNode(Op, DAG, HiFlag));
154 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, GetGlobalReg(DAG, Ty));
155 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
156 getTargetNode(Op, DAG, LoFlag));
157 return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Wrapper,
158 MachinePointerInfo::getGOT(), false, false, false, 0);
161 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
163 case MipsISD::JmpLink: return "MipsISD::JmpLink";
164 case MipsISD::TailCall: return "MipsISD::TailCall";
165 case MipsISD::Hi: return "MipsISD::Hi";
166 case MipsISD::Lo: return "MipsISD::Lo";
167 case MipsISD::GPRel: return "MipsISD::GPRel";
168 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
169 case MipsISD::Ret: return "MipsISD::Ret";
170 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN";
171 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
172 case MipsISD::FPCmp: return "MipsISD::FPCmp";
173 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
174 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
175 case MipsISD::FPRound: return "MipsISD::FPRound";
176 case MipsISD::MAdd: return "MipsISD::MAdd";
177 case MipsISD::MAddu: return "MipsISD::MAddu";
178 case MipsISD::MSub: return "MipsISD::MSub";
179 case MipsISD::MSubu: return "MipsISD::MSubu";
180 case MipsISD::DivRem: return "MipsISD::DivRem";
181 case MipsISD::DivRemU: return "MipsISD::DivRemU";
182 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
183 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
184 case MipsISD::Wrapper: return "MipsISD::Wrapper";
185 case MipsISD::Sync: return "MipsISD::Sync";
186 case MipsISD::Ext: return "MipsISD::Ext";
187 case MipsISD::Ins: return "MipsISD::Ins";
188 case MipsISD::LWL: return "MipsISD::LWL";
189 case MipsISD::LWR: return "MipsISD::LWR";
190 case MipsISD::SWL: return "MipsISD::SWL";
191 case MipsISD::SWR: return "MipsISD::SWR";
192 case MipsISD::LDL: return "MipsISD::LDL";
193 case MipsISD::LDR: return "MipsISD::LDR";
194 case MipsISD::SDL: return "MipsISD::SDL";
195 case MipsISD::SDR: return "MipsISD::SDR";
196 case MipsISD::EXTP: return "MipsISD::EXTP";
197 case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
198 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
199 case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
200 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
201 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
202 case MipsISD::SHILO: return "MipsISD::SHILO";
203 case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
204 case MipsISD::MULT: return "MipsISD::MULT";
205 case MipsISD::MULTU: return "MipsISD::MULTU";
206 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP";
207 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
208 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
209 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
210 default: return NULL;
216 bool operator()(const char *s1, const char *s2) const
218 return strcmp(s1, s2) < 0;
222 std::set<const char*, ltstr> noHelperNeeded;
225 void MipsTargetLowering::SetMips16LibcallName
226 (RTLIB::Libcall l, const char *Name) {
227 setLibcallName(l, Name);
228 noHelperNeeded.insert(Name);
231 void MipsTargetLowering::setMips16HardFloatLibCalls() {
232 SetMips16LibcallName(RTLIB::ADD_F32, "__mips16_addsf3");
233 SetMips16LibcallName(RTLIB::ADD_F64, "__mips16_adddf3");
234 SetMips16LibcallName(RTLIB::SUB_F32, "__mips16_subsf3");
235 SetMips16LibcallName(RTLIB::SUB_F64, "__mips16_subdf3");
236 SetMips16LibcallName(RTLIB::MUL_F32, "__mips16_mulsf3");
237 SetMips16LibcallName(RTLIB::MUL_F64, "__mips16_muldf3");
238 SetMips16LibcallName(RTLIB::DIV_F32, "__mips16_divsf3");
239 SetMips16LibcallName(RTLIB::DIV_F64, "__mips16_divdf3");
240 SetMips16LibcallName(RTLIB::FPEXT_F32_F64, "__mips16_extendsfdf2");
241 SetMips16LibcallName(RTLIB::FPROUND_F64_F32, "__mips16_truncdfsf2");
242 SetMips16LibcallName(RTLIB::FPTOSINT_F32_I32, "__mips16_fix_truncsfsi");
243 SetMips16LibcallName(RTLIB::FPTOSINT_F64_I32, "__mips16_fix_truncdfsi");
244 SetMips16LibcallName(RTLIB::SINTTOFP_I32_F32, "__mips16_floatsisf");
245 SetMips16LibcallName(RTLIB::SINTTOFP_I32_F64, "__mips16_floatsidf");
246 SetMips16LibcallName(RTLIB::UINTTOFP_I32_F32, "__mips16_floatunsisf");
247 SetMips16LibcallName(RTLIB::UINTTOFP_I32_F64, "__mips16_floatunsidf");
248 SetMips16LibcallName(RTLIB::OEQ_F32, "__mips16_eqsf2");
249 SetMips16LibcallName(RTLIB::OEQ_F64, "__mips16_eqdf2");
250 SetMips16LibcallName(RTLIB::UNE_F32, "__mips16_nesf2");
251 SetMips16LibcallName(RTLIB::UNE_F64, "__mips16_nedf2");
252 SetMips16LibcallName(RTLIB::OGE_F32, "__mips16_gesf2");
253 SetMips16LibcallName(RTLIB::OGE_F64, "__mips16_gedf2");
254 SetMips16LibcallName(RTLIB::OLT_F32, "__mips16_ltsf2");
255 SetMips16LibcallName(RTLIB::OLT_F64, "__mips16_ltdf2");
256 SetMips16LibcallName(RTLIB::OLE_F32, "__mips16_lesf2");
257 SetMips16LibcallName(RTLIB::OLE_F64, "__mips16_ledf2");
258 SetMips16LibcallName(RTLIB::OGT_F32, "__mips16_gtsf2");
259 SetMips16LibcallName(RTLIB::OGT_F64, "__mips16_gtdf2");
260 SetMips16LibcallName(RTLIB::UO_F32, "__mips16_unordsf2");
261 SetMips16LibcallName(RTLIB::UO_F64, "__mips16_unorddf2");
262 SetMips16LibcallName(RTLIB::O_F32, "__mips16_unordsf2");
263 SetMips16LibcallName(RTLIB::O_F64, "__mips16_unorddf2");
267 MipsTargetLowering(MipsTargetMachine &TM)
268 : TargetLowering(TM, new MipsTargetObjectFile()),
269 Subtarget(&TM.getSubtarget<MipsSubtarget>()),
270 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()),
271 IsO32(Subtarget->isABI_O32()) {
273 // Mips does not have i1 type, so use i32 for
274 // setcc operations results (slt, sgt, ...).
275 setBooleanContents(ZeroOrOneBooleanContent);
276 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
278 // Set up the register classes
279 addRegisterClass(MVT::i32, &Mips::CPURegsRegClass);
282 addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass);
284 if (Subtarget->inMips16Mode()) {
285 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
287 setMips16HardFloatLibCalls();
290 if (Subtarget->hasDSP()) {
291 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
293 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
294 addRegisterClass(VecTys[i], &Mips::DSPRegsRegClass);
296 // Expand all builtin opcodes.
297 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
298 setOperationAction(Opc, VecTys[i], Expand);
300 setOperationAction(ISD::LOAD, VecTys[i], Legal);
301 setOperationAction(ISD::STORE, VecTys[i], Legal);
302 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
306 if (!TM.Options.UseSoftFloat) {
307 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
309 // When dealing with single precision only, use libcalls
310 if (!Subtarget->isSingleFloat()) {
312 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
314 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
318 // Load extented operations for i1 types must be promoted
319 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
320 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
321 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
323 // MIPS doesn't have extending float->double load/store
324 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
325 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
327 // Used by legalize types to correctly generate the setcc result.
328 // Without this, every float setcc comes with a AND/OR with the result,
329 // we don't want this, since the fpcmp result goes to a flag register,
330 // which is used implicitly by brcond and select operations.
331 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
333 // Mips Custom Operations
334 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
335 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
336 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
337 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
338 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
339 setOperationAction(ISD::SELECT, MVT::f32, Custom);
340 setOperationAction(ISD::SELECT, MVT::f64, Custom);
341 setOperationAction(ISD::SELECT, MVT::i32, Custom);
342 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
343 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
344 setOperationAction(ISD::SETCC, MVT::f32, Custom);
345 setOperationAction(ISD::SETCC, MVT::f64, Custom);
346 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
347 setOperationAction(ISD::VASTART, MVT::Other, Custom);
348 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
349 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
350 if (Subtarget->inMips16Mode()) {
351 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
352 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
355 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
356 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
358 if (!Subtarget->inMips16Mode()) {
359 setOperationAction(ISD::LOAD, MVT::i32, Custom);
360 setOperationAction(ISD::STORE, MVT::i32, Custom);
363 if (!TM.Options.NoNaNsFPMath) {
364 setOperationAction(ISD::FABS, MVT::f32, Custom);
365 setOperationAction(ISD::FABS, MVT::f64, Custom);
369 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
370 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
371 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
372 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
373 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
374 setOperationAction(ISD::SELECT, MVT::i64, Custom);
375 setOperationAction(ISD::LOAD, MVT::i64, Custom);
376 setOperationAction(ISD::STORE, MVT::i64, Custom);
380 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
381 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
382 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
385 setOperationAction(ISD::ADD, MVT::i32, Custom);
387 setOperationAction(ISD::ADD, MVT::i64, Custom);
389 setOperationAction(ISD::SDIV, MVT::i32, Expand);
390 setOperationAction(ISD::SREM, MVT::i32, Expand);
391 setOperationAction(ISD::UDIV, MVT::i32, Expand);
392 setOperationAction(ISD::UREM, MVT::i32, Expand);
393 setOperationAction(ISD::SDIV, MVT::i64, Expand);
394 setOperationAction(ISD::SREM, MVT::i64, Expand);
395 setOperationAction(ISD::UDIV, MVT::i64, Expand);
396 setOperationAction(ISD::UREM, MVT::i64, Expand);
398 // Operations not directly supported by Mips.
399 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
400 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
401 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
402 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
403 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
404 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
405 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
406 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
407 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
408 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
409 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
410 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
411 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
412 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
414 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
415 setOperationAction(ISD::ROTL, MVT::i32, Expand);
416 setOperationAction(ISD::ROTL, MVT::i64, Expand);
417 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
418 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
420 if (!Subtarget->hasMips32r2())
421 setOperationAction(ISD::ROTR, MVT::i32, Expand);
423 if (!Subtarget->hasMips64r2())
424 setOperationAction(ISD::ROTR, MVT::i64, Expand);
426 setOperationAction(ISD::FSIN, MVT::f32, Expand);
427 setOperationAction(ISD::FSIN, MVT::f64, Expand);
428 setOperationAction(ISD::FCOS, MVT::f32, Expand);
429 setOperationAction(ISD::FCOS, MVT::f64, Expand);
430 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
431 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
432 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
433 setOperationAction(ISD::FPOW, MVT::f32, Expand);
434 setOperationAction(ISD::FPOW, MVT::f64, Expand);
435 setOperationAction(ISD::FLOG, MVT::f32, Expand);
436 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
437 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
438 setOperationAction(ISD::FEXP, MVT::f32, Expand);
439 setOperationAction(ISD::FMA, MVT::f32, Expand);
440 setOperationAction(ISD::FMA, MVT::f64, Expand);
441 setOperationAction(ISD::FREM, MVT::f32, Expand);
442 setOperationAction(ISD::FREM, MVT::f64, Expand);
444 if (!TM.Options.NoNaNsFPMath) {
445 setOperationAction(ISD::FNEG, MVT::f32, Expand);
446 setOperationAction(ISD::FNEG, MVT::f64, Expand);
449 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
450 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
451 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
452 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
454 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
456 setOperationAction(ISD::VAARG, MVT::Other, Expand);
457 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
458 setOperationAction(ISD::VAEND, MVT::Other, Expand);
460 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
461 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
463 // Use the default for now
464 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
465 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
467 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
468 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
469 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
470 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
472 if (Subtarget->inMips16Mode()) {
473 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
474 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
475 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
476 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
477 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
478 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
479 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
480 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
481 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
482 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
483 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
484 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
487 setInsertFencesForAtomic(true);
489 if (!Subtarget->hasSEInReg()) {
490 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
491 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
494 if (!Subtarget->hasBitCount()) {
495 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
496 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
499 if (!Subtarget->hasSwap()) {
500 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
501 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
505 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom);
506 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom);
507 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom);
508 setTruncStoreAction(MVT::i64, MVT::i32, Custom);
511 setTargetDAGCombine(ISD::ADDE);
512 setTargetDAGCombine(ISD::SUBE);
513 setTargetDAGCombine(ISD::SDIVREM);
514 setTargetDAGCombine(ISD::UDIVREM);
515 setTargetDAGCombine(ISD::SELECT);
516 setTargetDAGCombine(ISD::AND);
517 setTargetDAGCombine(ISD::OR);
518 setTargetDAGCombine(ISD::ADD);
520 setMinFunctionAlignment(HasMips64 ? 3 : 2);
522 setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP);
523 computeRegisterProperties();
525 setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0);
526 setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1);
528 MaxStoresPerMemcpy = 16;
532 MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
533 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
535 if (Subtarget->inMips16Mode())
549 EVT MipsTargetLowering::getSetCCResultType(EVT VT) const {
552 return VT.changeVectorElementTypeToInteger();
556 // Transforms a subgraph in CurDAG if the following pattern is found:
557 // (addc multLo, Lo0), (adde multHi, Hi0),
559 // multHi/Lo: product of multiplication
560 // Lo0: initial value of Lo register
561 // Hi0: initial value of Hi register
562 // Return true if pattern matching was successful.
563 static bool SelectMadd(SDNode *ADDENode, SelectionDAG *CurDAG) {
564 // ADDENode's second operand must be a flag output of an ADDC node in order
565 // for the matching to be successful.
566 SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
568 if (ADDCNode->getOpcode() != ISD::ADDC)
571 SDValue MultHi = ADDENode->getOperand(0);
572 SDValue MultLo = ADDCNode->getOperand(0);
573 SDNode *MultNode = MultHi.getNode();
574 unsigned MultOpc = MultHi.getOpcode();
576 // MultHi and MultLo must be generated by the same node,
577 if (MultLo.getNode() != MultNode)
580 // and it must be a multiplication.
581 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
584 // MultLo amd MultHi must be the first and second output of MultNode
586 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
589 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
590 // of the values of MultNode, in which case MultNode will be removed in later
592 // If there exist users other than ADDENode or ADDCNode, this function returns
593 // here, which will result in MultNode being mapped to a single MULT
594 // instruction node rather than a pair of MULT and MADD instructions being
596 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
599 SDValue Chain = CurDAG->getEntryNode();
600 DebugLoc dl = ADDENode->getDebugLoc();
602 // create MipsMAdd(u) node
603 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
605 SDValue MAdd = CurDAG->getNode(MultOpc, dl, MVT::Glue,
606 MultNode->getOperand(0),// Factor 0
607 MultNode->getOperand(1),// Factor 1
608 ADDCNode->getOperand(1),// Lo0
609 ADDENode->getOperand(1));// Hi0
611 // create CopyFromReg nodes
612 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
614 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
616 CopyFromLo.getValue(2));
618 // replace uses of adde and addc here
619 if (!SDValue(ADDCNode, 0).use_empty())
620 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo);
622 if (!SDValue(ADDENode, 0).use_empty())
623 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi);
629 // Transforms a subgraph in CurDAG if the following pattern is found:
630 // (addc Lo0, multLo), (sube Hi0, multHi),
632 // multHi/Lo: product of multiplication
633 // Lo0: initial value of Lo register
634 // Hi0: initial value of Hi register
635 // Return true if pattern matching was successful.
636 static bool SelectMsub(SDNode *SUBENode, SelectionDAG *CurDAG) {
637 // SUBENode's second operand must be a flag output of an SUBC node in order
638 // for the matching to be successful.
639 SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
641 if (SUBCNode->getOpcode() != ISD::SUBC)
644 SDValue MultHi = SUBENode->getOperand(1);
645 SDValue MultLo = SUBCNode->getOperand(1);
646 SDNode *MultNode = MultHi.getNode();
647 unsigned MultOpc = MultHi.getOpcode();
649 // MultHi and MultLo must be generated by the same node,
650 if (MultLo.getNode() != MultNode)
653 // and it must be a multiplication.
654 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
657 // MultLo amd MultHi must be the first and second output of MultNode
659 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
662 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
663 // of the values of MultNode, in which case MultNode will be removed in later
665 // If there exist users other than SUBENode or SUBCNode, this function returns
666 // here, which will result in MultNode being mapped to a single MULT
667 // instruction node rather than a pair of MULT and MSUB instructions being
669 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
672 SDValue Chain = CurDAG->getEntryNode();
673 DebugLoc dl = SUBENode->getDebugLoc();
675 // create MipsSub(u) node
676 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
678 SDValue MSub = CurDAG->getNode(MultOpc, dl, MVT::Glue,
679 MultNode->getOperand(0),// Factor 0
680 MultNode->getOperand(1),// Factor 1
681 SUBCNode->getOperand(0),// Lo0
682 SUBENode->getOperand(0));// Hi0
684 // create CopyFromReg nodes
685 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
687 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
689 CopyFromLo.getValue(2));
691 // replace uses of sube and subc here
692 if (!SDValue(SUBCNode, 0).use_empty())
693 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo);
695 if (!SDValue(SUBENode, 0).use_empty())
696 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi);
701 static SDValue PerformADDECombine(SDNode *N, SelectionDAG &DAG,
702 TargetLowering::DAGCombinerInfo &DCI,
703 const MipsSubtarget *Subtarget) {
704 if (DCI.isBeforeLegalize())
707 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
709 return SDValue(N, 0);
714 static SDValue PerformSUBECombine(SDNode *N, SelectionDAG &DAG,
715 TargetLowering::DAGCombinerInfo &DCI,
716 const MipsSubtarget *Subtarget) {
717 if (DCI.isBeforeLegalize())
720 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
722 return SDValue(N, 0);
727 static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG &DAG,
728 TargetLowering::DAGCombinerInfo &DCI,
729 const MipsSubtarget *Subtarget) {
730 if (DCI.isBeforeLegalizeOps())
733 EVT Ty = N->getValueType(0);
734 unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64;
735 unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64;
736 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem :
738 DebugLoc dl = N->getDebugLoc();
740 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue,
741 N->getOperand(0), N->getOperand(1));
742 SDValue InChain = DAG.getEntryNode();
743 SDValue InGlue = DivRem;
746 if (N->hasAnyUseOfValue(0)) {
747 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, LO, Ty,
749 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
750 InChain = CopyFromLo.getValue(1);
751 InGlue = CopyFromLo.getValue(2);
755 if (N->hasAnyUseOfValue(1)) {
756 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl,
758 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
764 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
766 default: llvm_unreachable("Unknown fp condition code!");
768 case ISD::SETOEQ: return Mips::FCOND_OEQ;
769 case ISD::SETUNE: return Mips::FCOND_UNE;
771 case ISD::SETOLT: return Mips::FCOND_OLT;
773 case ISD::SETOGT: return Mips::FCOND_OGT;
775 case ISD::SETOLE: return Mips::FCOND_OLE;
777 case ISD::SETOGE: return Mips::FCOND_OGE;
778 case ISD::SETULT: return Mips::FCOND_ULT;
779 case ISD::SETULE: return Mips::FCOND_ULE;
780 case ISD::SETUGT: return Mips::FCOND_UGT;
781 case ISD::SETUGE: return Mips::FCOND_UGE;
782 case ISD::SETUO: return Mips::FCOND_UN;
783 case ISD::SETO: return Mips::FCOND_OR;
785 case ISD::SETONE: return Mips::FCOND_ONE;
786 case ISD::SETUEQ: return Mips::FCOND_UEQ;
791 // Returns true if condition code has to be inverted.
792 static bool InvertFPCondCode(Mips::CondCode CC) {
793 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
796 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
797 "Illegal Condition Code");
802 // Creates and returns an FPCmp node from a setcc node.
803 // Returns Op if setcc is not a floating point comparison.
804 static SDValue CreateFPCmp(SelectionDAG &DAG, const SDValue &Op) {
805 // must be a SETCC node
806 if (Op.getOpcode() != ISD::SETCC)
809 SDValue LHS = Op.getOperand(0);
811 if (!LHS.getValueType().isFloatingPoint())
814 SDValue RHS = Op.getOperand(1);
815 DebugLoc dl = Op.getDebugLoc();
817 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
818 // node if necessary.
819 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
821 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS,
822 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
825 // Creates and returns a CMovFPT/F node.
826 static SDValue CreateCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
827 SDValue False, DebugLoc DL) {
828 bool invert = InvertFPCondCode((Mips::CondCode)
829 cast<ConstantSDNode>(Cond.getOperand(2))
832 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
833 True.getValueType(), True, False, Cond);
836 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
837 TargetLowering::DAGCombinerInfo &DCI,
838 const MipsSubtarget *Subtarget) {
839 if (DCI.isBeforeLegalizeOps())
842 SDValue SetCC = N->getOperand(0);
844 if ((SetCC.getOpcode() != ISD::SETCC) ||
845 !SetCC.getOperand(0).getValueType().isInteger())
848 SDValue False = N->getOperand(2);
849 EVT FalseTy = False.getValueType();
851 if (!FalseTy.isInteger())
854 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False);
856 if (!CN || CN->getZExtValue())
859 const DebugLoc DL = N->getDebugLoc();
860 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
861 SDValue True = N->getOperand(1);
863 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
864 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
866 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
869 static SDValue PerformANDCombine(SDNode *N, SelectionDAG &DAG,
870 TargetLowering::DAGCombinerInfo &DCI,
871 const MipsSubtarget *Subtarget) {
872 // Pattern match EXT.
873 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
874 // => ext $dst, $src, size, pos
875 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
878 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
879 unsigned ShiftRightOpc = ShiftRight.getOpcode();
881 // Op's first operand must be a shift right.
882 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
885 // The second operand of the shift must be an immediate.
887 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
890 uint64_t Pos = CN->getZExtValue();
891 uint64_t SMPos, SMSize;
893 // Op's second operand must be a shifted mask.
894 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
895 !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize))
898 // Return if the shifted mask does not start at bit 0 or the sum of its size
899 // and Pos exceeds the word's size.
900 EVT ValTy = N->getValueType(0);
901 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
904 return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), ValTy,
905 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32),
906 DAG.getConstant(SMSize, MVT::i32));
909 static SDValue PerformORCombine(SDNode *N, SelectionDAG &DAG,
910 TargetLowering::DAGCombinerInfo &DCI,
911 const MipsSubtarget *Subtarget) {
912 // Pattern match INS.
913 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
914 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
915 // => ins $dst, $src, size, pos, $src1
916 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
919 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
920 uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
923 // See if Op's first operand matches (and $src1 , mask0).
924 if (And0.getOpcode() != ISD::AND)
927 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
928 !IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
931 // See if Op's second operand matches (and (shl $src, pos), mask1).
932 if (And1.getOpcode() != ISD::AND)
935 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
936 !IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
939 // The shift masks must have the same position and size.
940 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
943 SDValue Shl = And1.getOperand(0);
944 if (Shl.getOpcode() != ISD::SHL)
947 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
950 unsigned Shamt = CN->getZExtValue();
952 // Return if the shift amount and the first bit position of mask are not the
954 EVT ValTy = N->getValueType(0);
955 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
958 return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), ValTy, Shl.getOperand(0),
959 DAG.getConstant(SMPos0, MVT::i32),
960 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
963 static SDValue PerformADDCombine(SDNode *N, SelectionDAG &DAG,
964 TargetLowering::DAGCombinerInfo &DCI,
965 const MipsSubtarget *Subtarget) {
966 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
968 if (DCI.isBeforeLegalizeOps())
971 SDValue Add = N->getOperand(1);
973 if (Add.getOpcode() != ISD::ADD)
976 SDValue Lo = Add.getOperand(1);
978 if ((Lo.getOpcode() != MipsISD::Lo) ||
979 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
982 EVT ValTy = N->getValueType(0);
983 DebugLoc DL = N->getDebugLoc();
985 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
987 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
990 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
992 SelectionDAG &DAG = DCI.DAG;
993 unsigned opc = N->getOpcode();
998 return PerformADDECombine(N, DAG, DCI, Subtarget);
1000 return PerformSUBECombine(N, DAG, DCI, Subtarget);
1003 return PerformDivRemCombine(N, DAG, DCI, Subtarget);
1005 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
1007 return PerformANDCombine(N, DAG, DCI, Subtarget);
1009 return PerformORCombine(N, DAG, DCI, Subtarget);
1011 return PerformADDCombine(N, DAG, DCI, Subtarget);
1018 MipsTargetLowering::LowerOperationWrapper(SDNode *N,
1019 SmallVectorImpl<SDValue> &Results,
1020 SelectionDAG &DAG) const {
1021 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
1023 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
1024 Results.push_back(Res.getValue(I));
1028 MipsTargetLowering::ReplaceNodeResults(SDNode *N,
1029 SmallVectorImpl<SDValue> &Results,
1030 SelectionDAG &DAG) const {
1031 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
1033 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
1034 Results.push_back(Res.getValue(I));
1037 SDValue MipsTargetLowering::
1038 LowerOperation(SDValue Op, SelectionDAG &DAG) const
1040 switch (Op.getOpcode())
1042 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
1043 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
1044 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
1045 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
1046 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
1047 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
1048 case ISD::SELECT: return LowerSELECT(Op, DAG);
1049 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
1050 case ISD::SETCC: return LowerSETCC(Op, DAG);
1051 case ISD::VASTART: return LowerVASTART(Op, DAG);
1052 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
1053 case ISD::FABS: return LowerFABS(Op, DAG);
1054 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
1055 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
1056 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
1057 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG);
1058 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
1059 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
1060 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG, true);
1061 case ISD::SRL_PARTS: return LowerShiftRightParts(Op, DAG, false);
1062 case ISD::LOAD: return LowerLOAD(Op, DAG);
1063 case ISD::STORE: return LowerSTORE(Op, DAG);
1064 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
1065 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
1066 case ISD::ADD: return LowerADD(Op, DAG);
1071 //===----------------------------------------------------------------------===//
1072 // Lower helper functions
1073 //===----------------------------------------------------------------------===//
1075 // AddLiveIn - This helper function adds the specified physical register to the
1076 // MachineFunction as a live in value. It also creates a corresponding
1077 // virtual register for it.
1079 AddLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
1081 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
1082 MF.getRegInfo().addLiveIn(PReg, VReg);
1086 // Get fp branch code (not opcode) from condition code.
1087 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
1088 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
1089 return Mips::BRANCH_T;
1091 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
1092 "Invalid CondCode.");
1094 return Mips::BRANCH_F;
1098 static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB,
1100 const MipsSubtarget *Subtarget,
1101 const TargetInstrInfo *TII,
1102 bool isFPCmp, unsigned Opc) {
1103 // There is no need to expand CMov instructions if target has
1104 // conditional moves.
1105 if (Subtarget->hasCondMov())
1108 // To "insert" a SELECT_CC instruction, we actually have to insert the
1109 // diamond control-flow pattern. The incoming instruction knows the
1110 // destination vreg to set, the condition code register to branch on, the
1111 // true/false values to select between, and a branch opcode to use.
1112 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1113 MachineFunction::iterator It = BB;
1120 // bNE r1, r0, copy1MBB
1121 // fallthrough --> copy0MBB
1122 MachineBasicBlock *thisMBB = BB;
1123 MachineFunction *F = BB->getParent();
1124 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1125 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1126 F->insert(It, copy0MBB);
1127 F->insert(It, sinkMBB);
1129 // Transfer the remainder of BB and its successor edges to sinkMBB.
1130 sinkMBB->splice(sinkMBB->begin(), BB,
1131 llvm::next(MachineBasicBlock::iterator(MI)),
1133 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
1135 // Next, add the true and fallthrough blocks as its successors.
1136 BB->addSuccessor(copy0MBB);
1137 BB->addSuccessor(sinkMBB);
1139 // Emit the right instruction according to the type of the operands compared
1141 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
1143 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg())
1144 .addReg(Mips::ZERO).addMBB(sinkMBB);
1147 // %FalseValue = ...
1148 // # fallthrough to sinkMBB
1151 // Update machine-CFG edges
1152 BB->addSuccessor(sinkMBB);
1155 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
1160 BuildMI(*BB, BB->begin(), dl,
1161 TII->get(Mips::PHI), MI->getOperand(0).getReg())
1162 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
1163 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
1165 BuildMI(*BB, BB->begin(), dl,
1166 TII->get(Mips::PHI), MI->getOperand(0).getReg())
1167 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB)
1168 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
1170 MI->eraseFromParent(); // The pseudo instruction is gone now.
1176 MipsTargetLowering::EmitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
1178 // bposge32_pseudo $vr0
1188 // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
1190 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
1191 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1192 const TargetRegisterClass *RC = &Mips::CPURegsRegClass;
1193 DebugLoc DL = MI->getDebugLoc();
1194 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1195 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
1196 MachineFunction *F = BB->getParent();
1197 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
1198 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
1199 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
1202 F->insert(It, Sink);
1204 // Transfer the remainder of BB and its successor edges to Sink.
1205 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
1207 Sink->transferSuccessorsAndUpdatePHIs(BB);
1210 BB->addSuccessor(FBB);
1211 BB->addSuccessor(TBB);
1212 FBB->addSuccessor(Sink);
1213 TBB->addSuccessor(Sink);
1215 // Insert the real bposge32 instruction to $BB.
1216 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
1219 unsigned VR2 = RegInfo.createVirtualRegister(RC);
1220 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
1221 .addReg(Mips::ZERO).addImm(0);
1222 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
1225 unsigned VR1 = RegInfo.createVirtualRegister(RC);
1226 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
1227 .addReg(Mips::ZERO).addImm(1);
1229 // Insert phi function to $Sink.
1230 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
1231 MI->getOperand(0).getReg())
1232 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
1234 MI->eraseFromParent(); // The pseudo instruction is gone now.
1238 MachineBasicBlock *MipsTargetLowering::EmitSel16(unsigned Opc, MachineInstr *MI,
1239 MachineBasicBlock *BB) const {
1240 if (DontExpandCondPseudos16)
1242 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1243 DebugLoc dl = MI->getDebugLoc();
1244 // To "insert" a SELECT_CC instruction, we actually have to insert the
1245 // diamond control-flow pattern. The incoming instruction knows the
1246 // destination vreg to set, the condition code register to branch on, the
1247 // true/false values to select between, and a branch opcode to use.
1248 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1249 MachineFunction::iterator It = BB;
1256 // bNE r1, r0, copy1MBB
1257 // fallthrough --> copy0MBB
1258 MachineBasicBlock *thisMBB = BB;
1259 MachineFunction *F = BB->getParent();
1260 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1261 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1262 F->insert(It, copy0MBB);
1263 F->insert(It, sinkMBB);
1265 // Transfer the remainder of BB and its successor edges to sinkMBB.
1266 sinkMBB->splice(sinkMBB->begin(), BB,
1267 llvm::next(MachineBasicBlock::iterator(MI)),
1269 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
1271 // Next, add the true and fallthrough blocks as its successors.
1272 BB->addSuccessor(copy0MBB);
1273 BB->addSuccessor(sinkMBB);
1275 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(3).getReg())
1279 // %FalseValue = ...
1280 // # fallthrough to sinkMBB
1283 // Update machine-CFG edges
1284 BB->addSuccessor(sinkMBB);
1287 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
1291 BuildMI(*BB, BB->begin(), dl,
1292 TII->get(Mips::PHI), MI->getOperand(0).getReg())
1293 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
1294 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
1296 MI->eraseFromParent(); // The pseudo instruction is gone now.
1300 MachineBasicBlock *MipsTargetLowering::EmitSelT16
1301 (unsigned Opc1, unsigned Opc2,
1302 MachineInstr *MI, MachineBasicBlock *BB) const {
1303 if (DontExpandCondPseudos16)
1305 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1306 DebugLoc dl = MI->getDebugLoc();
1307 // To "insert" a SELECT_CC instruction, we actually have to insert the
1308 // diamond control-flow pattern. The incoming instruction knows the
1309 // destination vreg to set, the condition code register to branch on, the
1310 // true/false values to select between, and a branch opcode to use.
1311 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1312 MachineFunction::iterator It = BB;
1319 // bNE r1, r0, copy1MBB
1320 // fallthrough --> copy0MBB
1321 MachineBasicBlock *thisMBB = BB;
1322 MachineFunction *F = BB->getParent();
1323 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1324 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1325 F->insert(It, copy0MBB);
1326 F->insert(It, sinkMBB);
1328 // Transfer the remainder of BB and its successor edges to sinkMBB.
1329 sinkMBB->splice(sinkMBB->begin(), BB,
1330 llvm::next(MachineBasicBlock::iterator(MI)),
1332 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
1334 // Next, add the true and fallthrough blocks as its successors.
1335 BB->addSuccessor(copy0MBB);
1336 BB->addSuccessor(sinkMBB);
1338 BuildMI(BB, dl, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
1339 .addReg(MI->getOperand(4).getReg());
1340 BuildMI(BB, dl, TII->get(Opc1)).addMBB(sinkMBB);
1343 // %FalseValue = ...
1344 // # fallthrough to sinkMBB
1347 // Update machine-CFG edges
1348 BB->addSuccessor(sinkMBB);
1351 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
1355 BuildMI(*BB, BB->begin(), dl,
1356 TII->get(Mips::PHI), MI->getOperand(0).getReg())
1357 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
1358 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
1360 MI->eraseFromParent(); // The pseudo instruction is gone now.
1366 MachineBasicBlock *MipsTargetLowering::EmitSeliT16
1367 (unsigned Opc1, unsigned Opc2,
1368 MachineInstr *MI, MachineBasicBlock *BB) const {
1369 if (DontExpandCondPseudos16)
1371 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1372 DebugLoc dl = MI->getDebugLoc();
1373 // To "insert" a SELECT_CC instruction, we actually have to insert the
1374 // diamond control-flow pattern. The incoming instruction knows the
1375 // destination vreg to set, the condition code register to branch on, the
1376 // true/false values to select between, and a branch opcode to use.
1377 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1378 MachineFunction::iterator It = BB;
1385 // bNE r1, r0, copy1MBB
1386 // fallthrough --> copy0MBB
1387 MachineBasicBlock *thisMBB = BB;
1388 MachineFunction *F = BB->getParent();
1389 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1390 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1391 F->insert(It, copy0MBB);
1392 F->insert(It, sinkMBB);
1394 // Transfer the remainder of BB and its successor edges to sinkMBB.
1395 sinkMBB->splice(sinkMBB->begin(), BB,
1396 llvm::next(MachineBasicBlock::iterator(MI)),
1398 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
1400 // Next, add the true and fallthrough blocks as its successors.
1401 BB->addSuccessor(copy0MBB);
1402 BB->addSuccessor(sinkMBB);
1404 BuildMI(BB, dl, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
1405 .addImm(MI->getOperand(4).getImm());
1406 BuildMI(BB, dl, TII->get(Opc1)).addMBB(sinkMBB);
1409 // %FalseValue = ...
1410 // # fallthrough to sinkMBB
1413 // Update machine-CFG edges
1414 BB->addSuccessor(sinkMBB);
1417 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
1421 BuildMI(*BB, BB->begin(), dl,
1422 TII->get(Mips::PHI), MI->getOperand(0).getReg())
1423 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
1424 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
1426 MI->eraseFromParent(); // The pseudo instruction is gone now.
1433 *MipsTargetLowering::EmitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc,
1435 MachineBasicBlock *BB) const {
1436 if (DontExpandCondPseudos16)
1438 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1439 unsigned regX = MI->getOperand(0).getReg();
1440 unsigned regY = MI->getOperand(1).getReg();
1441 MachineBasicBlock *target = MI->getOperand(2).getMBB();
1442 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addReg(regY);
1443 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target);
1444 MI->eraseFromParent(); // The pseudo instruction is gone now.
1449 MachineBasicBlock *MipsTargetLowering::EmitFEXT_T8I8I16_ins(
1450 unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc,
1451 MachineInstr *MI, MachineBasicBlock *BB) const {
1452 if (DontExpandCondPseudos16)
1454 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1455 unsigned regX = MI->getOperand(0).getReg();
1456 int64_t imm = MI->getOperand(1).getImm();
1457 MachineBasicBlock *target = MI->getOperand(2).getMBB();
1461 else if (isUInt<16>(imm))
1464 llvm_unreachable("immediate field not usable");
1465 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addImm(imm);
1466 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target);
1467 MI->eraseFromParent(); // The pseudo instruction is gone now.
1472 static unsigned Mips16WhichOp8uOr16simm
1473 (unsigned shortOp, unsigned longOp, int64_t Imm) {
1476 else if (isInt<16>(Imm))
1479 llvm_unreachable("immediate field not usable");
1482 MachineBasicBlock *MipsTargetLowering::EmitFEXT_CCRX16_ins(
1484 MachineInstr *MI, MachineBasicBlock *BB) const {
1485 if (DontExpandCondPseudos16)
1487 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1488 unsigned CC = MI->getOperand(0).getReg();
1489 unsigned regX = MI->getOperand(1).getReg();
1490 unsigned regY = MI->getOperand(2).getReg();
1491 BuildMI(*BB, MI, MI->getDebugLoc(),
1492 TII->get(SltOpc)).addReg(regX).addReg(regY);
1493 BuildMI(*BB, MI, MI->getDebugLoc(),
1494 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8);
1495 MI->eraseFromParent(); // The pseudo instruction is gone now.
1498 MachineBasicBlock *MipsTargetLowering::EmitFEXT_CCRXI16_ins(
1499 unsigned SltiOpc, unsigned SltiXOpc,
1500 MachineInstr *MI, MachineBasicBlock *BB )const {
1501 if (DontExpandCondPseudos16)
1503 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1504 unsigned CC = MI->getOperand(0).getReg();
1505 unsigned regX = MI->getOperand(1).getReg();
1506 int64_t Imm = MI->getOperand(2).getImm();
1507 unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm);
1508 BuildMI(*BB, MI, MI->getDebugLoc(),
1509 TII->get(SltOpc)).addReg(regX).addImm(Imm);
1510 BuildMI(*BB, MI, MI->getDebugLoc(),
1511 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8);
1512 MI->eraseFromParent(); // The pseudo instruction is gone now.
1517 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1518 MachineBasicBlock *BB) const {
1519 switch (MI->getOpcode()) {
1521 llvm_unreachable("Unexpected instr type to insert");
1522 case Mips::ATOMIC_LOAD_ADD_I8:
1523 case Mips::ATOMIC_LOAD_ADD_I8_P8:
1524 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
1525 case Mips::ATOMIC_LOAD_ADD_I16:
1526 case Mips::ATOMIC_LOAD_ADD_I16_P8:
1527 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
1528 case Mips::ATOMIC_LOAD_ADD_I32:
1529 case Mips::ATOMIC_LOAD_ADD_I32_P8:
1530 return EmitAtomicBinary(MI, BB, 4, Mips::ADDu);
1531 case Mips::ATOMIC_LOAD_ADD_I64:
1532 case Mips::ATOMIC_LOAD_ADD_I64_P8:
1533 return EmitAtomicBinary(MI, BB, 8, Mips::DADDu);
1535 case Mips::ATOMIC_LOAD_AND_I8:
1536 case Mips::ATOMIC_LOAD_AND_I8_P8:
1537 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
1538 case Mips::ATOMIC_LOAD_AND_I16:
1539 case Mips::ATOMIC_LOAD_AND_I16_P8:
1540 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
1541 case Mips::ATOMIC_LOAD_AND_I32:
1542 case Mips::ATOMIC_LOAD_AND_I32_P8:
1543 return EmitAtomicBinary(MI, BB, 4, Mips::AND);
1544 case Mips::ATOMIC_LOAD_AND_I64:
1545 case Mips::ATOMIC_LOAD_AND_I64_P8:
1546 return EmitAtomicBinary(MI, BB, 8, Mips::AND64);
1548 case Mips::ATOMIC_LOAD_OR_I8:
1549 case Mips::ATOMIC_LOAD_OR_I8_P8:
1550 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
1551 case Mips::ATOMIC_LOAD_OR_I16:
1552 case Mips::ATOMIC_LOAD_OR_I16_P8:
1553 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
1554 case Mips::ATOMIC_LOAD_OR_I32:
1555 case Mips::ATOMIC_LOAD_OR_I32_P8:
1556 return EmitAtomicBinary(MI, BB, 4, Mips::OR);
1557 case Mips::ATOMIC_LOAD_OR_I64:
1558 case Mips::ATOMIC_LOAD_OR_I64_P8:
1559 return EmitAtomicBinary(MI, BB, 8, Mips::OR64);
1561 case Mips::ATOMIC_LOAD_XOR_I8:
1562 case Mips::ATOMIC_LOAD_XOR_I8_P8:
1563 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
1564 case Mips::ATOMIC_LOAD_XOR_I16:
1565 case Mips::ATOMIC_LOAD_XOR_I16_P8:
1566 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
1567 case Mips::ATOMIC_LOAD_XOR_I32:
1568 case Mips::ATOMIC_LOAD_XOR_I32_P8:
1569 return EmitAtomicBinary(MI, BB, 4, Mips::XOR);
1570 case Mips::ATOMIC_LOAD_XOR_I64:
1571 case Mips::ATOMIC_LOAD_XOR_I64_P8:
1572 return EmitAtomicBinary(MI, BB, 8, Mips::XOR64);
1574 case Mips::ATOMIC_LOAD_NAND_I8:
1575 case Mips::ATOMIC_LOAD_NAND_I8_P8:
1576 return EmitAtomicBinaryPartword(MI, BB, 1, 0, true);
1577 case Mips::ATOMIC_LOAD_NAND_I16:
1578 case Mips::ATOMIC_LOAD_NAND_I16_P8:
1579 return EmitAtomicBinaryPartword(MI, BB, 2, 0, true);
1580 case Mips::ATOMIC_LOAD_NAND_I32:
1581 case Mips::ATOMIC_LOAD_NAND_I32_P8:
1582 return EmitAtomicBinary(MI, BB, 4, 0, true);
1583 case Mips::ATOMIC_LOAD_NAND_I64:
1584 case Mips::ATOMIC_LOAD_NAND_I64_P8:
1585 return EmitAtomicBinary(MI, BB, 8, 0, true);
1587 case Mips::ATOMIC_LOAD_SUB_I8:
1588 case Mips::ATOMIC_LOAD_SUB_I8_P8:
1589 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
1590 case Mips::ATOMIC_LOAD_SUB_I16:
1591 case Mips::ATOMIC_LOAD_SUB_I16_P8:
1592 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
1593 case Mips::ATOMIC_LOAD_SUB_I32:
1594 case Mips::ATOMIC_LOAD_SUB_I32_P8:
1595 return EmitAtomicBinary(MI, BB, 4, Mips::SUBu);
1596 case Mips::ATOMIC_LOAD_SUB_I64:
1597 case Mips::ATOMIC_LOAD_SUB_I64_P8:
1598 return EmitAtomicBinary(MI, BB, 8, Mips::DSUBu);
1600 case Mips::ATOMIC_SWAP_I8:
1601 case Mips::ATOMIC_SWAP_I8_P8:
1602 return EmitAtomicBinaryPartword(MI, BB, 1, 0);
1603 case Mips::ATOMIC_SWAP_I16:
1604 case Mips::ATOMIC_SWAP_I16_P8:
1605 return EmitAtomicBinaryPartword(MI, BB, 2, 0);
1606 case Mips::ATOMIC_SWAP_I32:
1607 case Mips::ATOMIC_SWAP_I32_P8:
1608 return EmitAtomicBinary(MI, BB, 4, 0);
1609 case Mips::ATOMIC_SWAP_I64:
1610 case Mips::ATOMIC_SWAP_I64_P8:
1611 return EmitAtomicBinary(MI, BB, 8, 0);
1613 case Mips::ATOMIC_CMP_SWAP_I8:
1614 case Mips::ATOMIC_CMP_SWAP_I8_P8:
1615 return EmitAtomicCmpSwapPartword(MI, BB, 1);
1616 case Mips::ATOMIC_CMP_SWAP_I16:
1617 case Mips::ATOMIC_CMP_SWAP_I16_P8:
1618 return EmitAtomicCmpSwapPartword(MI, BB, 2);
1619 case Mips::ATOMIC_CMP_SWAP_I32:
1620 case Mips::ATOMIC_CMP_SWAP_I32_P8:
1621 return EmitAtomicCmpSwap(MI, BB, 4);
1622 case Mips::ATOMIC_CMP_SWAP_I64:
1623 case Mips::ATOMIC_CMP_SWAP_I64_P8:
1624 return EmitAtomicCmpSwap(MI, BB, 8);
1625 case Mips::BPOSGE32_PSEUDO:
1626 return EmitBPOSGE32(MI, BB);
1628 return EmitSel16(Mips::BeqzRxImm16, MI, BB);
1630 return EmitSel16(Mips::BnezRxImm16, MI, BB);
1631 case Mips::SelTBteqZCmpi:
1632 return EmitSeliT16(Mips::BteqzX16, Mips::CmpiRxImmX16, MI, BB);
1633 case Mips::SelTBteqZSlti:
1634 return EmitSeliT16(Mips::BteqzX16, Mips::SltiRxImmX16, MI, BB);
1635 case Mips::SelTBteqZSltiu:
1636 return EmitSeliT16(Mips::BteqzX16, Mips::SltiuRxImmX16, MI, BB);
1637 case Mips::SelTBtneZCmpi:
1638 return EmitSeliT16(Mips::BtnezX16, Mips::CmpiRxImmX16, MI, BB);
1639 case Mips::SelTBtneZSlti:
1640 return EmitSeliT16(Mips::BtnezX16, Mips::SltiRxImmX16, MI, BB);
1641 case Mips::SelTBtneZSltiu:
1642 return EmitSeliT16(Mips::BtnezX16, Mips::SltiuRxImmX16, MI, BB);
1643 case Mips::SelTBteqZCmp:
1644 return EmitSelT16(Mips::BteqzX16, Mips::CmpRxRy16, MI, BB);
1645 case Mips::SelTBteqZSlt:
1646 return EmitSelT16(Mips::BteqzX16, Mips::SltRxRy16, MI, BB);
1647 case Mips::SelTBteqZSltu:
1648 return EmitSelT16(Mips::BteqzX16, Mips::SltuRxRy16, MI, BB);
1649 case Mips::SelTBtneZCmp:
1650 return EmitSelT16(Mips::BtnezX16, Mips::CmpRxRy16, MI, BB);
1651 case Mips::SelTBtneZSlt:
1652 return EmitSelT16(Mips::BtnezX16, Mips::SltRxRy16, MI, BB);
1653 case Mips::SelTBtneZSltu:
1654 return EmitSelT16(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB);
1655 case Mips::BteqzT8CmpX16:
1656 return EmitFEXT_T8I816_ins(Mips::BteqzX16, Mips::CmpRxRy16, MI, BB);
1657 case Mips::BteqzT8SltX16:
1658 return EmitFEXT_T8I816_ins(Mips::BteqzX16, Mips::SltRxRy16, MI, BB);
1659 case Mips::BteqzT8SltuX16:
1660 // TBD: figure out a way to get this or remove the instruction
1662 return EmitFEXT_T8I816_ins(Mips::BteqzX16, Mips::SltuRxRy16, MI, BB);
1663 case Mips::BtnezT8CmpX16:
1664 return EmitFEXT_T8I816_ins(Mips::BtnezX16, Mips::CmpRxRy16, MI, BB);
1665 case Mips::BtnezT8SltX16:
1666 return EmitFEXT_T8I816_ins(Mips::BtnezX16, Mips::SltRxRy16, MI, BB);
1667 case Mips::BtnezT8SltuX16:
1668 // TBD: figure out a way to get this or remove the instruction
1670 return EmitFEXT_T8I816_ins(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB);
1671 case Mips::BteqzT8CmpiX16: return EmitFEXT_T8I8I16_ins(
1672 Mips::BteqzX16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, MI, BB);
1673 case Mips::BteqzT8SltiX16: return EmitFEXT_T8I8I16_ins(
1674 Mips::BteqzX16, Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
1675 case Mips::BteqzT8SltiuX16: return EmitFEXT_T8I8I16_ins(
1676 Mips::BteqzX16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
1677 case Mips::BtnezT8CmpiX16: return EmitFEXT_T8I8I16_ins(
1678 Mips::BtnezX16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, MI, BB);
1679 case Mips::BtnezT8SltiX16: return EmitFEXT_T8I8I16_ins(
1680 Mips::BtnezX16, Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
1681 case Mips::BtnezT8SltiuX16: return EmitFEXT_T8I8I16_ins(
1682 Mips::BtnezX16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
1684 case Mips::SltCCRxRy16:
1685 return EmitFEXT_CCRX16_ins(Mips::SltRxRy16, MI, BB);
1687 case Mips::SltiCCRxImmX16:
1688 return EmitFEXT_CCRXI16_ins
1689 (Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
1690 case Mips::SltiuCCRxImmX16:
1691 return EmitFEXT_CCRXI16_ins
1692 (Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
1693 case Mips::SltuCCRxRy16:
1694 return EmitFEXT_CCRX16_ins
1695 (Mips::SltuRxRy16, MI, BB);
1699 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1700 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
1702 MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
1703 unsigned Size, unsigned BinOpcode,
1705 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
1707 MachineFunction *MF = BB->getParent();
1708 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1709 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1710 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1711 DebugLoc dl = MI->getDebugLoc();
1712 unsigned LL, SC, AND, NOR, ZERO, BEQ;
1715 LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1716 SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1723 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
1724 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
1727 ZERO = Mips::ZERO_64;
1731 unsigned OldVal = MI->getOperand(0).getReg();
1732 unsigned Ptr = MI->getOperand(1).getReg();
1733 unsigned Incr = MI->getOperand(2).getReg();
1735 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1736 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1737 unsigned Success = RegInfo.createVirtualRegister(RC);
1739 // insert new blocks after the current block
1740 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1741 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1742 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1743 MachineFunction::iterator It = BB;
1745 MF->insert(It, loopMBB);
1746 MF->insert(It, exitMBB);
1748 // Transfer the remainder of BB and its successor edges to exitMBB.
1749 exitMBB->splice(exitMBB->begin(), BB,
1750 llvm::next(MachineBasicBlock::iterator(MI)),
1752 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1756 // fallthrough --> loopMBB
1757 BB->addSuccessor(loopMBB);
1758 loopMBB->addSuccessor(loopMBB);
1759 loopMBB->addSuccessor(exitMBB);
1762 // ll oldval, 0(ptr)
1763 // <binop> storeval, oldval, incr
1764 // sc success, storeval, 0(ptr)
1765 // beq success, $0, loopMBB
1767 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
1769 // and andres, oldval, incr
1770 // nor storeval, $0, andres
1771 BuildMI(BB, dl, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
1772 BuildMI(BB, dl, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
1773 } else if (BinOpcode) {
1774 // <binop> storeval, oldval, incr
1775 BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
1779 BuildMI(BB, dl, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
1780 BuildMI(BB, dl, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
1782 MI->eraseFromParent(); // The instruction is gone now.
1788 MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
1789 MachineBasicBlock *BB,
1790 unsigned Size, unsigned BinOpcode,
1792 assert((Size == 1 || Size == 2) &&
1793 "Unsupported size for EmitAtomicBinaryPartial.");
1795 MachineFunction *MF = BB->getParent();
1796 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1797 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1798 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1799 DebugLoc dl = MI->getDebugLoc();
1800 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1801 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1803 unsigned Dest = MI->getOperand(0).getReg();
1804 unsigned Ptr = MI->getOperand(1).getReg();
1805 unsigned Incr = MI->getOperand(2).getReg();
1807 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1808 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1809 unsigned Mask = RegInfo.createVirtualRegister(RC);
1810 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1811 unsigned NewVal = RegInfo.createVirtualRegister(RC);
1812 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1813 unsigned Incr2 = RegInfo.createVirtualRegister(RC);
1814 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1815 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1816 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1817 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1818 unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
1819 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1820 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1821 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1822 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1823 unsigned SllRes = RegInfo.createVirtualRegister(RC);
1824 unsigned Success = RegInfo.createVirtualRegister(RC);
1826 // insert new blocks after the current block
1827 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1828 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1829 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1830 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1831 MachineFunction::iterator It = BB;
1833 MF->insert(It, loopMBB);
1834 MF->insert(It, sinkMBB);
1835 MF->insert(It, exitMBB);
1837 // Transfer the remainder of BB and its successor edges to exitMBB.
1838 exitMBB->splice(exitMBB->begin(), BB,
1839 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1840 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1842 BB->addSuccessor(loopMBB);
1843 loopMBB->addSuccessor(loopMBB);
1844 loopMBB->addSuccessor(sinkMBB);
1845 sinkMBB->addSuccessor(exitMBB);
1848 // addiu masklsb2,$0,-4 # 0xfffffffc
1849 // and alignedaddr,ptr,masklsb2
1850 // andi ptrlsb2,ptr,3
1851 // sll shiftamt,ptrlsb2,3
1852 // ori maskupper,$0,255 # 0xff
1853 // sll mask,maskupper,shiftamt
1854 // nor mask2,$0,mask
1855 // sll incr2,incr,shiftamt
1857 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1858 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
1859 .addReg(Mips::ZERO).addImm(-4);
1860 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
1861 .addReg(Ptr).addReg(MaskLSB2);
1862 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1863 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1864 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
1865 .addReg(Mips::ZERO).addImm(MaskImm);
1866 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
1867 .addReg(ShiftAmt).addReg(MaskUpper);
1868 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1869 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr);
1871 // atomic.load.binop
1873 // ll oldval,0(alignedaddr)
1874 // binop binopres,oldval,incr2
1875 // and newval,binopres,mask
1876 // and maskedoldval0,oldval,mask2
1877 // or storeval,maskedoldval0,newval
1878 // sc success,storeval,0(alignedaddr)
1879 // beq success,$0,loopMBB
1883 // ll oldval,0(alignedaddr)
1884 // and newval,incr2,mask
1885 // and maskedoldval0,oldval,mask2
1886 // or storeval,maskedoldval0,newval
1887 // sc success,storeval,0(alignedaddr)
1888 // beq success,$0,loopMBB
1891 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1893 // and andres, oldval, incr2
1894 // nor binopres, $0, andres
1895 // and newval, binopres, mask
1896 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1897 BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes)
1898 .addReg(Mips::ZERO).addReg(AndRes);
1899 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1900 } else if (BinOpcode) {
1901 // <binop> binopres, oldval, incr2
1902 // and newval, binopres, mask
1903 BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1904 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1905 } else {// atomic.swap
1906 // and newval, incr2, mask
1907 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1910 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
1911 .addReg(OldVal).addReg(Mask2);
1912 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
1913 .addReg(MaskedOldVal0).addReg(NewVal);
1914 BuildMI(BB, dl, TII->get(SC), Success)
1915 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1916 BuildMI(BB, dl, TII->get(Mips::BEQ))
1917 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
1920 // and maskedoldval1,oldval,mask
1921 // srl srlres,maskedoldval1,shiftamt
1922 // sll sllres,srlres,24
1923 // sra dest,sllres,24
1925 int64_t ShiftImm = (Size == 1) ? 24 : 16;
1927 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
1928 .addReg(OldVal).addReg(Mask);
1929 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
1930 .addReg(ShiftAmt).addReg(MaskedOldVal1);
1931 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
1932 .addReg(SrlRes).addImm(ShiftImm);
1933 BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
1934 .addReg(SllRes).addImm(ShiftImm);
1936 MI->eraseFromParent(); // The instruction is gone now.
1942 MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
1943 MachineBasicBlock *BB,
1944 unsigned Size) const {
1945 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
1947 MachineFunction *MF = BB->getParent();
1948 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1949 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1950 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1951 DebugLoc dl = MI->getDebugLoc();
1952 unsigned LL, SC, ZERO, BNE, BEQ;
1955 LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1956 SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1962 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
1963 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
1964 ZERO = Mips::ZERO_64;
1969 unsigned Dest = MI->getOperand(0).getReg();
1970 unsigned Ptr = MI->getOperand(1).getReg();
1971 unsigned OldVal = MI->getOperand(2).getReg();
1972 unsigned NewVal = MI->getOperand(3).getReg();
1974 unsigned Success = RegInfo.createVirtualRegister(RC);
1976 // insert new blocks after the current block
1977 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1978 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1979 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1980 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1981 MachineFunction::iterator It = BB;
1983 MF->insert(It, loop1MBB);
1984 MF->insert(It, loop2MBB);
1985 MF->insert(It, exitMBB);
1987 // Transfer the remainder of BB and its successor edges to exitMBB.
1988 exitMBB->splice(exitMBB->begin(), BB,
1989 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1990 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1994 // fallthrough --> loop1MBB
1995 BB->addSuccessor(loop1MBB);
1996 loop1MBB->addSuccessor(exitMBB);
1997 loop1MBB->addSuccessor(loop2MBB);
1998 loop2MBB->addSuccessor(loop1MBB);
1999 loop2MBB->addSuccessor(exitMBB);
2003 // bne dest, oldval, exitMBB
2005 BuildMI(BB, dl, TII->get(LL), Dest).addReg(Ptr).addImm(0);
2006 BuildMI(BB, dl, TII->get(BNE))
2007 .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
2010 // sc success, newval, 0(ptr)
2011 // beq success, $0, loop1MBB
2013 BuildMI(BB, dl, TII->get(SC), Success)
2014 .addReg(NewVal).addReg(Ptr).addImm(0);
2015 BuildMI(BB, dl, TII->get(BEQ))
2016 .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
2018 MI->eraseFromParent(); // The instruction is gone now.
2024 MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
2025 MachineBasicBlock *BB,
2026 unsigned Size) const {
2027 assert((Size == 1 || Size == 2) &&
2028 "Unsupported size for EmitAtomicCmpSwapPartial.");
2030 MachineFunction *MF = BB->getParent();
2031 MachineRegisterInfo &RegInfo = MF->getRegInfo();
2032 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
2033 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2034 DebugLoc dl = MI->getDebugLoc();
2035 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
2036 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
2038 unsigned Dest = MI->getOperand(0).getReg();
2039 unsigned Ptr = MI->getOperand(1).getReg();
2040 unsigned CmpVal = MI->getOperand(2).getReg();
2041 unsigned NewVal = MI->getOperand(3).getReg();
2043 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
2044 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
2045 unsigned Mask = RegInfo.createVirtualRegister(RC);
2046 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
2047 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
2048 unsigned OldVal = RegInfo.createVirtualRegister(RC);
2049 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
2050 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
2051 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
2052 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
2053 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
2054 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
2055 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
2056 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
2057 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
2058 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
2059 unsigned SllRes = RegInfo.createVirtualRegister(RC);
2060 unsigned Success = RegInfo.createVirtualRegister(RC);
2062 // insert new blocks after the current block
2063 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2064 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
2065 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
2066 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
2067 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
2068 MachineFunction::iterator It = BB;
2070 MF->insert(It, loop1MBB);
2071 MF->insert(It, loop2MBB);
2072 MF->insert(It, sinkMBB);
2073 MF->insert(It, exitMBB);
2075 // Transfer the remainder of BB and its successor edges to exitMBB.
2076 exitMBB->splice(exitMBB->begin(), BB,
2077 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
2078 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
2080 BB->addSuccessor(loop1MBB);
2081 loop1MBB->addSuccessor(sinkMBB);
2082 loop1MBB->addSuccessor(loop2MBB);
2083 loop2MBB->addSuccessor(loop1MBB);
2084 loop2MBB->addSuccessor(sinkMBB);
2085 sinkMBB->addSuccessor(exitMBB);
2087 // FIXME: computation of newval2 can be moved to loop2MBB.
2089 // addiu masklsb2,$0,-4 # 0xfffffffc
2090 // and alignedaddr,ptr,masklsb2
2091 // andi ptrlsb2,ptr,3
2092 // sll shiftamt,ptrlsb2,3
2093 // ori maskupper,$0,255 # 0xff
2094 // sll mask,maskupper,shiftamt
2095 // nor mask2,$0,mask
2096 // andi maskedcmpval,cmpval,255
2097 // sll shiftedcmpval,maskedcmpval,shiftamt
2098 // andi maskednewval,newval,255
2099 // sll shiftednewval,maskednewval,shiftamt
2100 int64_t MaskImm = (Size == 1) ? 255 : 65535;
2101 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
2102 .addReg(Mips::ZERO).addImm(-4);
2103 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
2104 .addReg(Ptr).addReg(MaskLSB2);
2105 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
2106 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
2107 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
2108 .addReg(Mips::ZERO).addImm(MaskImm);
2109 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
2110 .addReg(ShiftAmt).addReg(MaskUpper);
2111 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
2112 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal)
2113 .addReg(CmpVal).addImm(MaskImm);
2114 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal)
2115 .addReg(ShiftAmt).addReg(MaskedCmpVal);
2116 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal)
2117 .addReg(NewVal).addImm(MaskImm);
2118 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal)
2119 .addReg(ShiftAmt).addReg(MaskedNewVal);
2122 // ll oldval,0(alginedaddr)
2123 // and maskedoldval0,oldval,mask
2124 // bne maskedoldval0,shiftedcmpval,sinkMBB
2126 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
2127 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
2128 .addReg(OldVal).addReg(Mask);
2129 BuildMI(BB, dl, TII->get(Mips::BNE))
2130 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
2133 // and maskedoldval1,oldval,mask2
2134 // or storeval,maskedoldval1,shiftednewval
2135 // sc success,storeval,0(alignedaddr)
2136 // beq success,$0,loop1MBB
2138 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
2139 .addReg(OldVal).addReg(Mask2);
2140 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
2141 .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
2142 BuildMI(BB, dl, TII->get(SC), Success)
2143 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
2144 BuildMI(BB, dl, TII->get(Mips::BEQ))
2145 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
2148 // srl srlres,maskedoldval0,shiftamt
2149 // sll sllres,srlres,24
2150 // sra dest,sllres,24
2152 int64_t ShiftImm = (Size == 1) ? 24 : 16;
2154 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
2155 .addReg(ShiftAmt).addReg(MaskedOldVal0);
2156 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
2157 .addReg(SrlRes).addImm(ShiftImm);
2158 BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
2159 .addReg(SllRes).addImm(ShiftImm);
2161 MI->eraseFromParent(); // The instruction is gone now.
2166 //===----------------------------------------------------------------------===//
2167 // Misc Lower Operation implementation
2168 //===----------------------------------------------------------------------===//
2169 SDValue MipsTargetLowering::
2170 LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
2172 // The first operand is the chain, the second is the condition, the third is
2173 // the block to branch to if the condition is true.
2174 SDValue Chain = Op.getOperand(0);
2175 SDValue Dest = Op.getOperand(2);
2176 DebugLoc dl = Op.getDebugLoc();
2178 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1));
2180 // Return if flag is not set by a floating point comparison.
2181 if (CondRes.getOpcode() != MipsISD::FPCmp)
2184 SDValue CCNode = CondRes.getOperand(2);
2186 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
2187 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
2189 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
2193 SDValue MipsTargetLowering::
2194 LowerSELECT(SDValue Op, SelectionDAG &DAG) const
2196 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0));
2198 // Return if flag is not set by a floating point comparison.
2199 if (Cond.getOpcode() != MipsISD::FPCmp)
2202 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
2206 SDValue MipsTargetLowering::
2207 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
2209 DebugLoc DL = Op.getDebugLoc();
2210 EVT Ty = Op.getOperand(0).getValueType();
2211 SDValue Cond = DAG.getNode(ISD::SETCC, DL, getSetCCResultType(Ty),
2212 Op.getOperand(0), Op.getOperand(1),
2215 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2),
2219 SDValue MipsTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2220 SDValue Cond = CreateFPCmp(DAG, Op);
2222 assert(Cond.getOpcode() == MipsISD::FPCmp &&
2223 "Floating point operand expected.");
2225 SDValue True = DAG.getConstant(1, MVT::i32);
2226 SDValue False = DAG.getConstant(0, MVT::i32);
2228 return CreateCMovFP(DAG, Cond, True, False, Op.getDebugLoc());
2231 SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
2232 SelectionDAG &DAG) const {
2233 // FIXME there isn't actually debug info here
2234 DebugLoc dl = Op.getDebugLoc();
2235 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2237 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
2238 const MipsTargetObjectFile &TLOF =
2239 (const MipsTargetObjectFile&)getObjFileLowering();
2241 // %gp_rel relocation
2242 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
2243 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
2245 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl,
2246 DAG.getVTList(MVT::i32), &GA, 1);
2247 SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32);
2248 return DAG.getNode(ISD::ADD, dl, MVT::i32, GPReg, GPRelNode);
2251 // %hi/%lo relocation
2252 return getAddrNonPIC(Op, DAG);
2255 if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV)))
2256 return getAddrLocal(Op, DAG, HasMips64);
2259 return getAddrGlobalLargeGOT(Op, DAG, MipsII::MO_GOT_HI16,
2260 MipsII::MO_GOT_LO16);
2262 return getAddrGlobal(Op, DAG,
2263 HasMips64 ? MipsII::MO_GOT_DISP : MipsII::MO_GOT16);
2266 SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
2267 SelectionDAG &DAG) const {
2268 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64)
2269 return getAddrNonPIC(Op, DAG);
2271 return getAddrLocal(Op, DAG, HasMips64);
2274 SDValue MipsTargetLowering::
2275 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
2277 // If the relocation model is PIC, use the General Dynamic TLS Model or
2278 // Local Dynamic TLS model, otherwise use the Initial Exec or
2279 // Local Exec TLS Model.
2281 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2282 DebugLoc dl = GA->getDebugLoc();
2283 const GlobalValue *GV = GA->getGlobal();
2284 EVT PtrVT = getPointerTy();
2286 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
2288 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
2289 // General Dynamic and Local Dynamic TLS Model.
2290 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
2293 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, Flag);
2294 SDValue Argument = DAG.getNode(MipsISD::Wrapper, dl, PtrVT,
2295 GetGlobalReg(DAG, PtrVT), TGA);
2296 unsigned PtrSize = PtrVT.getSizeInBits();
2297 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
2299 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
2303 Entry.Node = Argument;
2305 Args.push_back(Entry);
2307 TargetLowering::CallLoweringInfo CLI(DAG.getEntryNode(), PtrTy,
2308 false, false, false, false, 0, CallingConv::C,
2309 /*isTailCall=*/false, /*doesNotRet=*/false,
2310 /*isReturnValueUsed=*/true,
2311 TlsGetAddr, Args, DAG, dl);
2312 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2314 SDValue Ret = CallResult.first;
2316 if (model != TLSModel::LocalDynamic)
2319 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2320 MipsII::MO_DTPREL_HI);
2321 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi);
2322 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2323 MipsII::MO_DTPREL_LO);
2324 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo);
2325 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Ret);
2326 return DAG.getNode(ISD::ADD, dl, PtrVT, Add, Lo);
2330 if (model == TLSModel::InitialExec) {
2331 // Initial Exec TLS Model
2332 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2333 MipsII::MO_GOTTPREL);
2334 TGA = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT),
2336 Offset = DAG.getLoad(PtrVT, dl,
2337 DAG.getEntryNode(), TGA, MachinePointerInfo(),
2338 false, false, false, 0);
2340 // Local Exec TLS Model
2341 assert(model == TLSModel::LocalExec);
2342 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2343 MipsII::MO_TPREL_HI);
2344 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2345 MipsII::MO_TPREL_LO);
2346 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi);
2347 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo);
2348 Offset = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
2351 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT);
2352 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
2355 SDValue MipsTargetLowering::
2356 LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
2358 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64)
2359 return getAddrNonPIC(Op, DAG);
2361 return getAddrLocal(Op, DAG, HasMips64);
2364 SDValue MipsTargetLowering::
2365 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
2367 // gp_rel relocation
2368 // FIXME: we should reference the constant pool using small data sections,
2369 // but the asm printer currently doesn't support this feature without
2370 // hacking it. This feature should come soon so we can uncomment the
2372 //if (IsInSmallSection(C->getType())) {
2373 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
2374 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
2375 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
2377 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64)
2378 return getAddrNonPIC(Op, DAG);
2380 return getAddrLocal(Op, DAG, HasMips64);
2383 SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
2384 MachineFunction &MF = DAG.getMachineFunction();
2385 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2387 DebugLoc dl = Op.getDebugLoc();
2388 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2391 // vastart just stores the address of the VarArgsFrameIndex slot into the
2392 // memory location argument.
2393 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2394 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
2395 MachinePointerInfo(SV), false, false, 0);
2398 static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
2399 EVT TyX = Op.getOperand(0).getValueType();
2400 EVT TyY = Op.getOperand(1).getValueType();
2401 SDValue Const1 = DAG.getConstant(1, MVT::i32);
2402 SDValue Const31 = DAG.getConstant(31, MVT::i32);
2403 DebugLoc DL = Op.getDebugLoc();
2406 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2408 SDValue X = (TyX == MVT::f32) ?
2409 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
2410 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2412 SDValue Y = (TyY == MVT::f32) ?
2413 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
2414 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
2418 // ext E, Y, 31, 1 ; extract bit31 of Y
2419 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X
2420 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
2421 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
2424 // srl SrlX, SllX, 1
2426 // sll SllY, SrlX, 31
2427 // or Or, SrlX, SllY
2428 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2429 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2430 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
2431 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
2432 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
2435 if (TyX == MVT::f32)
2436 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
2438 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2439 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
2440 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2443 static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
2444 unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
2445 unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
2446 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
2447 SDValue Const1 = DAG.getConstant(1, MVT::i32);
2448 DebugLoc DL = Op.getDebugLoc();
2450 // Bitcast to integer nodes.
2451 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
2452 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
2455 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
2456 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
2457 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
2458 DAG.getConstant(WidthY - 1, MVT::i32), Const1);
2460 if (WidthX > WidthY)
2461 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
2462 else if (WidthY > WidthX)
2463 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
2465 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
2466 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X);
2467 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
2470 // (d)sll SllX, X, 1
2471 // (d)srl SrlX, SllX, 1
2472 // (d)srl SrlY, Y, width(Y)-1
2473 // (d)sll SllY, SrlX, width(Y)-1
2474 // or Or, SrlX, SllY
2475 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
2476 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
2477 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
2478 DAG.getConstant(WidthY - 1, MVT::i32));
2480 if (WidthX > WidthY)
2481 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
2482 else if (WidthY > WidthX)
2483 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
2485 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
2486 DAG.getConstant(WidthX - 1, MVT::i32));
2487 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
2488 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
2492 MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2493 if (Subtarget->hasMips64())
2494 return LowerFCOPYSIGN64(Op, DAG, Subtarget->hasMips32r2());
2496 return LowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2());
2499 static SDValue LowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
2500 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
2501 DebugLoc DL = Op.getDebugLoc();
2503 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2505 SDValue X = (Op.getValueType() == MVT::f32) ?
2506 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
2507 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2512 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32,
2513 DAG.getRegister(Mips::ZERO, MVT::i32),
2514 DAG.getConstant(31, MVT::i32), Const1, X);
2516 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2517 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2520 if (Op.getValueType() == MVT::f32)
2521 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
2523 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2524 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
2525 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2528 static SDValue LowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
2529 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
2530 DebugLoc DL = Op.getDebugLoc();
2532 // Bitcast to integer node.
2533 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0));
2537 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64,
2538 DAG.getRegister(Mips::ZERO_64, MVT::i64),
2539 DAG.getConstant(63, MVT::i32), Const1, X);
2541 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
2542 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
2545 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res);
2549 MipsTargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
2550 if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64))
2551 return LowerFABS64(Op, DAG, Subtarget->hasMips32r2());
2553 return LowerFABS32(Op, DAG, Subtarget->hasMips32r2());
2556 SDValue MipsTargetLowering::
2557 LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2559 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
2560 "Frame address can only be determined for current frame.");
2562 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2563 MFI->setFrameAddressIsTaken(true);
2564 EVT VT = Op.getValueType();
2565 DebugLoc dl = Op.getDebugLoc();
2566 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2567 IsN64 ? Mips::FP_64 : Mips::FP, VT);
2571 SDValue MipsTargetLowering::LowerRETURNADDR(SDValue Op,
2572 SelectionDAG &DAG) const {
2574 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
2575 "Return address can be determined only for current frame.");
2577 MachineFunction &MF = DAG.getMachineFunction();
2578 MachineFrameInfo *MFI = MF.getFrameInfo();
2579 MVT VT = Op.getSimpleValueType();
2580 unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA;
2581 MFI->setReturnAddressIsTaken(true);
2583 // Return RA, which contains the return address. Mark it an implicit live-in.
2584 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
2585 return DAG.getCopyFromReg(DAG.getEntryNode(), Op.getDebugLoc(), Reg, VT);
2588 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is
2589 // generated from __builtin_eh_return (offset, handler)
2590 // The effect of this is to adjust the stack pointer by "offset"
2591 // and then branch to "handler".
2592 SDValue MipsTargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
2594 MachineFunction &MF = DAG.getMachineFunction();
2595 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2597 MipsFI->setCallsEhReturn();
2598 SDValue Chain = Op.getOperand(0);
2599 SDValue Offset = Op.getOperand(1);
2600 SDValue Handler = Op.getOperand(2);
2601 DebugLoc DL = Op.getDebugLoc();
2602 EVT Ty = IsN64 ? MVT::i64 : MVT::i32;
2604 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
2605 // EH_RETURN nodes, so that instructions are emitted back-to-back.
2606 unsigned OffsetReg = IsN64 ? Mips::V1_64 : Mips::V1;
2607 unsigned AddrReg = IsN64 ? Mips::V0_64 : Mips::V0;
2608 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
2609 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
2610 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
2611 DAG.getRegister(OffsetReg, Ty),
2612 DAG.getRegister(AddrReg, getPointerTy()),
2616 // TODO: set SType according to the desired memory barrier behavior.
2618 MipsTargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const {
2620 DebugLoc dl = Op.getDebugLoc();
2621 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
2622 DAG.getConstant(SType, MVT::i32));
2625 SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op,
2626 SelectionDAG &DAG) const {
2627 // FIXME: Need pseudo-fence for 'singlethread' fences
2628 // FIXME: Set SType for weaker fences where supported/appropriate.
2630 DebugLoc dl = Op.getDebugLoc();
2631 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
2632 DAG.getConstant(SType, MVT::i32));
2635 SDValue MipsTargetLowering::LowerShiftLeftParts(SDValue Op,
2636 SelectionDAG &DAG) const {
2637 DebugLoc DL = Op.getDebugLoc();
2638 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2639 SDValue Shamt = Op.getOperand(2);
2642 // lo = (shl lo, shamt)
2643 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
2646 // hi = (shl lo, shamt[4:0])
2647 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2648 DAG.getConstant(-1, MVT::i32));
2649 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo,
2650 DAG.getConstant(1, MVT::i32));
2651 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo,
2653 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt);
2654 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
2655 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt);
2656 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2657 DAG.getConstant(0x20, MVT::i32));
2658 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
2659 DAG.getConstant(0, MVT::i32), ShiftLeftLo);
2660 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or);
2662 SDValue Ops[2] = {Lo, Hi};
2663 return DAG.getMergeValues(Ops, 2, DL);
2666 SDValue MipsTargetLowering::LowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
2668 DebugLoc DL = Op.getDebugLoc();
2669 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2670 SDValue Shamt = Op.getOperand(2);
2673 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2675 // hi = (sra hi, shamt)
2677 // hi = (srl hi, shamt)
2680 // lo = (sra hi, shamt[4:0])
2681 // hi = (sra hi, 31)
2683 // lo = (srl hi, shamt[4:0])
2685 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2686 DAG.getConstant(-1, MVT::i32));
2687 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi,
2688 DAG.getConstant(1, MVT::i32));
2689 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not);
2690 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt);
2691 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
2692 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2694 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2695 DAG.getConstant(0x20, MVT::i32));
2696 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi,
2697 DAG.getConstant(31, MVT::i32));
2698 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or);
2699 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
2700 IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32),
2703 SDValue Ops[2] = {Lo, Hi};
2704 return DAG.getMergeValues(Ops, 2, DL);
2707 static SDValue CreateLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2708 SDValue Chain, SDValue Src, unsigned Offset) {
2709 SDValue Ptr = LD->getBasePtr();
2710 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2711 EVT BasePtrVT = Ptr.getValueType();
2712 DebugLoc DL = LD->getDebugLoc();
2713 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2716 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2717 DAG.getConstant(Offset, BasePtrVT));
2719 SDValue Ops[] = { Chain, Ptr, Src };
2720 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
2721 LD->getMemOperand());
2724 // Expand an unaligned 32 or 64-bit integer load node.
2725 SDValue MipsTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2726 LoadSDNode *LD = cast<LoadSDNode>(Op);
2727 EVT MemVT = LD->getMemoryVT();
2729 // Return if load is aligned or if MemVT is neither i32 nor i64.
2730 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2731 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2734 bool IsLittle = Subtarget->isLittle();
2735 EVT VT = Op.getValueType();
2736 ISD::LoadExtType ExtType = LD->getExtensionType();
2737 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2739 assert((VT == MVT::i32) || (VT == MVT::i64));
2742 // (set dst, (i64 (load baseptr)))
2744 // (set tmp, (ldl (add baseptr, 7), undef))
2745 // (set dst, (ldr baseptr, tmp))
2746 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2747 SDValue LDL = CreateLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2749 return CreateLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2753 SDValue LWL = CreateLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2755 SDValue LWR = CreateLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2759 // (set dst, (i32 (load baseptr))) or
2760 // (set dst, (i64 (sextload baseptr))) or
2761 // (set dst, (i64 (extload baseptr)))
2763 // (set tmp, (lwl (add baseptr, 3), undef))
2764 // (set dst, (lwr baseptr, tmp))
2765 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2766 (ExtType == ISD::EXTLOAD))
2769 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2772 // (set dst, (i64 (zextload baseptr)))
2774 // (set tmp0, (lwl (add baseptr, 3), undef))
2775 // (set tmp1, (lwr baseptr, tmp0))
2776 // (set tmp2, (shl tmp1, 32))
2777 // (set dst, (srl tmp2, 32))
2778 DebugLoc DL = LD->getDebugLoc();
2779 SDValue Const32 = DAG.getConstant(32, MVT::i32);
2780 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2781 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2782 SDValue Ops[] = { SRL, LWR.getValue(1) };
2783 return DAG.getMergeValues(Ops, 2, DL);
2786 static SDValue CreateStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2787 SDValue Chain, unsigned Offset) {
2788 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2789 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2790 DebugLoc DL = SD->getDebugLoc();
2791 SDVTList VTList = DAG.getVTList(MVT::Other);
2794 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2795 DAG.getConstant(Offset, BasePtrVT));
2797 SDValue Ops[] = { Chain, Value, Ptr };
2798 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
2799 SD->getMemOperand());
2802 // Expand an unaligned 32 or 64-bit integer store node.
2803 SDValue MipsTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2804 StoreSDNode *SD = cast<StoreSDNode>(Op);
2805 EVT MemVT = SD->getMemoryVT();
2807 // Return if store is aligned or if MemVT is neither i32 nor i64.
2808 if ((SD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2809 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2812 bool IsLittle = Subtarget->isLittle();
2813 SDValue Value = SD->getValue(), Chain = SD->getChain();
2814 EVT VT = Value.getValueType();
2817 // (store val, baseptr) or
2818 // (truncstore val, baseptr)
2820 // (swl val, (add baseptr, 3))
2821 // (swr val, baseptr)
2822 if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2823 SDValue SWL = CreateStoreLR(MipsISD::SWL, DAG, SD, Chain,
2825 return CreateStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2828 assert(VT == MVT::i64);
2831 // (store val, baseptr)
2833 // (sdl val, (add baseptr, 7))
2834 // (sdr val, baseptr)
2835 SDValue SDL = CreateStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2836 return CreateStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2839 // This function expands mips intrinsic nodes which have 64-bit input operands
2840 // or output values.
2842 // out64 = intrinsic-node in64
2844 // lo = copy (extract-element (in64, 0))
2845 // hi = copy (extract-element (in64, 1))
2846 // mips-specific-node
2849 // out64 = merge-values (v0, v1)
2851 static SDValue LowerDSPIntr(SDValue Op, SelectionDAG &DAG,
2852 unsigned Opc, bool HasI64In, bool HasI64Out) {
2853 DebugLoc DL = Op.getDebugLoc();
2854 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
2855 SDValue Chain = HasChainIn ? Op->getOperand(0) : DAG.getEntryNode();
2856 SmallVector<SDValue, 3> Ops;
2859 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
2860 Op->getOperand(1 + HasChainIn),
2861 DAG.getConstant(0, MVT::i32));
2862 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
2863 Op->getOperand(1 + HasChainIn),
2864 DAG.getConstant(1, MVT::i32));
2866 Chain = DAG.getCopyToReg(Chain, DL, Mips::LO, InLo, SDValue());
2867 Chain = DAG.getCopyToReg(Chain, DL, Mips::HI, InHi, Chain.getValue(1));
2869 Ops.push_back(Chain);
2870 Ops.append(Op->op_begin() + HasChainIn + 2, Op->op_end());
2871 Ops.push_back(Chain.getValue(1));
2873 Ops.push_back(Chain);
2874 Ops.append(Op->op_begin() + HasChainIn + 1, Op->op_end());
2878 return DAG.getNode(Opc, DL, Op->value_begin(), Op->getNumValues(),
2879 Ops.begin(), Ops.size());
2881 SDValue Intr = DAG.getNode(Opc, DL, DAG.getVTList(MVT::Other, MVT::Glue),
2882 Ops.begin(), Ops.size());
2883 SDValue OutLo = DAG.getCopyFromReg(Intr.getValue(0), DL, Mips::LO, MVT::i32,
2885 SDValue OutHi = DAG.getCopyFromReg(OutLo.getValue(1), DL, Mips::HI, MVT::i32,
2887 SDValue Out = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, OutLo, OutHi);
2892 SDValue Vals[] = { Out, OutHi.getValue(1) };
2893 return DAG.getMergeValues(Vals, 2, DL);
2896 SDValue MipsTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
2897 SelectionDAG &DAG) const {
2898 switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
2901 case Intrinsic::mips_shilo:
2902 return LowerDSPIntr(Op, DAG, MipsISD::SHILO, true, true);
2903 case Intrinsic::mips_dpau_h_qbl:
2904 return LowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL, true, true);
2905 case Intrinsic::mips_dpau_h_qbr:
2906 return LowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR, true, true);
2907 case Intrinsic::mips_dpsu_h_qbl:
2908 return LowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL, true, true);
2909 case Intrinsic::mips_dpsu_h_qbr:
2910 return LowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR, true, true);
2911 case Intrinsic::mips_dpa_w_ph:
2912 return LowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH, true, true);
2913 case Intrinsic::mips_dps_w_ph:
2914 return LowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH, true, true);
2915 case Intrinsic::mips_dpax_w_ph:
2916 return LowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH, true, true);
2917 case Intrinsic::mips_dpsx_w_ph:
2918 return LowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH, true, true);
2919 case Intrinsic::mips_mulsa_w_ph:
2920 return LowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH, true, true);
2921 case Intrinsic::mips_mult:
2922 return LowerDSPIntr(Op, DAG, MipsISD::MULT, false, true);
2923 case Intrinsic::mips_multu:
2924 return LowerDSPIntr(Op, DAG, MipsISD::MULTU, false, true);
2925 case Intrinsic::mips_madd:
2926 return LowerDSPIntr(Op, DAG, MipsISD::MADD_DSP, true, true);
2927 case Intrinsic::mips_maddu:
2928 return LowerDSPIntr(Op, DAG, MipsISD::MADDU_DSP, true, true);
2929 case Intrinsic::mips_msub:
2930 return LowerDSPIntr(Op, DAG, MipsISD::MSUB_DSP, true, true);
2931 case Intrinsic::mips_msubu:
2932 return LowerDSPIntr(Op, DAG, MipsISD::MSUBU_DSP, true, true);
2936 SDValue MipsTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
2937 SelectionDAG &DAG) const {
2938 switch (cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue()) {
2941 case Intrinsic::mips_extp:
2942 return LowerDSPIntr(Op, DAG, MipsISD::EXTP, true, false);
2943 case Intrinsic::mips_extpdp:
2944 return LowerDSPIntr(Op, DAG, MipsISD::EXTPDP, true, false);
2945 case Intrinsic::mips_extr_w:
2946 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_W, true, false);
2947 case Intrinsic::mips_extr_r_w:
2948 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W, true, false);
2949 case Intrinsic::mips_extr_rs_w:
2950 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W, true, false);
2951 case Intrinsic::mips_extr_s_h:
2952 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H, true, false);
2953 case Intrinsic::mips_mthlip:
2954 return LowerDSPIntr(Op, DAG, MipsISD::MTHLIP, true, true);
2955 case Intrinsic::mips_mulsaq_s_w_ph:
2956 return LowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH, true, true);
2957 case Intrinsic::mips_maq_s_w_phl:
2958 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL, true, true);
2959 case Intrinsic::mips_maq_s_w_phr:
2960 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR, true, true);
2961 case Intrinsic::mips_maq_sa_w_phl:
2962 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL, true, true);
2963 case Intrinsic::mips_maq_sa_w_phr:
2964 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR, true, true);
2965 case Intrinsic::mips_dpaq_s_w_ph:
2966 return LowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH, true, true);
2967 case Intrinsic::mips_dpsq_s_w_ph:
2968 return LowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH, true, true);
2969 case Intrinsic::mips_dpaq_sa_l_w:
2970 return LowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W, true, true);
2971 case Intrinsic::mips_dpsq_sa_l_w:
2972 return LowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W, true, true);
2973 case Intrinsic::mips_dpaqx_s_w_ph:
2974 return LowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH, true, true);
2975 case Intrinsic::mips_dpaqx_sa_w_ph:
2976 return LowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH, true, true);
2977 case Intrinsic::mips_dpsqx_s_w_ph:
2978 return LowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH, true, true);
2979 case Intrinsic::mips_dpsqx_sa_w_ph:
2980 return LowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH, true, true);
2984 SDValue MipsTargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
2985 if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR
2986 || cast<ConstantSDNode>
2987 (Op->getOperand(0).getOperand(0))->getZExtValue() != 0
2988 || Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET)
2992 // (add (frameaddr 0), (frame_to_args_offset))
2993 // results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to
2994 // (add FrameObject, 0)
2995 // where FrameObject is a fixed StackObject with offset 0 which points to
2996 // the old stack pointer.
2997 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2998 EVT ValTy = Op->getValueType(0);
2999 int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
3000 SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy);
3001 return DAG.getNode(ISD::ADD, Op->getDebugLoc(), ValTy, InArgsAddr,
3002 DAG.getConstant(0, ValTy));
3005 //===----------------------------------------------------------------------===//
3006 // Calling Convention Implementation
3007 //===----------------------------------------------------------------------===//
3009 //===----------------------------------------------------------------------===//
3010 // TODO: Implement a generic logic using tblgen that can support this.
3011 // Mips O32 ABI rules:
3013 // i32 - Passed in A0, A1, A2, A3 and stack
3014 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
3015 // an argument. Otherwise, passed in A1, A2, A3 and stack.
3016 // f64 - Only passed in two aliased f32 registers if no int reg has been used
3017 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
3018 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
3021 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
3022 //===----------------------------------------------------------------------===//
3024 static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
3025 MVT LocVT, CCValAssign::LocInfo LocInfo,
3026 ISD::ArgFlagsTy ArgFlags, CCState &State) {
3028 static const unsigned IntRegsSize=4, FloatRegsSize=2;
3030 static const uint16_t IntRegs[] = {
3031 Mips::A0, Mips::A1, Mips::A2, Mips::A3
3033 static const uint16_t F32Regs[] = {
3034 Mips::F12, Mips::F14
3036 static const uint16_t F64Regs[] = {
3040 // Do not process byval args here.
3041 if (ArgFlags.isByVal())
3044 // Promote i8 and i16
3045 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
3047 if (ArgFlags.isSExt())
3048 LocInfo = CCValAssign::SExt;
3049 else if (ArgFlags.isZExt())
3050 LocInfo = CCValAssign::ZExt;
3052 LocInfo = CCValAssign::AExt;
3057 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
3058 // is true: function is vararg, argument is 3rd or higher, there is previous
3059 // argument which is not f32 or f64.
3060 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
3061 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
3062 unsigned OrigAlign = ArgFlags.getOrigAlign();
3063 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
3065 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
3066 Reg = State.AllocateReg(IntRegs, IntRegsSize);
3067 // If this is the first part of an i64 arg,
3068 // the allocated register must be either A0 or A2.
3069 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
3070 Reg = State.AllocateReg(IntRegs, IntRegsSize);
3072 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
3073 // Allocate int register and shadow next int register. If first
3074 // available register is Mips::A1 or Mips::A3, shadow it too.
3075 Reg = State.AllocateReg(IntRegs, IntRegsSize);
3076 if (Reg == Mips::A1 || Reg == Mips::A3)
3077 Reg = State.AllocateReg(IntRegs, IntRegsSize);
3078 State.AllocateReg(IntRegs, IntRegsSize);
3080 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
3081 // we are guaranteed to find an available float register
3082 if (ValVT == MVT::f32) {
3083 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
3084 // Shadow int register
3085 State.AllocateReg(IntRegs, IntRegsSize);
3087 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
3088 // Shadow int registers
3089 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
3090 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
3091 State.AllocateReg(IntRegs, IntRegsSize);
3092 State.AllocateReg(IntRegs, IntRegsSize);
3095 llvm_unreachable("Cannot handle this ValVT.");
3098 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3,
3100 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
3102 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3107 #include "MipsGenCallingConv.inc"
3109 //===----------------------------------------------------------------------===//
3110 // Call Calling Convention Implementation
3111 //===----------------------------------------------------------------------===//
3113 static const unsigned O32IntRegsSize = 4;
3115 // Return next O32 integer argument register.
3116 static unsigned getNextIntArgReg(unsigned Reg) {
3117 assert((Reg == Mips::A0) || (Reg == Mips::A2));
3118 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
3121 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3122 /// for tail call optimization.
3123 bool MipsTargetLowering::
3124 IsEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
3125 unsigned NextStackOffset,
3126 const MipsFunctionInfo& FI) const {
3127 if (!EnableMipsTailCalls)
3130 // No tail call optimization for mips16.
3131 if (Subtarget->inMips16Mode())
3134 // Return false if either the callee or caller has a byval argument.
3135 if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
3138 // Return true if the callee's argument area is no larger than the
3140 return NextStackOffset <= FI.getIncomingArgSize();
3144 MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
3145 SDValue Chain, SDValue Arg, DebugLoc DL,
3146 bool IsTailCall, SelectionDAG &DAG) const {
3148 SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
3149 DAG.getIntPtrConstant(Offset));
3150 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false,
3154 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3155 int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
3156 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
3157 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
3158 /*isVolatile=*/ true, false, 0);
3162 // The Mips16 hard float is a crazy quilt inherited from gcc. I have a much
3163 // cleaner way to do all of this but it will have to wait until the traditional
3164 // gcc mechanism is completed.
3166 // For Pic, in order for Mips16 code to call Mips32 code which according the abi
3167 // have either arguments or returned values placed in floating point registers,
3168 // we use a set of helper functions. (This includes functions which return type
3169 // complex which on Mips are returned in a pair of floating point registers).
3171 // This is an encoding that we inherited from gcc.
3172 // In Mips traditional O32, N32 ABI, floating point numbers are passed in
3173 // floating point argument registers 1,2 only when the first and optionally
3174 // the second arguments are float (sf) or double (df).
3175 // For Mips16 we are only concerned with the situations where floating point
3176 // arguments are being passed in floating point registers by the ABI, because
3177 // Mips16 mode code cannot execute floating point instructions to load those
3178 // values and hence helper functions are needed.
3179 // The possibilities are (), (sf), (sf, sf), (sf, df), (df), (df, sf), (df, df)
3180 // the helper function suffixs for these are:
3181 // 0, 1, 5, 9, 2, 6, 10
3182 // this suffix can then be calculated as follows:
3183 // for a given argument Arg:
3184 // Arg1x, Arg2x = 1 : Arg is sf
3186 // 0: Arg is neither sf or df
3187 // So this stub is the string for number Arg1x + Arg2x*4.
3188 // However not all numbers between 0 and 10 are possible, we check anyway and
3189 // assert if the impossible exists.
3192 unsigned int MipsTargetLowering::getMips16HelperFunctionStubNumber
3193 (ArgListTy &Args) const {
3194 unsigned int resultNum = 0;
3195 if (Args.size() >= 1) {
3196 Type *t = Args[0].Ty;
3197 if (t->isFloatTy()) {
3200 else if (t->isDoubleTy()) {
3205 if (Args.size() >=2) {
3206 Type *t = Args[1].Ty;
3207 if (t->isFloatTy()) {
3210 else if (t->isDoubleTy()) {
3219 // prefixs are attached to stub numbers depending on the return type .
3220 // return type: float sf_
3222 // single complex sc_
3223 // double complext dc_
3227 // The full name of a helper function is__mips16_call_stub +
3228 // return type dependent prefix + stub number
3231 // This is something that probably should be in a different source file and
3232 // perhaps done differently but my main purpose is to not waste runtime
3233 // on something that we can enumerate in the source. Another possibility is
3234 // to have a python script to generate these mapping tables. This will do
3235 // for now. There are a whole series of helper function mapping arrays, one
3236 // for each return type class as outlined above. There there are 11 possible
3237 // entries. Ones with 0 are ones which should never be selected
3239 // All the arrays are similar except for ones which return neither
3240 // sf, df, sc, dc, in which only care about ones which have sf or df as a
3243 #define P_ "__mips16_call_stub_"
3244 #define MAX_STUB_NUMBER 10
3245 #define T1 P "1", P "2", 0, 0, P "5", P "6", 0, 0, P "9", P "10"
3246 #define T P "0" , T1
3248 static char const * vMips16Helper[MAX_STUB_NUMBER+1] =
3252 static char const * sfMips16Helper[MAX_STUB_NUMBER+1] =
3256 static char const * dfMips16Helper[MAX_STUB_NUMBER+1] =
3260 static char const * scMips16Helper[MAX_STUB_NUMBER+1] =
3264 static char const * dcMips16Helper[MAX_STUB_NUMBER+1] =
3270 const char* MipsTargetLowering::
3271 getMips16HelperFunction
3272 (Type* RetTy, ArgListTy &Args, bool &needHelper) const {
3273 const unsigned int stubNum = getMips16HelperFunctionStubNumber(Args);
3275 const unsigned int maxStubNum = 10;
3276 assert(stubNum <= maxStubNum);
3277 const bool validStubNum[maxStubNum+1] =
3278 {true, true, true, false, false, true, true, false, false, true, true};
3279 assert(validStubNum[stubNum]);
3282 if (RetTy->isFloatTy()) {
3283 result = sfMips16Helper[stubNum];
3285 else if (RetTy ->isDoubleTy()) {
3286 result = dfMips16Helper[stubNum];
3288 else if (RetTy->isStructTy()) {
3289 // check if it's complex
3290 if (RetTy->getNumContainedTypes() == 2) {
3291 if ((RetTy->getContainedType(0)->isFloatTy()) &&
3292 (RetTy->getContainedType(1)->isFloatTy())) {
3293 result = scMips16Helper[stubNum];
3295 else if ((RetTy->getContainedType(0)->isDoubleTy()) &&
3296 (RetTy->getContainedType(1)->isDoubleTy())) {
3297 result = dcMips16Helper[stubNum];
3300 llvm_unreachable("Uncovered condition");
3304 llvm_unreachable("Uncovered condition");
3312 result = vMips16Helper[stubNum];
3318 /// LowerCall - functions arguments are copied from virtual regs to
3319 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
3321 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3322 SmallVectorImpl<SDValue> &InVals) const {
3323 SelectionDAG &DAG = CLI.DAG;
3324 DebugLoc &dl = CLI.DL;
3325 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
3326 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
3327 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
3328 SDValue Chain = CLI.Chain;
3329 SDValue Callee = CLI.Callee;
3330 bool &isTailCall = CLI.IsTailCall;
3331 CallingConv::ID CallConv = CLI.CallConv;
3332 bool isVarArg = CLI.IsVarArg;
3334 const char* mips16HelperFunction = 0;
3335 bool needMips16Helper = false;
3337 if (Subtarget->inMips16Mode() && getTargetMachine().Options.UseSoftFloat &&
3340 // currently we don't have symbols tagged with the mips16 or mips32
3341 // qualifier so we will assume that we don't know what kind it is.
3342 // and generate the helper
3344 bool lookupHelper = true;
3345 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3346 if (noHelperNeeded.find(S->getSymbol()) != noHelperNeeded.end()) {
3347 lookupHelper = false;
3350 if (lookupHelper) mips16HelperFunction =
3351 getMips16HelperFunction(CLI.RetTy, CLI.Args, needMips16Helper);
3354 MachineFunction &MF = DAG.getMachineFunction();
3355 MachineFrameInfo *MFI = MF.getFrameInfo();
3356 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();
3357 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
3359 // Analyze operands of the call, assigning locations to each operand.
3360 SmallVector<CCValAssign, 16> ArgLocs;
3361 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3362 getTargetMachine(), ArgLocs, *DAG.getContext());
3363 MipsCC MipsCCInfo(CallConv, IsO32, CCInfo);
3365 MipsCCInfo.analyzeCallOperands(Outs, isVarArg);
3367 // Get a count of how many bytes are to be pushed on the stack.
3368 unsigned NextStackOffset = CCInfo.getNextStackOffset();
3370 // Check if it's really possible to do a tail call.
3373 IsEligibleForTailCallOptimization(MipsCCInfo, NextStackOffset,
3374 *MF.getInfo<MipsFunctionInfo>());
3379 // Chain is the output chain of the last Load/Store or CopyToReg node.
3380 // ByValChain is the output chain of the last Memcpy node created for copying
3381 // byval arguments to the stack.
3382 unsigned StackAlignment = TFL->getStackAlignment();
3383 NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);
3384 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
3387 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal);
3389 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl,
3390 IsN64 ? Mips::SP_64 : Mips::SP,
3393 // With EABI is it possible to have 16 args on registers.
3394 std::deque< std::pair<unsigned, SDValue> > RegsToPass;
3395 SmallVector<SDValue, 8> MemOpChains;
3396 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin();
3398 // Walk the register/memloc assignments, inserting copies/loads.
3399 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3400 SDValue Arg = OutVals[i];
3401 CCValAssign &VA = ArgLocs[i];
3402 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
3403 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3406 if (Flags.isByVal()) {
3407 assert(Flags.getByValSize() &&
3408 "ByVal args of size 0 should have been ignored by front-end.");
3409 assert(ByValArg != MipsCCInfo.byval_end());
3410 assert(!isTailCall &&
3411 "Do not tail-call optimize if there is a byval argument.");
3412 passByValArg(Chain, dl, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
3413 MipsCCInfo, *ByValArg, Flags, Subtarget->isLittle());
3418 // Promote the value if needed.
3419 switch (VA.getLocInfo()) {
3420 default: llvm_unreachable("Unknown loc info!");
3421 case CCValAssign::Full:
3422 if (VA.isRegLoc()) {
3423 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
3424 (ValVT == MVT::f64 && LocVT == MVT::i64))
3425 Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg);
3426 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
3427 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
3428 Arg, DAG.getConstant(0, MVT::i32));
3429 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
3430 Arg, DAG.getConstant(1, MVT::i32));
3431 if (!Subtarget->isLittle())
3433 unsigned LocRegLo = VA.getLocReg();
3434 unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
3435 RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
3436 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
3441 case CCValAssign::SExt:
3442 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, LocVT, Arg);
3444 case CCValAssign::ZExt:
3445 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, LocVT, Arg);
3447 case CCValAssign::AExt:
3448 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, LocVT, Arg);
3452 // Arguments that can be passed on register must be kept at
3453 // RegsToPass vector
3454 if (VA.isRegLoc()) {
3455 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3459 // Register can't get to this point...
3460 assert(VA.isMemLoc());
3462 // emit ISD::STORE whichs stores the
3463 // parameter value to a stack Location
3464 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
3465 Chain, Arg, dl, isTailCall, DAG));
3468 // Transform all store nodes into one single node because all store
3469 // nodes are independent of each other.
3470 if (!MemOpChains.empty())
3471 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3472 &MemOpChains[0], MemOpChains.size());
3474 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
3475 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
3476 // node so that legalize doesn't hack it.
3477 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25
3478 bool GlobalOrExternal = false, InternalLinkage = false;
3481 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3483 InternalLinkage = G->getGlobal()->hasInternalLinkage();
3485 if (InternalLinkage)
3486 Callee = getAddrLocal(Callee, DAG, HasMips64);
3488 Callee = getAddrGlobalLargeGOT(Callee, DAG, MipsII::MO_CALL_HI16,
3489 MipsII::MO_CALL_LO16);
3491 Callee = getAddrGlobal(Callee, DAG, MipsII::MO_GOT_CALL);
3493 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0,
3494 MipsII::MO_NO_FLAG);
3495 GlobalOrExternal = true;
3497 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3498 if (!IsN64 && !IsPIC) // !N64 && static
3499 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3500 MipsII::MO_NO_FLAG);
3502 Callee = getAddrGlobalLargeGOT(Callee, DAG, MipsII::MO_CALL_HI16,
3503 MipsII::MO_CALL_LO16);
3505 Callee = getAddrGlobal(Callee, DAG, MipsII::MO_GOT_CALL);
3507 GlobalOrExternal = true;
3510 SDValue JumpTarget = Callee;
3512 // T9 should contain the address of the callee function if
3513 // -reloction-model=pic or it is an indirect call.
3514 if (IsPICCall || !GlobalOrExternal) {
3515 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
3516 unsigned V0Reg = Mips::V0;
3517 if (needMips16Helper) {
3518 RegsToPass.push_front(std::make_pair(V0Reg, Callee));
3519 JumpTarget = DAG.getExternalSymbol(
3520 mips16HelperFunction, getPointerTy());
3521 JumpTarget = getAddrGlobal(JumpTarget, DAG, MipsII::MO_GOT);
3524 RegsToPass.push_front(std::make_pair(T9Reg, Callee));
3526 if (!Subtarget->inMips16Mode())
3527 JumpTarget = SDValue();
3531 // Insert node "GP copy globalreg" before call to function.
3533 // R_MIPS_CALL* operators (emitted when non-internal functions are called
3534 // in PIC mode) allow symbols to be resolved via lazy binding.
3535 // The lazy binding stub requires GP to point to the GOT.
3536 if (IsPICCall && !InternalLinkage) {
3537 unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP;
3538 EVT Ty = IsN64 ? MVT::i64 : MVT::i32;
3539 RegsToPass.push_back(std::make_pair(GPReg, GetGlobalReg(DAG, Ty)));
3542 // Build a sequence of copy-to-reg nodes chained together with token
3543 // chain and flag operands which copy the outgoing args into registers.
3544 // The InFlag in necessary since all emitted instructions must be
3548 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3549 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3550 RegsToPass[i].second, InFlag);
3551 InFlag = Chain.getValue(1);
3554 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
3555 // = Chain, Callee, Reg#1, Reg#2, ...
3557 // Returns a chain & a flag for retval copy to use.
3558 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3559 SmallVector<SDValue, 8> Ops(1, Chain);
3561 if (JumpTarget.getNode())
3562 Ops.push_back(JumpTarget);
3564 // Add argument registers to the end of the list so that they are
3565 // known live into the call.
3566 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3567 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3568 RegsToPass[i].second.getValueType()));
3570 // Add a register mask operand representing the call-preserved registers.
3571 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3572 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3573 assert(Mask && "Missing call preserved mask for calling convention");
3574 Ops.push_back(DAG.getRegisterMask(Mask));
3576 if (InFlag.getNode())
3577 Ops.push_back(InFlag);
3580 return DAG.getNode(MipsISD::TailCall, dl, MVT::Other, &Ops[0], Ops.size());
3582 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
3583 InFlag = Chain.getValue(1);
3585 // Create the CALLSEQ_END node.
3586 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
3587 DAG.getIntPtrConstant(0, true), InFlag);
3588 InFlag = Chain.getValue(1);
3590 // Handle result values, copying them out of physregs into vregs that we
3592 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3593 Ins, dl, DAG, InVals);
3596 /// LowerCallResult - Lower the result values of a call into the
3597 /// appropriate copies out of appropriate physical registers.
3599 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3600 CallingConv::ID CallConv, bool isVarArg,
3601 const SmallVectorImpl<ISD::InputArg> &Ins,
3602 DebugLoc dl, SelectionDAG &DAG,
3603 SmallVectorImpl<SDValue> &InVals) const {
3604 // Assign locations to each value returned by this call.
3605 SmallVector<CCValAssign, 16> RVLocs;
3606 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3607 getTargetMachine(), RVLocs, *DAG.getContext());
3609 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
3611 // Copy all of the result registers out of their specified physreg.
3612 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3613 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
3614 RVLocs[i].getValVT(), InFlag).getValue(1);
3615 InFlag = Chain.getValue(2);
3616 InVals.push_back(Chain.getValue(0));
3622 //===----------------------------------------------------------------------===//
3623 // Formal Arguments Calling Convention Implementation
3624 //===----------------------------------------------------------------------===//
3625 /// LowerFormalArguments - transform physical registers into virtual registers
3626 /// and generate load operations for arguments places on the stack.
3628 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
3629 CallingConv::ID CallConv,
3631 const SmallVectorImpl<ISD::InputArg> &Ins,
3632 DebugLoc dl, SelectionDAG &DAG,
3633 SmallVectorImpl<SDValue> &InVals)
3635 MachineFunction &MF = DAG.getMachineFunction();
3636 MachineFrameInfo *MFI = MF.getFrameInfo();
3637 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3639 MipsFI->setVarArgsFrameIndex(0);
3641 // Used with vargs to acumulate store chains.
3642 std::vector<SDValue> OutChains;
3644 // Assign locations to all of the incoming arguments.
3645 SmallVector<CCValAssign, 16> ArgLocs;
3646 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3647 getTargetMachine(), ArgLocs, *DAG.getContext());
3648 MipsCC MipsCCInfo(CallConv, IsO32, CCInfo);
3649 Function::const_arg_iterator FuncArg =
3650 DAG.getMachineFunction().getFunction()->arg_begin();
3651 bool UseSoftFloat = getTargetMachine().Options.UseSoftFloat;
3653 MipsCCInfo.analyzeFormalArguments(Ins, UseSoftFloat, FuncArg);
3654 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
3655 MipsCCInfo.hasByValArg());
3657 unsigned CurArgIdx = 0;
3658 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin();
3660 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3661 CCValAssign &VA = ArgLocs[i];
3662 std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx);
3663 CurArgIdx = Ins[i].OrigArgIndex;
3664 EVT ValVT = VA.getValVT();
3665 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3666 bool IsRegLoc = VA.isRegLoc();
3668 if (Flags.isByVal()) {
3669 assert(Flags.getByValSize() &&
3670 "ByVal args of size 0 should have been ignored by front-end.");
3671 assert(ByValArg != MipsCCInfo.byval_end());
3672 copyByValRegs(Chain, dl, OutChains, DAG, Flags, InVals, &*FuncArg,
3673 MipsCCInfo, *ByValArg);
3678 // Arguments stored on registers
3680 EVT RegVT = VA.getLocVT();
3681 unsigned ArgReg = VA.getLocReg();
3682 const TargetRegisterClass *RC;
3684 if (RegVT == MVT::i32)
3685 RC = Subtarget->inMips16Mode()? &Mips::CPU16RegsRegClass :
3686 &Mips::CPURegsRegClass;
3687 else if (RegVT == MVT::i64)
3688 RC = &Mips::CPU64RegsRegClass;
3689 else if (RegVT == MVT::f32)
3690 RC = &Mips::FGR32RegClass;
3691 else if (RegVT == MVT::f64)
3692 RC = HasMips64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
3694 llvm_unreachable("RegVT not supported by FormalArguments Lowering");
3696 // Transform the arguments stored on
3697 // physical registers into virtual ones
3698 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC);
3699 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3701 // If this is an 8 or 16-bit value, it has been passed promoted
3702 // to 32 bits. Insert an assert[sz]ext to capture this, then
3703 // truncate to the right size.
3704 if (VA.getLocInfo() != CCValAssign::Full) {
3705 unsigned Opcode = 0;
3706 if (VA.getLocInfo() == CCValAssign::SExt)
3707 Opcode = ISD::AssertSext;
3708 else if (VA.getLocInfo() == CCValAssign::ZExt)
3709 Opcode = ISD::AssertZext;
3711 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
3712 DAG.getValueType(ValVT));
3713 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, ValVT, ArgValue);
3716 // Handle floating point arguments passed in integer registers and
3717 // long double arguments passed in floating point registers.
3718 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3719 (RegVT == MVT::i64 && ValVT == MVT::f64) ||
3720 (RegVT == MVT::f64 && ValVT == MVT::i64))
3721 ArgValue = DAG.getNode(ISD::BITCAST, dl, ValVT, ArgValue);
3722 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) {
3723 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
3724 getNextIntArgReg(ArgReg), RC);
3725 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
3726 if (!Subtarget->isLittle())
3727 std::swap(ArgValue, ArgValue2);
3728 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64,
3729 ArgValue, ArgValue2);
3732 InVals.push_back(ArgValue);
3733 } else { // VA.isRegLoc()
3736 assert(VA.isMemLoc());
3738 // The stack pointer offset is relative to the caller stack frame.
3739 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
3740 VA.getLocMemOffset(), true);
3742 // Create load nodes to retrieve arguments from the stack
3743 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
3744 InVals.push_back(DAG.getLoad(ValVT, dl, Chain, FIN,
3745 MachinePointerInfo::getFixedStack(FI),
3746 false, false, false, 0));
3750 // The mips ABIs for returning structs by value requires that we copy
3751 // the sret argument into $v0 for the return. Save the argument into
3752 // a virtual register so that we can access it from the return points.
3753 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
3754 unsigned Reg = MipsFI->getSRetReturnReg();
3756 Reg = MF.getRegInfo().
3757 createVirtualRegister(getRegClassFor(IsN64 ? MVT::i64 : MVT::i32));
3758 MipsFI->setSRetReturnReg(Reg);
3760 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
3761 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
3765 writeVarArgRegs(OutChains, MipsCCInfo, Chain, dl, DAG);
3767 // All stores are grouped in one node to allow the matching between
3768 // the size of Ins and InVals. This only happens when on varg functions
3769 if (!OutChains.empty()) {
3770 OutChains.push_back(Chain);
3771 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3772 &OutChains[0], OutChains.size());
3778 //===----------------------------------------------------------------------===//
3779 // Return Value Calling Convention Implementation
3780 //===----------------------------------------------------------------------===//
3783 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3784 MachineFunction &MF, bool isVarArg,
3785 const SmallVectorImpl<ISD::OutputArg> &Outs,
3786 LLVMContext &Context) const {
3787 SmallVector<CCValAssign, 16> RVLocs;
3788 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
3790 return CCInfo.CheckReturn(Outs, RetCC_Mips);
3794 MipsTargetLowering::LowerReturn(SDValue Chain,
3795 CallingConv::ID CallConv, bool isVarArg,
3796 const SmallVectorImpl<ISD::OutputArg> &Outs,
3797 const SmallVectorImpl<SDValue> &OutVals,
3798 DebugLoc dl, SelectionDAG &DAG) const {
3800 // CCValAssign - represent the assignment of
3801 // the return value to a location
3802 SmallVector<CCValAssign, 16> RVLocs;
3804 // CCState - Info about the registers and stack slot.
3805 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3806 getTargetMachine(), RVLocs, *DAG.getContext());
3808 // Analize return values.
3809 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3812 SmallVector<SDValue, 4> RetOps(1, Chain);
3814 // Copy the result values into the output registers.
3815 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3816 CCValAssign &VA = RVLocs[i];
3817 assert(VA.isRegLoc() && "Can only return in registers!");
3819 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
3821 // Guarantee that all emitted copies are stuck together with flags.
3822 Flag = Chain.getValue(1);
3823 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3826 // The mips ABIs for returning structs by value requires that we copy
3827 // the sret argument into $v0 for the return. We saved the argument into
3828 // a virtual register in the entry block, so now we copy the value out
3830 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
3831 MachineFunction &MF = DAG.getMachineFunction();
3832 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3833 unsigned Reg = MipsFI->getSRetReturnReg();
3836 llvm_unreachable("sret virtual register not created in the entry block");
3837 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
3838 unsigned V0 = IsN64 ? Mips::V0_64 : Mips::V0;
3840 Chain = DAG.getCopyToReg(Chain, dl, V0, Val, Flag);
3841 Flag = Chain.getValue(1);
3842 RetOps.push_back(DAG.getRegister(V0, getPointerTy()));
3845 RetOps[0] = Chain; // Update chain.
3847 // Add the flag if we have it.
3849 RetOps.push_back(Flag);
3851 // Return on Mips is always a "jr $ra"
3852 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, &RetOps[0], RetOps.size());
3855 //===----------------------------------------------------------------------===//
3856 // Mips Inline Assembly Support
3857 //===----------------------------------------------------------------------===//
3859 /// getConstraintType - Given a constraint letter, return the type of
3860 /// constraint it is for this target.
3861 MipsTargetLowering::ConstraintType MipsTargetLowering::
3862 getConstraintType(const std::string &Constraint) const
3864 // Mips specific constrainy
3865 // GCC config/mips/constraints.md
3867 // 'd' : An address register. Equivalent to r
3868 // unless generating MIPS16 code.
3869 // 'y' : Equivalent to r; retained for
3870 // backwards compatibility.
3871 // 'c' : A register suitable for use in an indirect
3872 // jump. This will always be $25 for -mabicalls.
3873 // 'l' : The lo register. 1 word storage.
3874 // 'x' : The hilo register pair. Double word storage.
3875 if (Constraint.size() == 1) {
3876 switch (Constraint[0]) {
3884 return C_RegisterClass;
3889 return TargetLowering::getConstraintType(Constraint);
3892 /// Examine constraint type and operand type and determine a weight value.
3893 /// This object must already have been set up with the operand type
3894 /// and the current alternative constraint selected.
3895 TargetLowering::ConstraintWeight
3896 MipsTargetLowering::getSingleConstraintMatchWeight(
3897 AsmOperandInfo &info, const char *constraint) const {
3898 ConstraintWeight weight = CW_Invalid;
3899 Value *CallOperandVal = info.CallOperandVal;
3900 // If we don't have a value, we can't do a match,
3901 // but allow it at the lowest weight.
3902 if (CallOperandVal == NULL)
3904 Type *type = CallOperandVal->getType();
3905 // Look at the constraint type.
3906 switch (*constraint) {
3908 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3912 if (type->isIntegerTy())
3913 weight = CW_Register;
3916 if (type->isFloatTy())
3917 weight = CW_Register;
3919 case 'c': // $25 for indirect jumps
3920 case 'l': // lo register
3921 case 'x': // hilo register pair
3922 if (type->isIntegerTy())
3923 weight = CW_SpecificReg;
3925 case 'I': // signed 16 bit immediate
3926 case 'J': // integer zero
3927 case 'K': // unsigned 16 bit immediate
3928 case 'L': // signed 32 bit immediate where lower 16 bits are 0
3929 case 'N': // immediate in the range of -65535 to -1 (inclusive)
3930 case 'O': // signed 15 bit immediate (+- 16383)
3931 case 'P': // immediate in the range of 65535 to 1 (inclusive)
3932 if (isa<ConstantInt>(CallOperandVal))
3933 weight = CW_Constant;
3942 /// Given a register class constraint, like 'r', if this corresponds directly
3943 /// to an LLVM register class, return a register of 0 and the register class
3945 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
3946 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
3948 if (Constraint.size() == 1) {
3949 switch (Constraint[0]) {
3950 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
3951 case 'y': // Same as 'r'. Exists for compatibility.
3953 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
3954 if (Subtarget->inMips16Mode())
3955 return std::make_pair(0U, &Mips::CPU16RegsRegClass);
3956 return std::make_pair(0U, &Mips::CPURegsRegClass);
3958 if (VT == MVT::i64 && !HasMips64)
3959 return std::make_pair(0U, &Mips::CPURegsRegClass);
3960 if (VT == MVT::i64 && HasMips64)
3961 return std::make_pair(0U, &Mips::CPU64RegsRegClass);
3962 // This will generate an error message
3963 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
3966 return std::make_pair(0U, &Mips::FGR32RegClass);
3967 if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) {
3968 if (Subtarget->isFP64bit())
3969 return std::make_pair(0U, &Mips::FGR64RegClass);
3970 return std::make_pair(0U, &Mips::AFGR64RegClass);
3973 case 'c': // register suitable for indirect jump
3975 return std::make_pair((unsigned)Mips::T9, &Mips::CPURegsRegClass);
3976 assert(VT == MVT::i64 && "Unexpected type.");
3977 return std::make_pair((unsigned)Mips::T9_64, &Mips::CPU64RegsRegClass);
3978 case 'l': // register suitable for indirect jump
3980 return std::make_pair((unsigned)Mips::LO, &Mips::HILORegClass);
3981 return std::make_pair((unsigned)Mips::LO64, &Mips::HILO64RegClass);
3982 case 'x': // register suitable for indirect jump
3983 // Fixme: Not triggering the use of both hi and low
3984 // This will generate an error message
3985 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
3988 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3991 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3992 /// vector. If it is invalid, don't add anything to Ops.
3993 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3994 std::string &Constraint,
3995 std::vector<SDValue>&Ops,
3996 SelectionDAG &DAG) const {
3997 SDValue Result(0, 0);
3999 // Only support length 1 constraints for now.
4000 if (Constraint.length() > 1) return;
4002 char ConstraintLetter = Constraint[0];
4003 switch (ConstraintLetter) {
4004 default: break; // This will fall through to the generic implementation
4005 case 'I': // Signed 16 bit constant
4006 // If this fails, the parent routine will give an error
4007 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4008 EVT Type = Op.getValueType();
4009 int64_t Val = C->getSExtValue();
4010 if (isInt<16>(Val)) {
4011 Result = DAG.getTargetConstant(Val, Type);
4016 case 'J': // integer zero
4017 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4018 EVT Type = Op.getValueType();
4019 int64_t Val = C->getZExtValue();
4021 Result = DAG.getTargetConstant(0, Type);
4026 case 'K': // unsigned 16 bit immediate
4027 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4028 EVT Type = Op.getValueType();
4029 uint64_t Val = (uint64_t)C->getZExtValue();
4030 if (isUInt<16>(Val)) {
4031 Result = DAG.getTargetConstant(Val, Type);
4036 case 'L': // signed 32 bit immediate where lower 16 bits are 0
4037 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4038 EVT Type = Op.getValueType();
4039 int64_t Val = C->getSExtValue();
4040 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
4041 Result = DAG.getTargetConstant(Val, Type);
4046 case 'N': // immediate in the range of -65535 to -1 (inclusive)
4047 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4048 EVT Type = Op.getValueType();
4049 int64_t Val = C->getSExtValue();
4050 if ((Val >= -65535) && (Val <= -1)) {
4051 Result = DAG.getTargetConstant(Val, Type);
4056 case 'O': // signed 15 bit immediate
4057 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4058 EVT Type = Op.getValueType();
4059 int64_t Val = C->getSExtValue();
4060 if ((isInt<15>(Val))) {
4061 Result = DAG.getTargetConstant(Val, Type);
4066 case 'P': // immediate in the range of 1 to 65535 (inclusive)
4067 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4068 EVT Type = Op.getValueType();
4069 int64_t Val = C->getSExtValue();
4070 if ((Val <= 65535) && (Val >= 1)) {
4071 Result = DAG.getTargetConstant(Val, Type);
4078 if (Result.getNode()) {
4079 Ops.push_back(Result);
4083 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4087 MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM, Type *Ty) const {
4088 // No global is ever allowed as a base.
4093 case 0: // "r+i" or just "i", depending on HasBaseReg.
4096 if (!AM.HasBaseReg) // allow "r+i".
4098 return false; // disallow "r+r" or "r+r+i".
4107 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
4108 // The Mips target isn't yet aware of offsets.
4112 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
4114 bool IsMemset, bool ZeroMemset,
4116 MachineFunction &MF) const {
4117 if (Subtarget->hasMips64())
4123 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4124 if (VT != MVT::f32 && VT != MVT::f64)
4126 if (Imm.isNegZero())
4128 return Imm.isZero();
4131 unsigned MipsTargetLowering::getJumpTableEncoding() const {
4133 return MachineJumpTableInfo::EK_GPRel64BlockAddress;
4135 return TargetLowering::getJumpTableEncoding();
4138 MipsTargetLowering::MipsCC::MipsCC(CallingConv::ID CC, bool IsO32_,
4140 : CCInfo(Info), CallConv(CC), IsO32(IsO32_) {
4141 // Pre-allocate reserved argument area.
4142 CCInfo.AllocateStack(reservedArgArea(), 1);
4145 void MipsTargetLowering::MipsCC::
4146 analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Args,
4148 assert((CallConv != CallingConv::Fast || !IsVarArg) &&
4149 "CallingConv::Fast shouldn't be used for vararg functions.");
4151 unsigned NumOpnds = Args.size();
4152 llvm::CCAssignFn *FixedFn = fixedArgFn(), *VarFn = varArgFn();
4154 for (unsigned I = 0; I != NumOpnds; ++I) {
4155 MVT ArgVT = Args[I].VT;
4156 ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
4159 if (ArgFlags.isByVal()) {
4160 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags);
4164 if (IsVarArg && !Args[I].IsFixed)
4165 R = VarFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
4167 R = FixedFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
4171 dbgs() << "Call operand #" << I << " has unhandled type "
4172 << EVT(ArgVT).getEVTString();
4174 llvm_unreachable(0);
4179 void MipsTargetLowering::MipsCC::
4180 analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Args,
4181 bool IsSoftFloat, Function::const_arg_iterator FuncArg) {
4182 unsigned NumArgs = Args.size();
4183 llvm::CCAssignFn *FixedFn = fixedArgFn();
4184 unsigned CurArgIdx = 0;
4186 for (unsigned I = 0; I != NumArgs; ++I) {
4187 MVT ArgVT = Args[I].VT;
4188 ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
4189 std::advance(FuncArg, Args[I].OrigArgIndex - CurArgIdx);
4190 CurArgIdx = Args[I].OrigArgIndex;
4192 if (ArgFlags.isByVal()) {
4193 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags);
4197 MVT RegVT = getRegVT(ArgVT, FuncArg->getType(), 0, IsSoftFloat);
4199 if (!FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo))
4203 dbgs() << "Formal Arg #" << I << " has unhandled type "
4204 << EVT(ArgVT).getEVTString();
4206 llvm_unreachable(0);
4211 MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT,
4213 CCValAssign::LocInfo LocInfo,
4214 ISD::ArgFlagsTy ArgFlags) {
4215 assert(ArgFlags.getByValSize() && "Byval argument's size shouldn't be 0.");
4217 struct ByValArgInfo ByVal;
4218 unsigned RegSize = regSize();
4219 unsigned ByValSize = RoundUpToAlignment(ArgFlags.getByValSize(), RegSize);
4220 unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSize),
4223 if (useRegsForByval())
4224 allocateRegs(ByVal, ByValSize, Align);
4226 // Allocate space on caller's stack.
4227 ByVal.Address = CCInfo.AllocateStack(ByValSize - RegSize * ByVal.NumRegs,
4229 CCInfo.addLoc(CCValAssign::getMem(ValNo, ValVT, ByVal.Address, LocVT,
4231 ByValArgs.push_back(ByVal);
4234 unsigned MipsTargetLowering::MipsCC::numIntArgRegs() const {
4235 return IsO32 ? array_lengthof(O32IntRegs) : array_lengthof(Mips64IntRegs);
4238 unsigned MipsTargetLowering::MipsCC::reservedArgArea() const {
4239 return (IsO32 && (CallConv != CallingConv::Fast)) ? 16 : 0;
4242 const uint16_t *MipsTargetLowering::MipsCC::intArgRegs() const {
4243 return IsO32 ? O32IntRegs : Mips64IntRegs;
4246 llvm::CCAssignFn *MipsTargetLowering::MipsCC::fixedArgFn() const {
4247 if (CallConv == CallingConv::Fast)
4248 return CC_Mips_FastCC;
4250 return IsO32 ? CC_MipsO32 : CC_MipsN;
4253 llvm::CCAssignFn *MipsTargetLowering::MipsCC::varArgFn() const {
4254 return IsO32 ? CC_MipsO32 : CC_MipsN_VarArg;
4257 const uint16_t *MipsTargetLowering::MipsCC::shadowRegs() const {
4258 return IsO32 ? O32IntRegs : Mips64DPRegs;
4261 void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal,
4264 unsigned RegSize = regSize(), NumIntArgRegs = numIntArgRegs();
4265 const uint16_t *IntArgRegs = intArgRegs(), *ShadowRegs = shadowRegs();
4266 assert(!(ByValSize % RegSize) && !(Align % RegSize) &&
4267 "Byval argument's size and alignment should be a multiple of"
4270 ByVal.FirstIdx = CCInfo.getFirstUnallocated(IntArgRegs, NumIntArgRegs);
4272 // If Align > RegSize, the first arg register must be even.
4273 if ((Align > RegSize) && (ByVal.FirstIdx % 2)) {
4274 CCInfo.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]);
4278 // Mark the registers allocated.
4279 for (unsigned I = ByVal.FirstIdx; ByValSize && (I < NumIntArgRegs);
4280 ByValSize -= RegSize, ++I, ++ByVal.NumRegs)
4281 CCInfo.AllocateReg(IntArgRegs[I], ShadowRegs[I]);
4284 /// This function returns true if CallSym is a long double emulation routine.
4285 static bool isF128SoftLibCall(const char *CallSym) {
4286 const char *const LibCalls[] =
4287 {"__addtf3", "__divtf3", "__eqtf2", "__extenddftf2", "__extendsftf2",
4288 "__fixtfdi", "__fixtfsi", "__fixtfti", "__fixunstfdi", "__fixunstfsi",
4289 "__fixunstfti", "__floatditf", "__floatsitf", "__floattitf",
4290 "__floatunditf", "__floatunsitf", "__floatuntitf", "__getf2", "__gttf2",
4291 "__letf2", "__lttf2", "__multf3", "__netf2", "__powitf2", "__subtf3",
4292 "__trunctfdf2", "__trunctfsf2", "__unordtf2",
4293 "ceill", "copysignl", "cosl", "exp2l", "expl", "floorl", "fmal", "fmodl",
4294 "log10l", "log2l", "logl", "nearbyintl", "powl", "rintl", "sinl", "sqrtl",
4297 const char * const *End = LibCalls + array_lengthof(LibCalls);
4299 // Check that LibCalls is sorted alphabetically.
4303 for (const char * const *I = LibCalls; I < End - 1; ++I)
4304 assert(Comp(*I, *(I + 1)));
4307 return std::binary_search(LibCalls, End, CallSym, ltstr());
4311 MVT MipsTargetLowering::MipsCC::getRegVT(MVT VT, const Type *OrigTy,
4312 const SDNode *CallNode,
4313 bool IsSoftFloat) const {
4314 if (IsSoftFloat || IsO32)
4317 // Check if the original type was fp128.
4318 if (OrigTy->isFP128Ty()) {
4319 assert(VT == MVT::i64);
4323 const ExternalSymbolSDNode *ES =
4324 dyn_cast_or_null<const ExternalSymbolSDNode>(CallNode);
4326 // If the original type was i128 and the function being called is a long
4327 // double emulation routine, the argument must be passed in an f64 register.
4328 if (ES && OrigTy->isIntegerTy(128) && isF128SoftLibCall(ES->getSymbol())) {
4329 assert(VT == MVT::i64);
4336 void MipsTargetLowering::
4337 copyByValRegs(SDValue Chain, DebugLoc DL, std::vector<SDValue> &OutChains,
4338 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
4339 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg,
4340 const MipsCC &CC, const ByValArgInfo &ByVal) const {
4341 MachineFunction &MF = DAG.getMachineFunction();
4342 MachineFrameInfo *MFI = MF.getFrameInfo();
4343 unsigned RegAreaSize = ByVal.NumRegs * CC.regSize();
4344 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
4348 FrameObjOffset = (int)CC.reservedArgArea() -
4349 (int)((CC.numIntArgRegs() - ByVal.FirstIdx) * CC.regSize());
4351 FrameObjOffset = ByVal.Address;
4353 // Create frame object.
4354 EVT PtrTy = getPointerTy();
4355 int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true);
4356 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4357 InVals.push_back(FIN);
4362 // Copy arg registers.
4363 MVT RegTy = MVT::getIntegerVT(CC.regSize() * 8);
4364 const TargetRegisterClass *RC = getRegClassFor(RegTy);
4366 for (unsigned I = 0; I < ByVal.NumRegs; ++I) {
4367 unsigned ArgReg = CC.intArgRegs()[ByVal.FirstIdx + I];
4368 unsigned VReg = AddLiveIn(MF, ArgReg, RC);
4369 unsigned Offset = I * CC.regSize();
4370 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
4371 DAG.getConstant(Offset, PtrTy));
4372 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
4373 StorePtr, MachinePointerInfo(FuncArg, Offset),
4375 OutChains.push_back(Store);
4379 // Copy byVal arg to registers and stack.
4380 void MipsTargetLowering::
4381 passByValArg(SDValue Chain, DebugLoc DL,
4382 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
4383 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
4384 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
4385 const MipsCC &CC, const ByValArgInfo &ByVal,
4386 const ISD::ArgFlagsTy &Flags, bool isLittle) const {
4387 unsigned ByValSize = Flags.getByValSize();
4388 unsigned Offset = 0; // Offset in # of bytes from the beginning of struct.
4389 unsigned RegSize = CC.regSize();
4390 unsigned Alignment = std::min(Flags.getByValAlign(), RegSize);
4391 EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSize * 8);
4393 if (ByVal.NumRegs) {
4394 const uint16_t *ArgRegs = CC.intArgRegs();
4395 bool LeftoverBytes = (ByVal.NumRegs * RegSize > ByValSize);
4398 // Copy words to registers.
4399 for (; I < ByVal.NumRegs - LeftoverBytes; ++I, Offset += RegSize) {
4400 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4401 DAG.getConstant(Offset, PtrTy));
4402 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
4403 MachinePointerInfo(), false, false, false,
4405 MemOpChains.push_back(LoadVal.getValue(1));
4406 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I];
4407 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
4410 // Return if the struct has been fully copied.
4411 if (ByValSize == Offset)
4414 // Copy the remainder of the byval argument with sub-word loads and shifts.
4415 if (LeftoverBytes) {
4416 assert((ByValSize > Offset) && (ByValSize < Offset + RegSize) &&
4417 "Size of the remainder should be smaller than RegSize.");
4420 for (unsigned LoadSize = RegSize / 2, TotalSizeLoaded = 0;
4421 Offset < ByValSize; LoadSize /= 2) {
4422 unsigned RemSize = ByValSize - Offset;
4424 if (RemSize < LoadSize)
4428 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4429 DAG.getConstant(Offset, PtrTy));
4431 DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr,
4432 MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8),
4433 false, false, Alignment);
4434 MemOpChains.push_back(LoadVal.getValue(1));
4436 // Shift the loaded value.
4440 Shamt = TotalSizeLoaded;
4442 Shamt = (RegSize - (TotalSizeLoaded + LoadSize)) * 8;
4444 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
4445 DAG.getConstant(Shamt, MVT::i32));
4448 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
4453 TotalSizeLoaded += LoadSize;
4454 Alignment = std::min(Alignment, LoadSize);
4457 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I];
4458 RegsToPass.push_back(std::make_pair(ArgReg, Val));
4463 // Copy remainder of byval arg to it with memcpy.
4464 unsigned MemCpySize = ByValSize - Offset;
4465 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4466 DAG.getConstant(Offset, PtrTy));
4467 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
4468 DAG.getIntPtrConstant(ByVal.Address));
4469 Chain = DAG.getMemcpy(Chain, DL, Dst, Src,
4470 DAG.getConstant(MemCpySize, PtrTy), Alignment,
4471 /*isVolatile=*/false, /*AlwaysInline=*/false,
4472 MachinePointerInfo(0), MachinePointerInfo(0));
4473 MemOpChains.push_back(Chain);
4477 MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
4478 const MipsCC &CC, SDValue Chain,
4479 DebugLoc DL, SelectionDAG &DAG) const {
4480 unsigned NumRegs = CC.numIntArgRegs();
4481 const uint16_t *ArgRegs = CC.intArgRegs();
4482 const CCState &CCInfo = CC.getCCInfo();
4483 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs);
4484 unsigned RegSize = CC.regSize();
4485 MVT RegTy = MVT::getIntegerVT(RegSize * 8);
4486 const TargetRegisterClass *RC = getRegClassFor(RegTy);
4487 MachineFunction &MF = DAG.getMachineFunction();
4488 MachineFrameInfo *MFI = MF.getFrameInfo();
4489 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
4491 // Offset of the first variable argument from stack pointer.
4495 VaArgOffset = RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSize);
4498 (int)CC.reservedArgArea() - (int)(RegSize * (NumRegs - Idx));
4500 // Record the frame index of the first variable argument
4501 // which is a value necessary to VASTART.
4502 int FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true);
4503 MipsFI->setVarArgsFrameIndex(FI);
4505 // Copy the integer registers that have not been used for argument passing
4506 // to the argument register save area. For O32, the save area is allocated
4507 // in the caller's stack frame, while for N32/64, it is allocated in the
4508 // callee's stack frame.
4509 for (unsigned I = Idx; I < NumRegs; ++I, VaArgOffset += RegSize) {
4510 unsigned Reg = AddLiveIn(MF, ArgRegs[I], RC);
4511 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
4512 FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true);
4513 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
4514 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
4515 MachinePointerInfo(), false, false, 0);
4516 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(0);
4517 OutChains.push_back(Store);