1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
17 #include "MipsISelLowering.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsTargetMachine.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
39 const char *MipsTargetLowering::
40 getTargetNodeName(unsigned Opcode) const
44 case MipsISD::JmpLink : return "MipsISD::JmpLink";
45 case MipsISD::Hi : return "MipsISD::Hi";
46 case MipsISD::Lo : return "MipsISD::Lo";
47 case MipsISD::GPRel : return "MipsISD::GPRel";
48 case MipsISD::Ret : return "MipsISD::Ret";
49 case MipsISD::SelectCC : return "MipsISD::SelectCC";
50 case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC";
51 case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
52 case MipsISD::FPCmp : return "MipsISD::FPCmp";
53 default : return NULL;
58 MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
60 Subtarget = &TM.getSubtarget<MipsSubtarget>();
62 // Mips does not have i1 type, so use i32 for
63 // setcc operations results (slt, sgt, ...).
64 setSetCCResultContents(ZeroOrOneSetCCResult);
66 // JumpTable targets must use GOT when using PIC_
67 setUsesGlobalOffsetTable(true);
69 // Set up the register classes
70 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
72 // When dealing with single precision only, use libcalls
73 if (!Subtarget->isSingleFloat()) {
74 addRegisterClass(MVT::f32, Mips::AFGR32RegisterClass);
75 if (!Subtarget->isFP64bit())
76 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
78 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
80 // Load extented operations for i1 types must be promoted
81 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
82 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
83 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
85 // Mips Custom Operations
86 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
87 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
88 setOperationAction(ISD::RET, MVT::Other, Custom);
89 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
90 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
91 setOperationAction(ISD::SELECT, MVT::f32, Custom);
92 setOperationAction(ISD::SELECT, MVT::i32, Custom);
93 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
94 setOperationAction(ISD::SETCC, MVT::f32, Custom);
95 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
97 // Operations not directly supported by Mips.
98 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
99 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
100 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
101 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
102 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
103 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
104 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
105 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
106 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
107 setOperationAction(ISD::ROTL, MVT::i32, Expand);
108 setOperationAction(ISD::ROTR, MVT::i32, Expand);
109 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
110 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
111 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
112 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
114 // We don't have line number support yet.
115 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
116 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
117 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
118 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
120 // Use the default for now
121 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
122 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
123 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
125 if (Subtarget->isSingleFloat())
126 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
128 if (!Subtarget->hasSEInReg()) {
129 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
130 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
133 setStackPointerRegisterToSaveRestore(Mips::SP);
134 computeRegisterProperties();
138 MVT MipsTargetLowering::getSetCCResultType(const SDValue &) const {
143 SDValue MipsTargetLowering::
144 LowerOperation(SDValue Op, SelectionDAG &DAG)
146 switch (Op.getOpcode())
148 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
149 case ISD::CALL: return LowerCALL(Op, DAG);
150 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
151 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
152 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
153 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
154 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
155 case ISD::RET: return LowerRET(Op, DAG);
156 case ISD::SELECT: return LowerSELECT(Op, DAG);
157 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
158 case ISD::SETCC: return LowerSETCC(Op, DAG);
163 //===----------------------------------------------------------------------===//
164 // Lower helper functions
165 //===----------------------------------------------------------------------===//
167 // AddLiveIn - This helper function adds the specified physical register to the
168 // MachineFunction as a live in value. It also creates a corresponding
169 // virtual register for it.
171 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
173 assert(RC->contains(PReg) && "Not the correct regclass!");
174 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
175 MF.getRegInfo().addLiveIn(PReg, VReg);
179 // A address must be loaded from a small section if its size is less than the
180 // small section size threshold. Data in this section must be addressed using
182 bool MipsTargetLowering::IsInSmallSection(unsigned Size) {
183 return (Size > 0 && (Size <= Subtarget->getSSectionThreshold()));
186 // Discover if this global address can be placed into small data/bss section.
187 bool MipsTargetLowering::IsGlobalInSmallSection(GlobalValue *GV)
189 const TargetData *TD = getTargetData();
190 const GlobalVariable *GVA = dyn_cast<GlobalVariable>(GV);
195 const Type *Ty = GV->getType()->getElementType();
196 unsigned Size = TD->getABITypeSize(Ty);
198 // if this is a internal constant string, there is a special
199 // section for it, but not in small data/bss.
200 if (GVA->hasInitializer() && GV->hasInternalLinkage()) {
201 Constant *C = GVA->getInitializer();
202 const ConstantArray *CVA = dyn_cast<ConstantArray>(C);
203 if (CVA && CVA->isCString())
207 return IsInSmallSection(Size);
210 // Get fp branch code (not opcode) from condition code.
211 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
212 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
213 return Mips::BRANCH_T;
215 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
216 return Mips::BRANCH_F;
218 return Mips::BRANCH_INVALID;
221 static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) {
224 assert(0 && "Unknown branch code");
225 case Mips::BRANCH_T : return Mips::BC1T;
226 case Mips::BRANCH_F : return Mips::BC1F;
227 case Mips::BRANCH_TL : return Mips::BC1TL;
228 case Mips::BRANCH_FL : return Mips::BC1FL;
232 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
234 default: assert(0 && "Unknown fp condition code!");
236 case ISD::SETOEQ: return Mips::FCOND_EQ;
237 case ISD::SETUNE: return Mips::FCOND_OGL;
239 case ISD::SETOLT: return Mips::FCOND_OLT;
241 case ISD::SETOGT: return Mips::FCOND_OGT;
243 case ISD::SETOLE: return Mips::FCOND_OLE;
245 case ISD::SETOGE: return Mips::FCOND_OGE;
246 case ISD::SETULT: return Mips::FCOND_ULT;
247 case ISD::SETULE: return Mips::FCOND_ULE;
248 case ISD::SETUGT: return Mips::FCOND_UGT;
249 case ISD::SETUGE: return Mips::FCOND_UGE;
250 case ISD::SETUO: return Mips::FCOND_UN;
251 case ISD::SETO: return Mips::FCOND_OR;
253 case ISD::SETONE: return Mips::FCOND_NEQ;
254 case ISD::SETUEQ: return Mips::FCOND_UEQ;
259 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
260 MachineBasicBlock *BB)
262 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
263 bool isFPCmp = false;
265 switch (MI->getOpcode()) {
266 default: assert(false && "Unexpected instr type to insert");
267 case Mips::Select_FCC:
268 case Mips::Select_FCC_SO32:
269 case Mips::Select_FCC_AS32:
270 case Mips::Select_FCC_D32:
271 isFPCmp = true; // FALL THROUGH
272 case Mips::Select_CC:
273 case Mips::Select_CC_SO32:
274 case Mips::Select_CC_AS32:
275 case Mips::Select_CC_D32: {
276 // To "insert" a SELECT_CC instruction, we actually have to insert the
277 // diamond control-flow pattern. The incoming instruction knows the
278 // destination vreg to set, the condition code register to branch on, the
279 // true/false values to select between, and a branch opcode to use.
280 const BasicBlock *LLVM_BB = BB->getBasicBlock();
281 MachineFunction::iterator It = BB;
288 // bNE r1, r0, copy1MBB
289 // fallthrough --> copy0MBB
290 MachineBasicBlock *thisMBB = BB;
291 MachineFunction *F = BB->getParent();
292 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
293 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
295 // Emit the right instruction according to the type of the operands compared
297 // Find the condiction code present in the setcc operation.
298 Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm();
299 // Get the branch opcode from the branch code.
300 unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC));
301 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
303 BuildMI(BB, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
304 .addReg(Mips::ZERO).addMBB(sinkMBB);
306 F->insert(It, copy0MBB);
307 F->insert(It, sinkMBB);
308 // Update machine-CFG edges by first adding all successors of the current
309 // block to the new block which will contain the Phi node for the select.
310 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
311 e = BB->succ_end(); i != e; ++i)
312 sinkMBB->addSuccessor(*i);
313 // Next, remove all successors of the current block, and add the true
314 // and fallthrough blocks as its successors.
315 while(!BB->succ_empty())
316 BB->removeSuccessor(BB->succ_begin());
317 BB->addSuccessor(copy0MBB);
318 BB->addSuccessor(sinkMBB);
322 // # fallthrough to sinkMBB
325 // Update machine-CFG edges
326 BB->addSuccessor(sinkMBB);
329 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
332 BuildMI(BB, TII->get(Mips::PHI), MI->getOperand(0).getReg())
333 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
334 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
336 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
342 //===----------------------------------------------------------------------===//
343 // Misc Lower Operation implementation
344 //===----------------------------------------------------------------------===//
346 SDValue MipsTargetLowering::
347 LowerBRCOND(SDValue Op, SelectionDAG &DAG)
349 // The first operand is the chain, the second is the condition, the third is
350 // the block to branch to if the condition is true.
351 SDValue Chain = Op.getOperand(0);
352 SDValue Dest = Op.getOperand(2);
355 if (Op.getOperand(1).getOpcode() == ISD::AND) {
356 CondRes = Op.getOperand(1).getOperand(0);
357 if (CondRes.getOpcode() != MipsISD::FPCmp)
359 } else if (Op.getOperand(1).getOpcode() == MipsISD::FPCmp)
360 CondRes = Op.getOperand(1);
364 SDValue CCNode = CondRes.getOperand(2);
365 Mips::CondCode CC = (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getValue();
366 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
368 return DAG.getNode(MipsISD::FPBrcond, Op.getValueType(), Chain, BrCode,
372 SDValue MipsTargetLowering::
373 LowerSETCC(SDValue Op, SelectionDAG &DAG)
375 // The operands to this are the left and right operands to compare (ops #0,
376 // and #1) and the condition code to compare them with (op #2) as a
378 SDValue LHS = Op.getOperand(0);
379 SDValue RHS = Op.getOperand(1);
381 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
383 return DAG.getNode(MipsISD::FPCmp, Op.getValueType(), LHS, RHS,
384 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
387 SDValue MipsTargetLowering::
388 LowerSELECT(SDValue Op, SelectionDAG &DAG)
390 SDValue Cond = Op.getOperand(0);
391 SDValue True = Op.getOperand(1);
392 SDValue False = Op.getOperand(2);
394 // this can be a fp select but with a setcc comming from a
396 if (Cond.getOpcode() == ISD::SETCC)
397 if (Cond.getOperand(0).getValueType().isInteger())
398 return DAG.getNode(MipsISD::SelectCC, True.getValueType(),
401 // Otherwise we're dealing with floating point compare.
403 if (Cond.getOpcode() == ISD::AND)
404 CondRes = Cond.getOperand(0);
405 else if (Cond.getOpcode() == MipsISD::FPCmp)
408 assert(0 && "Incoming condition flag unknown");
410 SDValue CCNode = CondRes.getOperand(2);
411 return DAG.getNode(MipsISD::FPSelectCC, True.getValueType(),
412 CondRes, True, False, CCNode);
415 SDValue MipsTargetLowering::
416 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG)
418 SDValue LHS = Op.getOperand(0);
419 SDValue RHS = Op.getOperand(1);
420 SDValue True = Op.getOperand(2);
421 SDValue False = Op.getOperand(3);
422 SDValue CC = Op.getOperand(4);
424 SDValue SetCCRes = DAG.getNode(ISD::SETCC, LHS.getValueType(), LHS, RHS, CC);
425 return DAG.getNode(MipsISD::SelectCC, True.getValueType(),
426 SetCCRes, True, False);
429 SDValue MipsTargetLowering::
430 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
432 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
433 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
435 if (!Subtarget->hasABICall()) {
436 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
437 SDValue Ops[] = { GA };
438 // %gp_rel relocation
439 if (!isa<Function>(GV) && IsGlobalInSmallSection(GV)) {
440 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, VTs, 1, Ops, 1);
441 SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
442 return DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
444 // %hi/%lo relocation
445 SDValue HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
446 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
447 return DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
449 } else { // Abicall relocations, TODO: make this cleaner.
450 SDValue ResNode = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0);
451 // On functions and global targets not internal linked only
452 // a load from got/GP is necessary for PIC to work.
453 if (!GV->hasInternalLinkage() || isa<Function>(GV))
455 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
456 return DAG.getNode(ISD::ADD, MVT::i32, ResNode, Lo);
459 assert(0 && "Dont know how to handle GlobalAddress");
463 SDValue MipsTargetLowering::
464 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
466 assert(0 && "TLS not implemented for MIPS.");
467 return SDValue(); // Not reached
470 SDValue MipsTargetLowering::
471 LowerJumpTable(SDValue Op, SelectionDAG &DAG)
476 MVT PtrVT = Op.getValueType();
477 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
478 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
480 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
481 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
482 SDValue Ops[] = { JTI };
483 HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
484 } else // Emit Load from Global Pointer
485 HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), JTI, NULL, 0);
487 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, JTI);
488 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
493 SDValue MipsTargetLowering::
494 LowerConstantPool(SDValue Op, SelectionDAG &DAG)
497 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
498 Constant *C = N->getConstVal();
499 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
502 // FIXME: we should reference the constant pool using small data sections,
503 // but the asm printer currently doens't support this feature without
504 // hacking it. This feature should come soon so we can uncomment the
506 //if (!Subtarget->hasABICall() &&
507 // IsInSmallSection(getTargetData()->getABITypeSize(C->getType()))) {
508 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
509 // SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
510 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
511 //} else { // %hi/%lo relocation
512 SDValue HiPart = DAG.getNode(MipsISD::Hi, MVT::i32, CP);
513 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, CP);
514 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
520 //===----------------------------------------------------------------------===//
521 // Calling Convention Implementation
523 // The lower operations present on calling convention works on this order:
524 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
525 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
526 // LowerRET (virt regs --> phys regs)
527 // LowerCALL (phys regs --> virt regs)
529 //===----------------------------------------------------------------------===//
531 #include "MipsGenCallingConv.inc"
533 //===----------------------------------------------------------------------===//
534 // CALL Calling Convention Implementation
535 //===----------------------------------------------------------------------===//
537 /// Mips custom CALL implementation
538 SDValue MipsTargetLowering::
539 LowerCALL(SDValue Op, SelectionDAG &DAG)
541 unsigned CallingConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
543 // By now, only CallingConv::C implemented
544 switch (CallingConv) {
546 assert(0 && "Unsupported calling convention");
547 case CallingConv::Fast:
549 return LowerCCCCallTo(Op, DAG, CallingConv);
553 /// LowerCCCCallTo - functions arguments are copied from virtual
554 /// regs to (physical regs)/(stack frame), CALLSEQ_START and
555 /// CALLSEQ_END are emitted.
556 /// TODO: isVarArg, isTailCall.
557 SDValue MipsTargetLowering::
558 LowerCCCCallTo(SDValue Op, SelectionDAG &DAG, unsigned CC)
560 MachineFunction &MF = DAG.getMachineFunction();
562 SDValue Chain = Op.getOperand(0);
563 SDValue Callee = Op.getOperand(4);
564 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
566 MachineFrameInfo *MFI = MF.getFrameInfo();
568 // Analyze operands of the call, assigning locations to each operand.
569 SmallVector<CCValAssign, 16> ArgLocs;
570 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
572 // To meet O32 ABI, Mips must always allocate 16 bytes on
573 // the stack (even if less than 4 are used as arguments)
574 if (Subtarget->isABI_O32()) {
575 int VTsize = MVT(MVT::i32).getSizeInBits()/8;
576 MFI->CreateFixedObject(VTsize, (VTsize*3));
579 CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips);
581 // Get a count of how many bytes are to be pushed on the stack.
582 unsigned NumBytes = CCInfo.getNextStackOffset();
583 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
586 // With EABI is it possible to have 16 args on registers.
587 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
588 SmallVector<SDValue, 8> MemOpChains;
590 // First/LastArgStackLoc contains the first/last
591 // "at stack" argument location.
592 int LastArgStackLoc = 0;
593 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
595 // Walk the register/memloc assignments, inserting copies/loads.
596 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
597 CCValAssign &VA = ArgLocs[i];
599 // Arguments start after the 5 first operands of ISD::CALL
600 SDValue Arg = Op.getOperand(5+2*VA.getValNo());
602 // Promote the value if needed.
603 switch (VA.getLocInfo()) {
604 default: assert(0 && "Unknown loc info!");
605 case CCValAssign::Full: break;
606 case CCValAssign::SExt:
607 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
609 case CCValAssign::ZExt:
610 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
612 case CCValAssign::AExt:
613 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
617 // Arguments that can be passed on register must be kept at
620 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
624 // Register cant get to this point...
625 assert(VA.isMemLoc());
627 // Create the frame index object for this incoming parameter
628 // This guarantees that when allocating Local Area the firsts
629 // 16 bytes which are alwayes reserved won't be overwritten
630 // if O32 ABI is used. For EABI the first address is zero.
631 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
632 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
635 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
637 // emit ISD::STORE whichs stores the
638 // parameter value to a stack Location
639 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
642 // Transform all store nodes into one single node because all store
643 // nodes are independent of each other.
644 if (!MemOpChains.empty())
645 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
646 &MemOpChains[0], MemOpChains.size());
648 // Build a sequence of copy-to-reg nodes chained together with token
649 // chain and flag operands which copy the outgoing args into registers.
650 // The InFlag in necessary since all emited instructions must be
653 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
654 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first,
655 RegsToPass[i].second, InFlag);
656 InFlag = Chain.getValue(1);
659 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
660 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
661 // node so that legalize doesn't hack it.
662 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
663 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
664 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
665 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
668 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
669 // = Chain, Callee, Reg#1, Reg#2, ...
671 // Returns a chain & a flag for retval copy to use.
672 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
673 SmallVector<SDValue, 8> Ops;
674 Ops.push_back(Chain);
675 Ops.push_back(Callee);
677 // Add argument registers to the end of the list so that they are
678 // known live into the call.
679 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
680 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
681 RegsToPass[i].second.getValueType()));
684 Ops.push_back(InFlag);
686 Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size());
687 InFlag = Chain.getValue(1);
689 // Create the CALLSEQ_END node.
690 Chain = DAG.getCALLSEQ_END(Chain,
691 DAG.getConstant(NumBytes, getPointerTy()),
692 DAG.getConstant(0, getPointerTy()),
694 InFlag = Chain.getValue(1);
696 // Create a stack location to hold GP when PIC is used. This stack
697 // location is used on function prologue to save GP and also after all
698 // emited CALL's to restore GP.
699 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
700 // Function can have an arbitrary number of calls, so
701 // hold the LastArgStackLoc with the biggest offset.
703 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
704 if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
705 LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
706 // Create the frame index only once. SPOffset here can be anything
707 // (this will be fixed on processFunctionBeforeFrameFinalized)
708 if (MipsFI->getGPStackOffset() == -1) {
709 FI = MFI->CreateFixedObject(4, 0);
712 MipsFI->setGPStackOffset(LastArgStackLoc);
716 FI = MipsFI->getGPFI();
717 SDValue FIN = DAG.getFrameIndex(FI,getPointerTy());
718 SDValue GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0);
719 Chain = GPLoad.getValue(1);
720 Chain = DAG.getCopyToReg(Chain, DAG.getRegister(Mips::GP, MVT::i32),
721 GPLoad, SDValue(0,0));
722 InFlag = Chain.getValue(1);
725 // Handle result values, copying them out of physregs into vregs that we
727 return SDValue(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
730 /// LowerCallResult - Lower the result values of an ISD::CALL into the
731 /// appropriate copies out of appropriate physical registers. This assumes that
732 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
733 /// being lowered. Returns a SDNode with the same number of values as the
735 SDNode *MipsTargetLowering::
736 LowerCallResult(SDValue Chain, SDValue InFlag, SDNode *TheCall,
737 unsigned CallingConv, SelectionDAG &DAG) {
739 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
741 // Assign locations to each value returned by this call.
742 SmallVector<CCValAssign, 16> RVLocs;
743 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
745 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
746 SmallVector<SDValue, 8> ResultVals;
748 // Copy all of the result registers out of their specified physreg.
749 for (unsigned i = 0; i != RVLocs.size(); ++i) {
750 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
751 RVLocs[i].getValVT(), InFlag).getValue(1);
752 InFlag = Chain.getValue(2);
753 ResultVals.push_back(Chain.getValue(0));
756 ResultVals.push_back(Chain);
758 // Merge everything together with a MERGE_VALUES node.
759 return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0],
760 ResultVals.size()).Val;
763 //===----------------------------------------------------------------------===//
764 // FORMAL_ARGUMENTS Calling Convention Implementation
765 //===----------------------------------------------------------------------===//
767 /// Mips custom FORMAL_ARGUMENTS implementation
768 SDValue MipsTargetLowering::
769 LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG)
771 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
775 assert(0 && "Unsupported calling convention");
777 return LowerCCCArguments(Op, DAG);
781 /// LowerCCCArguments - transform physical registers into
782 /// virtual registers and generate load operations for
783 /// arguments places on the stack.
785 SDValue MipsTargetLowering::
786 LowerCCCArguments(SDValue Op, SelectionDAG &DAG)
788 SDValue Root = Op.getOperand(0);
789 MachineFunction &MF = DAG.getMachineFunction();
790 MachineFrameInfo *MFI = MF.getFrameInfo();
791 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
793 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
794 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
796 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
798 // GP must be live into PIC and non-PIC call target.
799 AddLiveIn(MF, Mips::GP, Mips::CPURegsRegisterClass);
801 // Assign locations to all of the incoming arguments.
802 SmallVector<CCValAssign, 16> ArgLocs;
803 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
805 CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips);
806 SmallVector<SDValue, 16> ArgValues;
809 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
811 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
813 CCValAssign &VA = ArgLocs[i];
815 // Arguments stored on registers
817 MVT RegVT = VA.getLocVT();
818 TargetRegisterClass *RC = 0;
820 if (RegVT == MVT::i32)
821 RC = Mips::CPURegsRegisterClass;
822 else if (RegVT == MVT::f32) {
823 if (Subtarget->isSingleFloat())
824 RC = Mips::FGR32RegisterClass;
826 RC = Mips::AFGR32RegisterClass;
827 } else if (RegVT == MVT::f64) {
828 if (!Subtarget->isSingleFloat())
829 RC = Mips::AFGR64RegisterClass;
831 assert(0 && "RegVT not supported by FORMAL_ARGUMENTS Lowering");
833 // Transform the arguments stored on
834 // physical registers into virtual ones
835 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
836 SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
838 // If this is an 8 or 16-bit value, it is really passed promoted
839 // to 32 bits. Insert an assert[sz]ext to capture this, then
840 // truncate to the right size.
841 if (VA.getLocInfo() == CCValAssign::SExt)
842 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
843 DAG.getValueType(VA.getValVT()));
844 else if (VA.getLocInfo() == CCValAssign::ZExt)
845 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
846 DAG.getValueType(VA.getValVT()));
848 if (VA.getLocInfo() != CCValAssign::Full)
849 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
851 ArgValues.push_back(ArgValue);
853 // To meet ABI, when VARARGS are passed on registers, the registers
854 // must have their values written to the caller stack frame.
855 if ((isVarArg) && (Subtarget->isABI_O32())) {
856 if (StackPtr.Val == 0)
857 StackPtr = DAG.getRegister(StackReg, getPointerTy());
859 // The stack pointer offset is relative to the caller stack frame.
860 // Since the real stack size is unknown here, a negative SPOffset
861 // is used so there's a way to adjust these offsets when the stack
862 // size get known (on EliminateFrameIndex). A dummy SPOffset is
863 // used instead of a direct negative address (which is recorded to
864 // be used on emitPrologue) to avoid mis-calc of the first stack
865 // offset on PEI::calculateFrameObjectOffsets.
866 // Arguments are always 32-bit.
867 int FI = MFI->CreateFixedObject(4, 0);
868 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
869 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
871 // emit ISD::STORE whichs stores the
872 // parameter value to a stack Location
873 ArgValues.push_back(DAG.getStore(Root, ArgValue, PtrOff, NULL, 0));
876 } else { // VA.isRegLoc()
879 assert(VA.isMemLoc());
881 // The stack pointer offset is relative to the caller stack frame.
882 // Since the real stack size is unknown here, a negative SPOffset
883 // is used so there's a way to adjust these offsets when the stack
884 // size get known (on EliminateFrameIndex). A dummy SPOffset is
885 // used instead of a direct negative address (which is recorded to
886 // be used on emitPrologue) to avoid mis-calc of the first stack
887 // offset on PEI::calculateFrameObjectOffsets.
888 // Arguments are always 32-bit.
889 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
890 int FI = MFI->CreateFixedObject(ArgSize, 0);
891 MipsFI->recordLoadArgsFI(FI, -(ArgSize+
892 (FirstStackArgLoc + VA.getLocMemOffset())));
894 // Create load nodes to retrieve arguments from the stack
895 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
896 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
900 // The mips ABIs for returning structs by value requires that we copy
901 // the sret argument into $v0 for the return. Save the argument into
902 // a virtual register so that we can access it from the return points.
903 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
904 unsigned Reg = MipsFI->getSRetReturnReg();
906 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
907 MipsFI->setSRetReturnReg(Reg);
909 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
910 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root);
913 ArgValues.push_back(Root);
915 // Return the new list of results.
916 return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
917 ArgValues.size()).getValue(Op.ResNo);
920 //===----------------------------------------------------------------------===//
921 // Return Value Calling Convention Implementation
922 //===----------------------------------------------------------------------===//
924 SDValue MipsTargetLowering::
925 LowerRET(SDValue Op, SelectionDAG &DAG)
927 // CCValAssign - represent the assignment of
928 // the return value to a location
929 SmallVector<CCValAssign, 16> RVLocs;
930 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
931 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
933 // CCState - Info about the registers and stack slot.
934 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
936 // Analize return values of ISD::RET
937 CCInfo.AnalyzeReturn(Op.Val, RetCC_Mips);
939 // If this is the first return lowered for this function, add
940 // the regs to the liveout set for the function.
941 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
942 for (unsigned i = 0; i != RVLocs.size(); ++i)
943 if (RVLocs[i].isRegLoc())
944 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
947 // The chain is always operand #0
948 SDValue Chain = Op.getOperand(0);
951 // Copy the result values into the output registers.
952 for (unsigned i = 0; i != RVLocs.size(); ++i) {
953 CCValAssign &VA = RVLocs[i];
954 assert(VA.isRegLoc() && "Can only return in registers!");
956 // ISD::RET => ret chain, (regnum1,val1), ...
957 // So i*2+1 index only the regnums
958 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
960 // guarantee that all emitted copies are
961 // stuck together, avoiding something bad
962 Flag = Chain.getValue(1);
965 // The mips ABIs for returning structs by value requires that we copy
966 // the sret argument into $v0 for the return. We saved the argument into
967 // a virtual register in the entry block, so now we copy the value out
969 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
970 MachineFunction &MF = DAG.getMachineFunction();
971 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
972 unsigned Reg = MipsFI->getSRetReturnReg();
975 assert(0 && "sret virtual register not created in the entry block");
976 SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
978 Chain = DAG.getCopyToReg(Chain, Mips::V0, Val, Flag);
979 Flag = Chain.getValue(1);
982 // Return on Mips is always a "jr $ra"
984 return DAG.getNode(MipsISD::Ret, MVT::Other,
985 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
987 return DAG.getNode(MipsISD::Ret, MVT::Other,
988 Chain, DAG.getRegister(Mips::RA, MVT::i32));
991 //===----------------------------------------------------------------------===//
992 // Mips Inline Assembly Support
993 //===----------------------------------------------------------------------===//
995 /// getConstraintType - Given a constraint letter, return the type of
996 /// constraint it is for this target.
997 MipsTargetLowering::ConstraintType MipsTargetLowering::
998 getConstraintType(const std::string &Constraint) const
1000 // Mips specific constrainy
1001 // GCC config/mips/constraints.md
1003 // 'd' : An address register. Equivalent to r
1004 // unless generating MIPS16 code.
1005 // 'y' : Equivalent to r; retained for
1006 // backwards compatibility.
1007 // 'f' : Floating Point registers.
1008 if (Constraint.size() == 1) {
1009 switch (Constraint[0]) {
1014 return C_RegisterClass;
1018 return TargetLowering::getConstraintType(Constraint);
1021 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1022 /// return a list of registers that can be used to satisfy the constraint.
1023 /// This should only be used for C_RegisterClass constraints.
1024 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
1025 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
1027 if (Constraint.size() == 1) {
1028 switch (Constraint[0]) {
1030 return std::make_pair(0U, Mips::CPURegsRegisterClass);
1032 if (VT == MVT::f32) {
1033 if (Subtarget->isSingleFloat())
1034 return std::make_pair(0U, Mips::FGR32RegisterClass);
1036 return std::make_pair(0U, Mips::AFGR32RegisterClass);
1039 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1040 return std::make_pair(0U, Mips::AFGR64RegisterClass);
1043 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1046 /// Given a register class constraint, like 'r', if this corresponds directly
1047 /// to an LLVM register class, return a register of 0 and the register class
1049 std::vector<unsigned> MipsTargetLowering::
1050 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1053 if (Constraint.size() != 1)
1054 return std::vector<unsigned>();
1056 switch (Constraint[0]) {
1059 // GCC Mips Constraint Letters
1062 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
1063 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
1064 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
1068 if (VT == MVT::f32) {
1069 if (Subtarget->isSingleFloat())
1070 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
1071 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
1072 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
1073 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
1074 Mips::F30, Mips::F31, 0);
1076 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
1077 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
1078 Mips::F28, Mips::F30, 0);
1082 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1083 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
1084 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
1085 Mips::D14, Mips::D15, 0);
1087 return std::vector<unsigned>();