1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
16 #include "MipsISelLowering.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsTargetMachine.h"
19 #include "MipsTargetObjectFile.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
37 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
39 case MipsISD::JmpLink : return "MipsISD::JmpLink";
40 case MipsISD::Hi : return "MipsISD::Hi";
41 case MipsISD::Lo : return "MipsISD::Lo";
42 case MipsISD::GPRel : return "MipsISD::GPRel";
43 case MipsISD::Ret : return "MipsISD::Ret";
44 case MipsISD::SelectCC : return "MipsISD::SelectCC";
45 case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC";
46 case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
47 case MipsISD::FPCmp : return "MipsISD::FPCmp";
48 case MipsISD::FPRound : return "MipsISD::FPRound";
49 case MipsISD::MAdd : return "MipsISD::MAdd";
50 case MipsISD::MAddu : return "MipsISD::MAddu";
51 case MipsISD::MSub : return "MipsISD::MSub";
52 case MipsISD::MSubu : return "MipsISD::MSubu";
53 case MipsISD::DivRem : return "MipsISD::DivRem";
54 case MipsISD::DivRemU : return "MipsISD::DivRemU";
55 default : return NULL;
60 MipsTargetLowering(MipsTargetMachine &TM)
61 : TargetLowering(TM, new MipsTargetObjectFile()) {
62 Subtarget = &TM.getSubtarget<MipsSubtarget>();
64 // Mips does not have i1 type, so use i32 for
65 // setcc operations results (slt, sgt, ...).
66 setBooleanContents(ZeroOrOneBooleanContent);
68 // Set up the register classes
69 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
70 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
72 // When dealing with single precision only, use libcalls
73 if (!Subtarget->isSingleFloat())
74 if (!Subtarget->isFP64bit())
75 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
77 // Load extented operations for i1 types must be promoted
78 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
79 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
80 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
82 // MIPS doesn't have extending float->double load/store
83 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
84 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
86 // Used by legalize types to correctly generate the setcc result.
87 // Without this, every float setcc comes with a AND/OR with the result,
88 // we don't want this, since the fpcmp result goes to a flag register,
89 // which is used implicitly by brcond and select operations.
90 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
92 // Mips Custom Operations
93 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
94 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
95 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
96 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
97 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
98 setOperationAction(ISD::SELECT, MVT::f32, Custom);
99 setOperationAction(ISD::SELECT, MVT::f64, Custom);
100 setOperationAction(ISD::SELECT, MVT::i32, Custom);
101 setOperationAction(ISD::SETCC, MVT::f32, Custom);
102 setOperationAction(ISD::SETCC, MVT::f64, Custom);
103 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
104 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
105 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
106 setOperationAction(ISD::VASTART, MVT::Other, Custom);
109 // We custom lower AND/OR to handle the case where the DAG contain 'ands/ors'
110 // with operands comming from setcc fp comparions. This is necessary since
111 // the result from these setcc are in a flag registers (FCR31).
112 setOperationAction(ISD::AND, MVT::i32, Custom);
113 setOperationAction(ISD::OR, MVT::i32, Custom);
115 setOperationAction(ISD::SDIV, MVT::i32, Expand);
116 setOperationAction(ISD::SREM, MVT::i32, Expand);
117 setOperationAction(ISD::UDIV, MVT::i32, Expand);
118 setOperationAction(ISD::UREM, MVT::i32, Expand);
120 // Operations not directly supported by Mips.
121 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
122 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
123 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
124 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
125 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
126 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
127 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
128 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
129 setOperationAction(ISD::ROTL, MVT::i32, Expand);
131 if (!Subtarget->isMips32r2())
132 setOperationAction(ISD::ROTR, MVT::i32, Expand);
134 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
135 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
136 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
137 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
138 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
139 setOperationAction(ISD::FSIN, MVT::f32, Expand);
140 setOperationAction(ISD::FSIN, MVT::f64, Expand);
141 setOperationAction(ISD::FCOS, MVT::f32, Expand);
142 setOperationAction(ISD::FCOS, MVT::f64, Expand);
143 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
144 setOperationAction(ISD::FPOW, MVT::f32, Expand);
145 setOperationAction(ISD::FLOG, MVT::f32, Expand);
146 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
147 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
148 setOperationAction(ISD::FEXP, MVT::f32, Expand);
150 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
152 // Use the default for now
153 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
154 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
155 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
157 if (Subtarget->isSingleFloat())
158 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
160 if (!Subtarget->hasSEInReg()) {
161 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
162 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
165 if (!Subtarget->hasBitCount())
166 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
168 if (!Subtarget->hasSwap())
169 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
171 setTargetDAGCombine(ISD::ADDE);
172 setTargetDAGCombine(ISD::SUBE);
173 setTargetDAGCombine(ISD::SDIVREM);
174 setTargetDAGCombine(ISD::UDIVREM);
176 setStackPointerRegisterToSaveRestore(Mips::SP);
177 computeRegisterProperties();
180 MVT::SimpleValueType MipsTargetLowering::getSetCCResultType(EVT VT) const {
184 /// getFunctionAlignment - Return the Log2 alignment of this function.
185 unsigned MipsTargetLowering::getFunctionAlignment(const Function *) const {
190 // Transforms a subgraph in CurDAG if the following pattern is found:
191 // (addc multLo, Lo0), (adde multHi, Hi0),
193 // multHi/Lo: product of multiplication
194 // Lo0: initial value of Lo register
195 // Hi0: initial value of Hi register
196 // Return true if mattern matching was successful.
197 static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) {
198 // ADDENode's second operand must be a flag output of an ADDC node in order
199 // for the matching to be successful.
200 SDNode* ADDCNode = ADDENode->getOperand(2).getNode();
202 if (ADDCNode->getOpcode() != ISD::ADDC)
205 SDValue MultHi = ADDENode->getOperand(0);
206 SDValue MultLo = ADDCNode->getOperand(0);
207 SDNode* MultNode = MultHi.getNode();
208 unsigned MultOpc = MultHi.getOpcode();
210 // MultHi and MultLo must be generated by the same node,
211 if (MultLo.getNode() != MultNode)
214 // and it must be a multiplication.
215 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
218 // MultLo amd MultHi must be the first and second output of MultNode
220 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
223 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
224 // of the values of MultNode, in which case MultNode will be removed in later
226 // If there exist users other than ADDENode or ADDCNode, this function returns
227 // here, which will result in MultNode being mapped to a single MULT
228 // instruction node rather than a pair of MULT and MADD instructions being
230 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
233 SDValue Chain = CurDAG->getEntryNode();
234 DebugLoc dl = ADDENode->getDebugLoc();
236 // create MipsMAdd(u) node
237 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
239 SDValue MAdd = CurDAG->getNode(MultOpc, dl,
241 MultNode->getOperand(0),// Factor 0
242 MultNode->getOperand(1),// Factor 1
243 ADDCNode->getOperand(1),// Lo0
244 ADDENode->getOperand(1));// Hi0
246 // create CopyFromReg nodes
247 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
249 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
251 CopyFromLo.getValue(2));
253 // replace uses of adde and addc here
254 if (!SDValue(ADDCNode, 0).use_empty())
255 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo);
257 if (!SDValue(ADDENode, 0).use_empty())
258 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi);
264 // Transforms a subgraph in CurDAG if the following pattern is found:
265 // (addc Lo0, multLo), (sube Hi0, multHi),
267 // multHi/Lo: product of multiplication
268 // Lo0: initial value of Lo register
269 // Hi0: initial value of Hi register
270 // Return true if mattern matching was successful.
271 static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) {
272 // SUBENode's second operand must be a flag output of an SUBC node in order
273 // for the matching to be successful.
274 SDNode* SUBCNode = SUBENode->getOperand(2).getNode();
276 if (SUBCNode->getOpcode() != ISD::SUBC)
279 SDValue MultHi = SUBENode->getOperand(1);
280 SDValue MultLo = SUBCNode->getOperand(1);
281 SDNode* MultNode = MultHi.getNode();
282 unsigned MultOpc = MultHi.getOpcode();
284 // MultHi and MultLo must be generated by the same node,
285 if (MultLo.getNode() != MultNode)
288 // and it must be a multiplication.
289 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
292 // MultLo amd MultHi must be the first and second output of MultNode
294 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
297 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
298 // of the values of MultNode, in which case MultNode will be removed in later
300 // If there exist users other than SUBENode or SUBCNode, this function returns
301 // here, which will result in MultNode being mapped to a single MULT
302 // instruction node rather than a pair of MULT and MSUB instructions being
304 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
307 SDValue Chain = CurDAG->getEntryNode();
308 DebugLoc dl = SUBENode->getDebugLoc();
310 // create MipsSub(u) node
311 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
313 SDValue MSub = CurDAG->getNode(MultOpc, dl,
315 MultNode->getOperand(0),// Factor 0
316 MultNode->getOperand(1),// Factor 1
317 SUBCNode->getOperand(0),// Lo0
318 SUBENode->getOperand(0));// Hi0
320 // create CopyFromReg nodes
321 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
323 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
325 CopyFromLo.getValue(2));
327 // replace uses of sube and subc here
328 if (!SDValue(SUBCNode, 0).use_empty())
329 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo);
331 if (!SDValue(SUBENode, 0).use_empty())
332 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi);
337 static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG,
338 TargetLowering::DAGCombinerInfo &DCI,
339 const MipsSubtarget* Subtarget) {
340 if (DCI.isBeforeLegalize())
343 if (Subtarget->isMips32() && SelectMadd(N, &DAG))
344 return SDValue(N, 0);
349 static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG,
350 TargetLowering::DAGCombinerInfo &DCI,
351 const MipsSubtarget* Subtarget) {
352 if (DCI.isBeforeLegalize())
355 if (Subtarget->isMips32() && SelectMsub(N, &DAG))
356 return SDValue(N, 0);
361 static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG& DAG,
362 TargetLowering::DAGCombinerInfo &DCI,
363 const MipsSubtarget* Subtarget) {
364 if (DCI.isBeforeLegalizeOps())
367 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem :
369 DebugLoc dl = N->getDebugLoc();
371 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue,
372 N->getOperand(0), N->getOperand(1));
373 SDValue InChain = DAG.getEntryNode();
374 SDValue InGlue = DivRem;
377 if (N->hasAnyUseOfValue(0)) {
378 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, Mips::LO, MVT::i32,
380 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
381 InChain = CopyFromLo.getValue(1);
382 InGlue = CopyFromLo.getValue(2);
386 if (N->hasAnyUseOfValue(1)) {
387 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl,
388 Mips::HI, MVT::i32, InGlue);
389 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
395 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
397 SelectionDAG &DAG = DCI.DAG;
398 unsigned opc = N->getOpcode();
403 return PerformADDECombine(N, DAG, DCI, Subtarget);
405 return PerformSUBECombine(N, DAG, DCI, Subtarget);
408 return PerformDivRemCombine(N, DAG, DCI, Subtarget);
414 SDValue MipsTargetLowering::
415 LowerOperation(SDValue Op, SelectionDAG &DAG) const
417 switch (Op.getOpcode())
419 case ISD::AND: return LowerANDOR(Op, DAG);
420 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
421 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
422 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
423 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
424 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
425 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
426 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
427 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
428 case ISD::OR: return LowerANDOR(Op, DAG);
429 case ISD::SELECT: return LowerSELECT(Op, DAG);
430 case ISD::SETCC: return LowerSETCC(Op, DAG);
431 case ISD::VASTART: return LowerVASTART(Op, DAG);
436 //===----------------------------------------------------------------------===//
437 // Lower helper functions
438 //===----------------------------------------------------------------------===//
440 // AddLiveIn - This helper function adds the specified physical register to the
441 // MachineFunction as a live in value. It also creates a corresponding
442 // virtual register for it.
444 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
446 assert(RC->contains(PReg) && "Not the correct regclass!");
447 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
448 MF.getRegInfo().addLiveIn(PReg, VReg);
452 // Get fp branch code (not opcode) from condition code.
453 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
454 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
455 return Mips::BRANCH_T;
457 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
458 return Mips::BRANCH_F;
460 return Mips::BRANCH_INVALID;
463 static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) {
466 llvm_unreachable("Unknown branch code");
467 case Mips::BRANCH_T : return Mips::BC1T;
468 case Mips::BRANCH_F : return Mips::BC1F;
469 case Mips::BRANCH_TL : return Mips::BC1TL;
470 case Mips::BRANCH_FL : return Mips::BC1FL;
474 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
476 default: llvm_unreachable("Unknown fp condition code!");
478 case ISD::SETOEQ: return Mips::FCOND_EQ;
479 case ISD::SETUNE: return Mips::FCOND_OGL;
481 case ISD::SETOLT: return Mips::FCOND_OLT;
483 case ISD::SETOGT: return Mips::FCOND_OGT;
485 case ISD::SETOLE: return Mips::FCOND_OLE;
487 case ISD::SETOGE: return Mips::FCOND_OGE;
488 case ISD::SETULT: return Mips::FCOND_ULT;
489 case ISD::SETULE: return Mips::FCOND_ULE;
490 case ISD::SETUGT: return Mips::FCOND_UGT;
491 case ISD::SETUGE: return Mips::FCOND_UGE;
492 case ISD::SETUO: return Mips::FCOND_UN;
493 case ISD::SETO: return Mips::FCOND_OR;
495 case ISD::SETONE: return Mips::FCOND_NEQ;
496 case ISD::SETUEQ: return Mips::FCOND_UEQ;
501 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
502 MachineBasicBlock *BB) const {
503 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
504 bool isFPCmp = false;
505 DebugLoc dl = MI->getDebugLoc();
507 switch (MI->getOpcode()) {
508 default: assert(false && "Unexpected instr type to insert");
509 case Mips::Select_FCC:
510 case Mips::Select_FCC_S32:
511 case Mips::Select_FCC_D32:
512 isFPCmp = true; // FALL THROUGH
513 case Mips::Select_CC:
514 case Mips::Select_CC_S32:
515 case Mips::Select_CC_D32: {
516 // To "insert" a SELECT_CC instruction, we actually have to insert the
517 // diamond control-flow pattern. The incoming instruction knows the
518 // destination vreg to set, the condition code register to branch on, the
519 // true/false values to select between, and a branch opcode to use.
520 const BasicBlock *LLVM_BB = BB->getBasicBlock();
521 MachineFunction::iterator It = BB;
528 // bNE r1, r0, copy1MBB
529 // fallthrough --> copy0MBB
530 MachineBasicBlock *thisMBB = BB;
531 MachineFunction *F = BB->getParent();
532 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
533 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
534 F->insert(It, copy0MBB);
535 F->insert(It, sinkMBB);
537 // Transfer the remainder of BB and its successor edges to sinkMBB.
538 sinkMBB->splice(sinkMBB->begin(), BB,
539 llvm::next(MachineBasicBlock::iterator(MI)),
541 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
543 // Next, add the true and fallthrough blocks as its successors.
544 BB->addSuccessor(copy0MBB);
545 BB->addSuccessor(sinkMBB);
547 // Emit the right instruction according to the type of the operands compared
549 // Find the condiction code present in the setcc operation.
550 Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm();
551 // Get the branch opcode from the branch code.
552 unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC));
553 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
555 BuildMI(BB, dl, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
556 .addReg(Mips::ZERO).addMBB(sinkMBB);
560 // # fallthrough to sinkMBB
563 // Update machine-CFG edges
564 BB->addSuccessor(sinkMBB);
567 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
570 BuildMI(*BB, BB->begin(), dl,
571 TII->get(Mips::PHI), MI->getOperand(0).getReg())
572 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
573 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB);
575 MI->eraseFromParent(); // The pseudo instruction is gone now.
581 //===----------------------------------------------------------------------===//
582 // Misc Lower Operation implementation
583 //===----------------------------------------------------------------------===//
585 SDValue MipsTargetLowering::
586 LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const
588 if (!Subtarget->isMips1())
591 MachineFunction &MF = DAG.getMachineFunction();
592 unsigned CCReg = AddLiveIn(MF, Mips::FCR31, Mips::CCRRegisterClass);
594 SDValue Chain = DAG.getEntryNode();
595 DebugLoc dl = Op.getDebugLoc();
596 SDValue Src = Op.getOperand(0);
598 // Set the condition register
599 SDValue CondReg = DAG.getCopyFromReg(Chain, dl, CCReg, MVT::i32);
600 CondReg = DAG.getCopyToReg(Chain, dl, Mips::AT, CondReg);
601 CondReg = DAG.getCopyFromReg(CondReg, dl, Mips::AT, MVT::i32);
603 SDValue Cst = DAG.getConstant(3, MVT::i32);
604 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i32, CondReg, Cst);
605 Cst = DAG.getConstant(2, MVT::i32);
606 SDValue Xor = DAG.getNode(ISD::XOR, dl, MVT::i32, Or, Cst);
608 SDValue InFlag(0, 0);
609 CondReg = DAG.getCopyToReg(Chain, dl, Mips::FCR31, Xor, InFlag);
611 // Emit the round instruction and bit convert to integer
612 SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, MVT::f32,
613 Src, CondReg.getValue(1));
614 SDValue BitCvt = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Trunc);
618 SDValue MipsTargetLowering::
619 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
621 SDValue Chain = Op.getOperand(0);
622 SDValue Size = Op.getOperand(1);
623 DebugLoc dl = Op.getDebugLoc();
625 // Get a reference from Mips stack pointer
626 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32);
628 // Subtract the dynamic size from the actual stack size to
629 // obtain the new stack size.
630 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
632 // The Sub result contains the new stack start address, so it
633 // must be placed in the stack pointer register.
634 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub);
636 // This node always has two return values: a new stack pointer
638 SDValue Ops[2] = { Sub, Chain };
639 return DAG.getMergeValues(Ops, 2, dl);
642 SDValue MipsTargetLowering::
643 LowerANDOR(SDValue Op, SelectionDAG &DAG) const
645 SDValue LHS = Op.getOperand(0);
646 SDValue RHS = Op.getOperand(1);
647 DebugLoc dl = Op.getDebugLoc();
649 if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp)
652 SDValue True = DAG.getConstant(1, MVT::i32);
653 SDValue False = DAG.getConstant(0, MVT::i32);
655 SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
656 LHS, True, False, LHS.getOperand(2));
657 SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
658 RHS, True, False, RHS.getOperand(2));
660 return DAG.getNode(Op.getOpcode(), dl, MVT::i32, LSEL, RSEL);
663 SDValue MipsTargetLowering::
664 LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
666 // The first operand is the chain, the second is the condition, the third is
667 // the block to branch to if the condition is true.
668 SDValue Chain = Op.getOperand(0);
669 SDValue Dest = Op.getOperand(2);
670 DebugLoc dl = Op.getDebugLoc();
672 if (Op.getOperand(1).getOpcode() != MipsISD::FPCmp)
675 SDValue CondRes = Op.getOperand(1);
676 SDValue CCNode = CondRes.getOperand(2);
678 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
679 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
681 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
685 SDValue MipsTargetLowering::
686 LowerSETCC(SDValue Op, SelectionDAG &DAG) const
688 // The operands to this are the left and right operands to compare (ops #0,
689 // and #1) and the condition code to compare them with (op #2) as a
691 SDValue LHS = Op.getOperand(0);
692 SDValue RHS = Op.getOperand(1);
693 DebugLoc dl = Op.getDebugLoc();
695 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
697 return DAG.getNode(MipsISD::FPCmp, dl, Op.getValueType(), LHS, RHS,
698 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
701 SDValue MipsTargetLowering::
702 LowerSELECT(SDValue Op, SelectionDAG &DAG) const
704 SDValue Cond = Op.getOperand(0);
705 SDValue True = Op.getOperand(1);
706 SDValue False = Op.getOperand(2);
707 DebugLoc dl = Op.getDebugLoc();
709 // if the incomming condition comes from a integer compare, the select
710 // operation must be SelectCC or a conditional move if the subtarget
712 if (Cond.getOpcode() != MipsISD::FPCmp) {
713 if (Subtarget->hasCondMov() && !True.getValueType().isFloatingPoint())
715 return DAG.getNode(MipsISD::SelectCC, dl, True.getValueType(),
719 // if the incomming condition comes from fpcmp, the select
720 // operation must use FPSelectCC.
721 SDValue CCNode = Cond.getOperand(2);
722 return DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
723 Cond, True, False, CCNode);
726 SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
727 SelectionDAG &DAG) const {
728 // FIXME there isn't actually debug info here
729 DebugLoc dl = Op.getDebugLoc();
730 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
732 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
733 SDVTList VTs = DAG.getVTList(MVT::i32);
735 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering();
737 // %gp_rel relocation
738 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
739 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
741 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
742 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
743 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
745 // %hi/%lo relocation
746 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
747 MipsII::MO_ABS_HILO);
748 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GA, 1);
749 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
750 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
753 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
755 SDValue ResNode = DAG.getLoad(MVT::i32, dl,
756 DAG.getEntryNode(), GA, MachinePointerInfo(),
758 // On functions and global targets not internal linked only
759 // a load from got/GP is necessary for PIC to work.
760 if (!GV->hasLocalLinkage() || isa<Function>(GV))
762 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
763 return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo);
766 llvm_unreachable("Dont know how to handle GlobalAddress");
770 SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
771 SelectionDAG &DAG) const {
772 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
773 assert(false && "implement LowerBlockAddress for -static");
774 return SDValue(0, 0);
777 // FIXME there isn't actually debug info here
778 DebugLoc dl = Op.getDebugLoc();
779 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
780 SDValue BAGOTOffset = DAG.getBlockAddress(BA, MVT::i32, true,
782 SDValue BALOOffset = DAG.getBlockAddress(BA, MVT::i32, true,
783 MipsII::MO_ABS_HILO);
784 SDValue Load = DAG.getLoad(MVT::i32, dl,
785 DAG.getEntryNode(), BAGOTOffset,
786 MachinePointerInfo(), false, false, 0);
787 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALOOffset);
788 return DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
792 SDValue MipsTargetLowering::
793 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
795 llvm_unreachable("TLS not implemented for MIPS.");
796 return SDValue(); // Not reached
799 SDValue MipsTargetLowering::
800 LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
804 // FIXME there isn't actually debug info here
805 DebugLoc dl = Op.getDebugLoc();
806 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
807 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT : MipsII::MO_ABS_HILO;
809 EVT PtrVT = Op.getValueType();
810 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
812 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
815 SDValue Ops[] = { JTI };
816 HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1);
817 } else // Emit Load from Global Pointer
818 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI,
819 MachinePointerInfo(),
822 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTI);
823 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
828 SDValue MipsTargetLowering::
829 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
832 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
833 const Constant *C = N->getConstVal();
834 // FIXME there isn't actually debug info here
835 DebugLoc dl = Op.getDebugLoc();
838 // FIXME: we should reference the constant pool using small data sections,
839 // but the asm printer currently doens't support this feature without
840 // hacking it. This feature should come soon so we can uncomment the
842 //if (IsInSmallSection(C->getType())) {
843 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
844 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
845 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
847 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
848 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
849 N->getOffset(), MipsII::MO_ABS_HILO);
850 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CP);
851 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP);
852 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
854 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
855 N->getOffset(), MipsII::MO_GOT);
856 SDValue Load = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(),
857 CP, MachinePointerInfo::getConstantPool(),
859 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP);
860 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
866 SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
867 MachineFunction &MF = DAG.getMachineFunction();
868 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
870 DebugLoc dl = Op.getDebugLoc();
871 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
874 // vastart just stores the address of the VarArgsFrameIndex slot into the
875 // memory location argument.
876 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
877 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
878 MachinePointerInfo(SV),
882 //===----------------------------------------------------------------------===//
883 // Calling Convention Implementation
884 //===----------------------------------------------------------------------===//
886 #include "MipsGenCallingConv.inc"
888 //===----------------------------------------------------------------------===//
889 // TODO: Implement a generic logic using tblgen that can support this.
890 // Mips O32 ABI rules:
892 // i32 - Passed in A0, A1, A2, A3 and stack
893 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
894 // an argument. Otherwise, passed in A1, A2, A3 and stack.
895 // f64 - Only passed in two aliased f32 registers if no int reg has been used
896 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
897 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
899 //===----------------------------------------------------------------------===//
901 static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
902 MVT LocVT, CCValAssign::LocInfo LocInfo,
903 ISD::ArgFlagsTy ArgFlags, CCState &State) {
905 static const unsigned IntRegsSize=4, FloatRegsSize=2;
907 static const unsigned IntRegs[] = {
908 Mips::A0, Mips::A1, Mips::A2, Mips::A3
910 static const unsigned F32Regs[] = {
913 static const unsigned F64Regs[] = {
918 static bool IntRegUsed = false;
920 // This must be the first arg of the call if no regs have been allocated.
921 // Initialize IntRegUsed in that case.
922 if (IntRegs[State.getFirstUnallocated(IntRegs, IntRegsSize)] == Mips::A0 &&
923 F32Regs[State.getFirstUnallocated(F32Regs, FloatRegsSize)] == Mips::F12 &&
924 F64Regs[State.getFirstUnallocated(F64Regs, FloatRegsSize)] == Mips::D6)
927 // Promote i8 and i16
928 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
930 if (ArgFlags.isSExt())
931 LocInfo = CCValAssign::SExt;
932 else if (ArgFlags.isZExt())
933 LocInfo = CCValAssign::ZExt;
935 LocInfo = CCValAssign::AExt;
938 if (ValVT == MVT::i32) {
939 Reg = State.AllocateReg(IntRegs, IntRegsSize);
941 } else if (ValVT == MVT::f32) {
942 // An int reg has to be marked allocated regardless of whether or not
943 // IntRegUsed is true.
944 Reg = State.AllocateReg(IntRegs, IntRegsSize);
947 if (Reg) // Int reg is available
950 unsigned FReg = State.AllocateReg(F32Regs, FloatRegsSize);
951 if (FReg) // F32 reg is available
953 else if (Reg) // No F32 regs are available, but an int reg is available.
956 } else if (ValVT == MVT::f64) {
957 // Int regs have to be marked allocated regardless of whether or not
958 // IntRegUsed is true.
959 Reg = State.AllocateReg(IntRegs, IntRegsSize);
961 Reg = State.AllocateReg(IntRegs, IntRegsSize);
962 else if (Reg == Mips::A3)
964 State.AllocateReg(IntRegs, IntRegsSize);
966 // At this point, Reg is A0, A2 or 0, and all the unavailable integer regs
967 // are marked as allocated.
969 if (Reg)// if int reg is available
972 unsigned FReg = State.AllocateReg(F64Regs, FloatRegsSize);
973 if (FReg) // F64 reg is available.
975 else if (Reg) // No F64 regs are available, but an int reg is available.
979 assert(false && "cannot handle this ValVT");
982 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
983 unsigned Offset = State.AllocateStack(SizeInBytes, SizeInBytes);
984 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
986 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
988 return false; // CC must always match
991 static bool CC_MipsO32_VarArgs(unsigned ValNo, MVT ValVT,
992 MVT LocVT, CCValAssign::LocInfo LocInfo,
993 ISD::ArgFlagsTy ArgFlags, CCState &State) {
995 static const unsigned IntRegsSize=4;
997 static const unsigned IntRegs[] = {
998 Mips::A0, Mips::A1, Mips::A2, Mips::A3
1001 // Promote i8 and i16
1002 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
1004 if (ArgFlags.isSExt())
1005 LocInfo = CCValAssign::SExt;
1006 else if (ArgFlags.isZExt())
1007 LocInfo = CCValAssign::ZExt;
1009 LocInfo = CCValAssign::AExt;
1014 if (ValVT == MVT::i32 || ValVT == MVT::f32) {
1015 Reg = State.AllocateReg(IntRegs, IntRegsSize);
1017 } else if (ValVT == MVT::f64) {
1018 Reg = State.AllocateReg(IntRegs, IntRegsSize);
1019 if (Reg == Mips::A1 || Reg == Mips::A3)
1020 Reg = State.AllocateReg(IntRegs, IntRegsSize);
1021 State.AllocateReg(IntRegs, IntRegsSize);
1024 llvm_unreachable("Cannot handle this ValVT.");
1027 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
1028 unsigned Offset = State.AllocateStack(SizeInBytes, SizeInBytes);
1029 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
1031 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1033 return false; // CC must always match
1036 //===----------------------------------------------------------------------===//
1037 // Call Calling Convention Implementation
1038 //===----------------------------------------------------------------------===//
1040 /// LowerCall - functions arguments are copied from virtual regs to
1041 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
1042 /// TODO: isTailCall.
1044 MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1045 CallingConv::ID CallConv, bool isVarArg,
1047 const SmallVectorImpl<ISD::OutputArg> &Outs,
1048 const SmallVectorImpl<SDValue> &OutVals,
1049 const SmallVectorImpl<ISD::InputArg> &Ins,
1050 DebugLoc dl, SelectionDAG &DAG,
1051 SmallVectorImpl<SDValue> &InVals) const {
1052 // MIPs target does not yet support tail call optimization.
1055 MachineFunction &MF = DAG.getMachineFunction();
1056 MachineFrameInfo *MFI = MF.getFrameInfo();
1057 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1059 // Analyze operands of the call, assigning locations to each operand.
1060 SmallVector<CCValAssign, 16> ArgLocs;
1061 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1064 // To meet O32 ABI, Mips must always allocate 16 bytes on
1065 // the stack (even if less than 4 are used as arguments)
1066 if (Subtarget->isABI_O32()) {
1067 int VTsize = MVT(MVT::i32).getSizeInBits()/8;
1068 MFI->CreateFixedObject(VTsize, (VTsize*3), true);
1069 CCInfo.AnalyzeCallOperands(Outs,
1070 isVarArg ? CC_MipsO32_VarArgs : CC_MipsO32);
1072 CCInfo.AnalyzeCallOperands(Outs, CC_Mips);
1074 // Get a count of how many bytes are to be pushed on the stack.
1075 unsigned NumBytes = CCInfo.getNextStackOffset();
1076 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1078 // With EABI is it possible to have 16 args on registers.
1079 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
1080 SmallVector<SDValue, 8> MemOpChains;
1082 // First/LastArgStackLoc contains the first/last
1083 // "at stack" argument location.
1084 int LastArgStackLoc = 0;
1085 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
1087 // Walk the register/memloc assignments, inserting copies/loads.
1088 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1089 SDValue Arg = OutVals[i];
1090 CCValAssign &VA = ArgLocs[i];
1092 // Promote the value if needed.
1093 switch (VA.getLocInfo()) {
1094 default: llvm_unreachable("Unknown loc info!");
1095 case CCValAssign::Full:
1096 if (Subtarget->isABI_O32() && VA.isRegLoc()) {
1097 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
1098 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
1099 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
1100 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
1101 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
1102 DAG.getConstant(0, getPointerTy()));
1103 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
1104 DAG.getConstant(1, getPointerTy()));
1105 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
1106 RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi));
1111 case CCValAssign::SExt:
1112 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1114 case CCValAssign::ZExt:
1115 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1117 case CCValAssign::AExt:
1118 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1122 // Arguments that can be passed on register must be kept at
1123 // RegsToPass vector
1124 if (VA.isRegLoc()) {
1125 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1129 // Register can't get to this point...
1130 assert(VA.isMemLoc());
1132 // Create the frame index object for this incoming parameter
1133 // This guarantees that when allocating Local Area the firsts
1134 // 16 bytes which are alwayes reserved won't be overwritten
1135 // if O32 ABI is used. For EABI the first address is zero.
1136 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
1137 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
1138 LastArgStackLoc, true);
1140 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
1142 // emit ISD::STORE whichs stores the
1143 // parameter value to a stack Location
1144 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
1145 MachinePointerInfo(),
1149 // Transform all store nodes into one single node because all store
1150 // nodes are independent of each other.
1151 if (!MemOpChains.empty())
1152 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1153 &MemOpChains[0], MemOpChains.size());
1155 // Build a sequence of copy-to-reg nodes chained together with token
1156 // chain and flag operands which copy the outgoing args into registers.
1157 // The InFlag in necessary since all emited instructions must be
1160 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1161 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1162 RegsToPass[i].second, InFlag);
1163 InFlag = Chain.getValue(1);
1166 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1167 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1168 // node so that legalize doesn't hack it.
1169 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
1170 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1171 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
1172 getPointerTy(), 0, OpFlag);
1173 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1174 Callee = DAG.getTargetExternalSymbol(S->getSymbol(),
1175 getPointerTy(), OpFlag);
1177 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
1178 // = Chain, Callee, Reg#1, Reg#2, ...
1180 // Returns a chain & a flag for retval copy to use.
1181 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1182 SmallVector<SDValue, 8> Ops;
1183 Ops.push_back(Chain);
1184 Ops.push_back(Callee);
1186 // Add argument registers to the end of the list so that they are
1187 // known live into the call.
1188 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1189 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1190 RegsToPass[i].second.getValueType()));
1192 if (InFlag.getNode())
1193 Ops.push_back(InFlag);
1195 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
1196 InFlag = Chain.getValue(1);
1198 // Create a stack location to hold GP when PIC is used. This stack
1199 // location is used on function prologue to save GP and also after all
1200 // emited CALL's to restore GP.
1202 // Function can have an arbitrary number of calls, so
1203 // hold the LastArgStackLoc with the biggest offset.
1205 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1206 if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
1207 LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
1208 // Create the frame index only once. SPOffset here can be anything
1209 // (this will be fixed on processFunctionBeforeFrameFinalized)
1210 if (MipsFI->getGPStackOffset() == -1) {
1211 FI = MFI->CreateFixedObject(4, 0, true);
1212 MipsFI->setGPFI(FI);
1214 MipsFI->setGPStackOffset(LastArgStackLoc);
1218 FI = MipsFI->getGPFI();
1219 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1220 SDValue GPLoad = DAG.getLoad(MVT::i32, dl, Chain, FIN,
1221 MachinePointerInfo::getFixedStack(FI),
1223 Chain = GPLoad.getValue(1);
1224 Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, MVT::i32),
1225 GPLoad, SDValue(0,0));
1226 InFlag = Chain.getValue(1);
1229 // Create the CALLSEQ_END node.
1230 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1231 DAG.getIntPtrConstant(0, true), InFlag);
1232 InFlag = Chain.getValue(1);
1234 // Handle result values, copying them out of physregs into vregs that we
1236 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
1237 Ins, dl, DAG, InVals);
1240 /// LowerCallResult - Lower the result values of a call into the
1241 /// appropriate copies out of appropriate physical registers.
1243 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1244 CallingConv::ID CallConv, bool isVarArg,
1245 const SmallVectorImpl<ISD::InputArg> &Ins,
1246 DebugLoc dl, SelectionDAG &DAG,
1247 SmallVectorImpl<SDValue> &InVals) const {
1249 // Assign locations to each value returned by this call.
1250 SmallVector<CCValAssign, 16> RVLocs;
1251 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1252 RVLocs, *DAG.getContext());
1254 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
1256 // Copy all of the result registers out of their specified physreg.
1257 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1258 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
1259 RVLocs[i].getValVT(), InFlag).getValue(1);
1260 InFlag = Chain.getValue(2);
1261 InVals.push_back(Chain.getValue(0));
1267 //===----------------------------------------------------------------------===//
1268 // Formal Arguments Calling Convention Implementation
1269 //===----------------------------------------------------------------------===//
1271 /// LowerFormalArguments - transform physical registers into virtual registers
1272 /// and generate load operations for arguments places on the stack.
1274 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
1275 CallingConv::ID CallConv, bool isVarArg,
1276 const SmallVectorImpl<ISD::InputArg>
1278 DebugLoc dl, SelectionDAG &DAG,
1279 SmallVectorImpl<SDValue> &InVals)
1282 MachineFunction &MF = DAG.getMachineFunction();
1283 MachineFrameInfo *MFI = MF.getFrameInfo();
1284 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1286 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
1287 MipsFI->setVarArgsFrameIndex(0);
1289 // Used with vargs to acumulate store chains.
1290 std::vector<SDValue> OutChains;
1292 // Keep track of the last register used for arguments
1293 unsigned ArgRegEnd = 0;
1295 // Assign locations to all of the incoming arguments.
1296 SmallVector<CCValAssign, 16> ArgLocs;
1297 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1298 ArgLocs, *DAG.getContext());
1300 if (Subtarget->isABI_O32())
1301 CCInfo.AnalyzeFormalArguments(Ins,
1302 isVarArg ? CC_MipsO32_VarArgs : CC_MipsO32);
1304 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips);
1308 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
1310 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1311 CCValAssign &VA = ArgLocs[i];
1313 // Arguments stored on registers
1314 if (VA.isRegLoc()) {
1315 EVT RegVT = VA.getLocVT();
1316 ArgRegEnd = VA.getLocReg();
1317 TargetRegisterClass *RC = 0;
1319 if (RegVT == MVT::i32)
1320 RC = Mips::CPURegsRegisterClass;
1321 else if (RegVT == MVT::f32)
1322 RC = Mips::FGR32RegisterClass;
1323 else if (RegVT == MVT::f64) {
1324 if (!Subtarget->isSingleFloat())
1325 RC = Mips::AFGR64RegisterClass;
1327 llvm_unreachable("RegVT not supported by FormalArguments Lowering");
1329 // Transform the arguments stored on
1330 // physical registers into virtual ones
1331 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegEnd, RC);
1332 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1334 // If this is an 8 or 16-bit value, it has been passed promoted
1335 // to 32 bits. Insert an assert[sz]ext to capture this, then
1336 // truncate to the right size.
1337 if (VA.getLocInfo() != CCValAssign::Full) {
1338 unsigned Opcode = 0;
1339 if (VA.getLocInfo() == CCValAssign::SExt)
1340 Opcode = ISD::AssertSext;
1341 else if (VA.getLocInfo() == CCValAssign::ZExt)
1342 Opcode = ISD::AssertZext;
1344 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
1345 DAG.getValueType(VA.getValVT()));
1346 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1349 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64
1350 if (Subtarget->isABI_O32()) {
1351 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32)
1352 ArgValue = DAG.getNode(ISD::BITCAST, dl, MVT::f32, ArgValue);
1353 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) {
1354 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
1355 VA.getLocReg()+1, RC);
1356 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
1357 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, ArgValue2, ArgValue);
1358 ArgValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Pair);
1362 InVals.push_back(ArgValue);
1363 } else { // VA.isRegLoc()
1366 assert(VA.isMemLoc());
1368 // The last argument is not a register anymore
1371 // The stack pointer offset is relative to the caller stack frame.
1372 // Since the real stack size is unknown here, a negative SPOffset
1373 // is used so there's a way to adjust these offsets when the stack
1374 // size get known (on EliminateFrameIndex). A dummy SPOffset is
1375 // used instead of a direct negative address (which is recorded to
1376 // be used on emitPrologue) to avoid mis-calc of the first stack
1377 // offset on PEI::calculateFrameObjectOffsets.
1378 // Arguments are always 32-bit.
1379 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1380 int FI = MFI->CreateFixedObject(ArgSize, 0, true);
1381 MipsFI->recordLoadArgsFI(FI, -(ArgSize+
1382 (FirstStackArgLoc + VA.getLocMemOffset())));
1384 // Create load nodes to retrieve arguments from the stack
1385 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1386 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
1387 MachinePointerInfo::getFixedStack(FI),
1392 // The mips ABIs for returning structs by value requires that we copy
1393 // the sret argument into $v0 for the return. Save the argument into
1394 // a virtual register so that we can access it from the return points.
1395 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1396 unsigned Reg = MipsFI->getSRetReturnReg();
1398 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
1399 MipsFI->setSRetReturnReg(Reg);
1401 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1402 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1405 // To meet ABI, when VARARGS are passed on registers, the registers
1406 // must have their values written to the caller stack frame. If the last
1407 // argument was placed in the stack, there's no need to save any register.
1408 if ((isVarArg) && (Subtarget->isABI_O32() && ArgRegEnd)) {
1409 if (StackPtr.getNode() == 0)
1410 StackPtr = DAG.getRegister(StackReg, getPointerTy());
1412 // The last register argument that must be saved is Mips::A3
1413 TargetRegisterClass *RC = Mips::CPURegsRegisterClass;
1414 unsigned StackLoc = ArgLocs.size()-1;
1416 for (++ArgRegEnd; ArgRegEnd <= Mips::A3; ++ArgRegEnd, ++StackLoc) {
1417 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegEnd, RC);
1418 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32);
1420 int FI = MFI->CreateFixedObject(4, 0, true);
1421 MipsFI->recordStoreVarArgsFI(FI, -(4+(StackLoc*4)));
1422 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
1423 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff,
1424 MachinePointerInfo(),
1427 // Record the frame index of the first variable argument
1428 // which is a value necessary to VASTART.
1429 if (!MipsFI->getVarArgsFrameIndex())
1430 MipsFI->setVarArgsFrameIndex(FI);
1434 // All stores are grouped in one node to allow the matching between
1435 // the size of Ins and InVals. This only happens when on varg functions
1436 if (!OutChains.empty()) {
1437 OutChains.push_back(Chain);
1438 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1439 &OutChains[0], OutChains.size());
1445 //===----------------------------------------------------------------------===//
1446 // Return Value Calling Convention Implementation
1447 //===----------------------------------------------------------------------===//
1450 MipsTargetLowering::LowerReturn(SDValue Chain,
1451 CallingConv::ID CallConv, bool isVarArg,
1452 const SmallVectorImpl<ISD::OutputArg> &Outs,
1453 const SmallVectorImpl<SDValue> &OutVals,
1454 DebugLoc dl, SelectionDAG &DAG) const {
1456 // CCValAssign - represent the assignment of
1457 // the return value to a location
1458 SmallVector<CCValAssign, 16> RVLocs;
1460 // CCState - Info about the registers and stack slot.
1461 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1462 RVLocs, *DAG.getContext());
1464 // Analize return values.
1465 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
1467 // If this is the first return lowered for this function, add
1468 // the regs to the liveout set for the function.
1469 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1470 for (unsigned i = 0; i != RVLocs.size(); ++i)
1471 if (RVLocs[i].isRegLoc())
1472 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1477 // Copy the result values into the output registers.
1478 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1479 CCValAssign &VA = RVLocs[i];
1480 assert(VA.isRegLoc() && "Can only return in registers!");
1482 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1485 // guarantee that all emitted copies are
1486 // stuck together, avoiding something bad
1487 Flag = Chain.getValue(1);
1490 // The mips ABIs for returning structs by value requires that we copy
1491 // the sret argument into $v0 for the return. We saved the argument into
1492 // a virtual register in the entry block, so now we copy the value out
1494 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1495 MachineFunction &MF = DAG.getMachineFunction();
1496 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1497 unsigned Reg = MipsFI->getSRetReturnReg();
1500 llvm_unreachable("sret virtual register not created in the entry block");
1501 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1503 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
1504 Flag = Chain.getValue(1);
1507 // Return on Mips is always a "jr $ra"
1509 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1510 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
1512 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1513 Chain, DAG.getRegister(Mips::RA, MVT::i32));
1516 //===----------------------------------------------------------------------===//
1517 // Mips Inline Assembly Support
1518 //===----------------------------------------------------------------------===//
1520 /// getConstraintType - Given a constraint letter, return the type of
1521 /// constraint it is for this target.
1522 MipsTargetLowering::ConstraintType MipsTargetLowering::
1523 getConstraintType(const std::string &Constraint) const
1525 // Mips specific constrainy
1526 // GCC config/mips/constraints.md
1528 // 'd' : An address register. Equivalent to r
1529 // unless generating MIPS16 code.
1530 // 'y' : Equivalent to r; retained for
1531 // backwards compatibility.
1532 // 'f' : Floating Point registers.
1533 if (Constraint.size() == 1) {
1534 switch (Constraint[0]) {
1539 return C_RegisterClass;
1543 return TargetLowering::getConstraintType(Constraint);
1546 /// Examine constraint type and operand type and determine a weight value.
1547 /// This object must already have been set up with the operand type
1548 /// and the current alternative constraint selected.
1549 TargetLowering::ConstraintWeight
1550 MipsTargetLowering::getSingleConstraintMatchWeight(
1551 AsmOperandInfo &info, const char *constraint) const {
1552 ConstraintWeight weight = CW_Invalid;
1553 Value *CallOperandVal = info.CallOperandVal;
1554 // If we don't have a value, we can't do a match,
1555 // but allow it at the lowest weight.
1556 if (CallOperandVal == NULL)
1558 const Type *type = CallOperandVal->getType();
1559 // Look at the constraint type.
1560 switch (*constraint) {
1562 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
1566 if (type->isIntegerTy())
1567 weight = CW_Register;
1570 if (type->isFloatTy())
1571 weight = CW_Register;
1577 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1578 /// return a list of registers that can be used to satisfy the constraint.
1579 /// This should only be used for C_RegisterClass constraints.
1580 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
1581 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
1583 if (Constraint.size() == 1) {
1584 switch (Constraint[0]) {
1586 return std::make_pair(0U, Mips::CPURegsRegisterClass);
1589 return std::make_pair(0U, Mips::FGR32RegisterClass);
1591 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1592 return std::make_pair(0U, Mips::AFGR64RegisterClass);
1595 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1598 /// Given a register class constraint, like 'r', if this corresponds directly
1599 /// to an LLVM register class, return a register of 0 and the register class
1601 std::vector<unsigned> MipsTargetLowering::
1602 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1605 if (Constraint.size() != 1)
1606 return std::vector<unsigned>();
1608 switch (Constraint[0]) {
1611 // GCC Mips Constraint Letters
1614 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
1615 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
1616 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
1620 if (VT == MVT::f32) {
1621 if (Subtarget->isSingleFloat())
1622 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
1623 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
1624 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
1625 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
1626 Mips::F30, Mips::F31, 0);
1628 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
1629 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
1630 Mips::F28, Mips::F30, 0);
1634 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1635 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
1636 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
1637 Mips::D14, Mips::D15, 0);
1639 return std::vector<unsigned>();
1643 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1644 // The Mips target isn't yet aware of offsets.
1648 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
1649 if (VT != MVT::f32 && VT != MVT::f64)
1651 if (Imm.isNegZero())
1653 return Imm.isZero();