1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
17 #include "MipsISelLowering.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsTargetMachine.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
39 const char *MipsTargetLowering::
40 getTargetNodeName(unsigned Opcode) const
44 case MipsISD::JmpLink : return "MipsISD::JmpLink";
45 case MipsISD::Hi : return "MipsISD::Hi";
46 case MipsISD::Lo : return "MipsISD::Lo";
47 case MipsISD::GPRel : return "MipsISD::GPRel";
48 case MipsISD::Ret : return "MipsISD::Ret";
49 case MipsISD::SelectCC : return "MipsISD::SelectCC";
50 case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
51 case MipsISD::FPCmp : return "MipsISD::FPCmp";
52 default : return NULL;
57 MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
59 Subtarget = &TM.getSubtarget<MipsSubtarget>();
61 // Mips does not have i1 type, so use i32 for
62 // setcc operations results (slt, sgt, ...).
63 setSetCCResultContents(ZeroOrOneSetCCResult);
65 // JumpTable targets must use GOT when using PIC_
66 setUsesGlobalOffsetTable(true);
68 // Set up the register classes
69 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
71 // When dealing with single precision only, use libcalls
72 if (!Subtarget->isSingleFloat()) {
73 addRegisterClass(MVT::f32, Mips::AFGR32RegisterClass);
74 if (!Subtarget->isFP64bit())
75 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
77 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
79 // Load extented operations for i1 types must be promoted
80 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
81 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
82 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
84 // Mips Custom Operations
85 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
86 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
87 setOperationAction(ISD::RET, MVT::Other, Custom);
88 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
89 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
90 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
91 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
93 // Operations not directly supported by Mips.
94 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
95 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
96 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
97 setOperationAction(ISD::SELECT, MVT::i32, Expand);
98 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
99 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
100 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
101 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
102 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
103 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
104 setOperationAction(ISD::ROTL, MVT::i32, Expand);
105 setOperationAction(ISD::ROTR, MVT::i32, Expand);
106 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
107 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
108 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
109 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
111 // We don't have line number support yet.
112 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
113 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
114 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
115 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
117 // Use the default for now
118 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
119 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
120 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
122 if (Subtarget->isSingleFloat())
123 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
125 if (!Subtarget->hasSEInReg()) {
126 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
127 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
130 setStackPointerRegisterToSaveRestore(Mips::SP);
131 computeRegisterProperties();
135 MVT MipsTargetLowering::getSetCCResultType(const SDValue &) const {
140 SDValue MipsTargetLowering::
141 LowerOperation(SDValue Op, SelectionDAG &DAG)
143 switch (Op.getOpcode())
145 case ISD::CALL: return LowerCALL(Op, DAG);
146 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
147 case ISD::RET: return LowerRET(Op, DAG);
148 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
149 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
150 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
151 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
152 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
158 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
159 MachineBasicBlock *BB)
161 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
162 switch (MI->getOpcode()) {
163 default: assert(false && "Unexpected instr type to insert");
164 case Mips::Select_CC: {
165 // To "insert" a SELECT_CC instruction, we actually have to insert the
166 // diamond control-flow pattern. The incoming instruction knows the
167 // destination vreg to set, the condition code register to branch on, the
168 // true/false values to select between, and a branch opcode to use.
169 const BasicBlock *LLVM_BB = BB->getBasicBlock();
170 MachineFunction::iterator It = BB;
177 // bNE r1, r0, copy1MBB
178 // fallthrough --> copy0MBB
179 MachineBasicBlock *thisMBB = BB;
180 MachineFunction *F = BB->getParent();
181 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
182 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
183 BuildMI(BB, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
184 .addReg(Mips::ZERO).addMBB(sinkMBB);
185 F->insert(It, copy0MBB);
186 F->insert(It, sinkMBB);
187 // Update machine-CFG edges by first adding all successors of the current
188 // block to the new block which will contain the Phi node for the select.
189 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
190 e = BB->succ_end(); i != e; ++i)
191 sinkMBB->addSuccessor(*i);
192 // Next, remove all successors of the current block, and add the true
193 // and fallthrough blocks as its successors.
194 while(!BB->succ_empty())
195 BB->removeSuccessor(BB->succ_begin());
196 BB->addSuccessor(copy0MBB);
197 BB->addSuccessor(sinkMBB);
201 // # fallthrough to sinkMBB
204 // Update machine-CFG edges
205 BB->addSuccessor(sinkMBB);
208 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
211 BuildMI(BB, TII->get(Mips::PHI), MI->getOperand(0).getReg())
212 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
213 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
215 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
221 //===----------------------------------------------------------------------===//
222 // Lower helper functions
223 //===----------------------------------------------------------------------===//
225 // AddLiveIn - This helper function adds the specified physical register to the
226 // MachineFunction as a live in value. It also creates a corresponding
227 // virtual register for it.
229 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
231 assert(RC->contains(PReg) && "Not the correct regclass!");
232 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
233 MF.getRegInfo().addLiveIn(PReg, VReg);
237 // A address must be loaded from a small section if its size is less than the
238 // small section size threshold. Data in this section must be addressed using
240 bool MipsTargetLowering::IsInSmallSection(unsigned Size) {
241 return (Size > 0 && (Size <= Subtarget->getSSectionThreshold()));
244 // Discover if this global address can be placed into small data/bss section.
245 bool MipsTargetLowering::IsGlobalInSmallSection(GlobalValue *GV)
247 const TargetData *TD = getTargetData();
248 const GlobalVariable *GVA = dyn_cast<GlobalVariable>(GV);
253 const Type *Ty = GV->getType()->getElementType();
254 unsigned Size = TD->getABITypeSize(Ty);
256 // if this is a internal constant string, there is a special
257 // section for it, but not in small data/bss.
258 if (GVA->hasInitializer() && GV->hasInternalLinkage()) {
259 Constant *C = GVA->getInitializer();
260 const ConstantArray *CVA = dyn_cast<ConstantArray>(C);
261 if (CVA && CVA->isCString())
265 return IsInSmallSection(Size);
268 //===----------------------------------------------------------------------===//
269 // Misc Lower Operation implementation
270 //===----------------------------------------------------------------------===//
271 SDValue MipsTargetLowering::
272 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
274 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
275 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
277 if (!Subtarget->hasABICall()) {
278 if (isa<Function>(GV)) return GA;
279 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
280 SDValue Ops[] = { GA };
282 if (IsGlobalInSmallSection(GV)) { // %gp_rel relocation
283 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, VTs, 1, Ops, 1);
284 SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
285 return DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
287 // %hi/%lo relocation
288 SDValue HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
289 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
290 return DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
292 } else { // Abicall relocations, TODO: make this cleaner.
293 SDValue ResNode = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0);
294 // On functions and global targets not internal linked only
295 // a load from got/GP is necessary for PIC to work.
296 if (!GV->hasInternalLinkage() || isa<Function>(GV))
298 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
299 return DAG.getNode(ISD::ADD, MVT::i32, ResNode, Lo);
302 assert(0 && "Dont know how to handle GlobalAddress");
306 SDValue MipsTargetLowering::
307 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
309 assert(0 && "TLS not implemented for MIPS.");
310 return SDValue(); // Not reached
313 SDValue MipsTargetLowering::
314 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG)
316 SDValue LHS = Op.getOperand(0);
317 SDValue RHS = Op.getOperand(1);
318 SDValue True = Op.getOperand(2);
319 SDValue False = Op.getOperand(3);
320 SDValue CC = Op.getOperand(4);
322 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
323 SDValue Ops[] = { LHS, RHS, CC };
324 SDValue SetCCRes = DAG.getNode(ISD::SETCC, VTs, 1, Ops, 3);
326 return DAG.getNode(MipsISD::SelectCC, True.getValueType(),
327 SetCCRes, True, False);
330 SDValue MipsTargetLowering::
331 LowerJumpTable(SDValue Op, SelectionDAG &DAG)
336 MVT PtrVT = Op.getValueType();
337 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
338 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
340 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
341 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
342 SDValue Ops[] = { JTI };
343 HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
344 } else // Emit Load from Global Pointer
345 HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), JTI, NULL, 0);
347 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, JTI);
348 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
353 SDValue MipsTargetLowering::
354 LowerConstantPool(SDValue Op, SelectionDAG &DAG)
357 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
358 Constant *C = N->getConstVal();
359 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
362 if (!Subtarget->hasABICall() &&
363 IsInSmallSection(getTargetData()->getABITypeSize(C->getType()))) {
364 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
365 SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
366 ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
367 } else { // %hi/%lo relocation
368 SDValue HiPart = DAG.getNode(MipsISD::Hi, MVT::i32, CP);
369 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, CP);
370 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
376 //===----------------------------------------------------------------------===//
377 // Calling Convention Implementation
379 // The lower operations present on calling convention works on this order:
380 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
381 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
382 // LowerRET (virt regs --> phys regs)
383 // LowerCALL (phys regs --> virt regs)
385 //===----------------------------------------------------------------------===//
387 #include "MipsGenCallingConv.inc"
389 //===----------------------------------------------------------------------===//
390 // CALL Calling Convention Implementation
391 //===----------------------------------------------------------------------===//
393 /// Mips custom CALL implementation
394 SDValue MipsTargetLowering::
395 LowerCALL(SDValue Op, SelectionDAG &DAG)
397 unsigned CallingConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
399 // By now, only CallingConv::C implemented
400 switch (CallingConv) {
402 assert(0 && "Unsupported calling convention");
403 case CallingConv::Fast:
405 return LowerCCCCallTo(Op, DAG, CallingConv);
409 /// LowerCCCCallTo - functions arguments are copied from virtual
410 /// regs to (physical regs)/(stack frame), CALLSEQ_START and
411 /// CALLSEQ_END are emitted.
412 /// TODO: isVarArg, isTailCall.
413 SDValue MipsTargetLowering::
414 LowerCCCCallTo(SDValue Op, SelectionDAG &DAG, unsigned CC)
416 MachineFunction &MF = DAG.getMachineFunction();
418 SDValue Chain = Op.getOperand(0);
419 SDValue Callee = Op.getOperand(4);
420 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
422 MachineFrameInfo *MFI = MF.getFrameInfo();
424 // Analyze operands of the call, assigning locations to each operand.
425 SmallVector<CCValAssign, 16> ArgLocs;
426 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
428 // To meet O32 ABI, Mips must always allocate 16 bytes on
429 // the stack (even if less than 4 are used as arguments)
430 if (Subtarget->isABI_O32()) {
431 int VTsize = MVT(MVT::i32).getSizeInBits()/8;
432 MFI->CreateFixedObject(VTsize, (VTsize*3));
435 CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips);
437 // Get a count of how many bytes are to be pushed on the stack.
438 unsigned NumBytes = CCInfo.getNextStackOffset();
439 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
442 // With EABI is it possible to have 16 args on registers.
443 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
444 SmallVector<SDValue, 8> MemOpChains;
446 // First/LastArgStackLoc contains the first/last
447 // "at stack" argument location.
448 int LastArgStackLoc = 0;
449 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
451 // Walk the register/memloc assignments, inserting copies/loads.
452 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
453 CCValAssign &VA = ArgLocs[i];
455 // Arguments start after the 5 first operands of ISD::CALL
456 SDValue Arg = Op.getOperand(5+2*VA.getValNo());
458 // Promote the value if needed.
459 switch (VA.getLocInfo()) {
460 default: assert(0 && "Unknown loc info!");
461 case CCValAssign::Full: break;
462 case CCValAssign::SExt:
463 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
465 case CCValAssign::ZExt:
466 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
468 case CCValAssign::AExt:
469 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
473 // Arguments that can be passed on register must be kept at
476 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
480 // Register cant get to this point...
481 assert(VA.isMemLoc());
483 // Create the frame index object for this incoming parameter
484 // This guarantees that when allocating Local Area the firsts
485 // 16 bytes which are alwayes reserved won't be overwritten
486 // if O32 ABI is used. For EABI the first address is zero.
487 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
488 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
491 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
493 // emit ISD::STORE whichs stores the
494 // parameter value to a stack Location
495 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
498 // Transform all store nodes into one single node because all store
499 // nodes are independent of each other.
500 if (!MemOpChains.empty())
501 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
502 &MemOpChains[0], MemOpChains.size());
504 // Build a sequence of copy-to-reg nodes chained together with token
505 // chain and flag operands which copy the outgoing args into registers.
506 // The InFlag in necessary since all emited instructions must be
509 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
510 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first,
511 RegsToPass[i].second, InFlag);
512 InFlag = Chain.getValue(1);
515 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
516 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
517 // node so that legalize doesn't hack it.
518 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
519 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
520 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
521 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
524 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
525 // = Chain, Callee, Reg#1, Reg#2, ...
527 // Returns a chain & a flag for retval copy to use.
528 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
529 SmallVector<SDValue, 8> Ops;
530 Ops.push_back(Chain);
531 Ops.push_back(Callee);
533 // Add argument registers to the end of the list so that they are
534 // known live into the call.
535 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
536 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
537 RegsToPass[i].second.getValueType()));
540 Ops.push_back(InFlag);
542 Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size());
543 InFlag = Chain.getValue(1);
545 // Create the CALLSEQ_END node.
546 Chain = DAG.getCALLSEQ_END(Chain,
547 DAG.getConstant(NumBytes, getPointerTy()),
548 DAG.getConstant(0, getPointerTy()),
550 InFlag = Chain.getValue(1);
552 // Create a stack location to hold GP when PIC is used. This stack
553 // location is used on function prologue to save GP and also after all
554 // emited CALL's to restore GP.
555 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
556 // Function can have an arbitrary number of calls, so
557 // hold the LastArgStackLoc with the biggest offset.
559 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
560 if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
561 LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
562 // Create the frame index only once. SPOffset here can be anything
563 // (this will be fixed on processFunctionBeforeFrameFinalized)
564 if (MipsFI->getGPStackOffset() == -1) {
565 FI = MFI->CreateFixedObject(4, 0);
568 MipsFI->setGPStackOffset(LastArgStackLoc);
572 FI = MipsFI->getGPFI();
573 SDValue FIN = DAG.getFrameIndex(FI,getPointerTy());
574 SDValue GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0);
575 Chain = GPLoad.getValue(1);
576 Chain = DAG.getCopyToReg(Chain, DAG.getRegister(Mips::GP, MVT::i32),
577 GPLoad, SDValue(0,0));
578 InFlag = Chain.getValue(1);
581 // Handle result values, copying them out of physregs into vregs that we
583 return SDValue(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
586 /// LowerCallResult - Lower the result values of an ISD::CALL into the
587 /// appropriate copies out of appropriate physical registers. This assumes that
588 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
589 /// being lowered. Returns a SDNode with the same number of values as the
591 SDNode *MipsTargetLowering::
592 LowerCallResult(SDValue Chain, SDValue InFlag, SDNode *TheCall,
593 unsigned CallingConv, SelectionDAG &DAG) {
595 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
597 // Assign locations to each value returned by this call.
598 SmallVector<CCValAssign, 16> RVLocs;
599 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
601 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
602 SmallVector<SDValue, 8> ResultVals;
604 // Copy all of the result registers out of their specified physreg.
605 for (unsigned i = 0; i != RVLocs.size(); ++i) {
606 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
607 RVLocs[i].getValVT(), InFlag).getValue(1);
608 InFlag = Chain.getValue(2);
609 ResultVals.push_back(Chain.getValue(0));
612 ResultVals.push_back(Chain);
614 // Merge everything together with a MERGE_VALUES node.
615 return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0],
616 ResultVals.size()).Val;
619 //===----------------------------------------------------------------------===//
620 // FORMAL_ARGUMENTS Calling Convention Implementation
621 //===----------------------------------------------------------------------===//
623 /// Mips custom FORMAL_ARGUMENTS implementation
624 SDValue MipsTargetLowering::
625 LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG)
627 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
631 assert(0 && "Unsupported calling convention");
633 return LowerCCCArguments(Op, DAG);
637 /// LowerCCCArguments - transform physical registers into
638 /// virtual registers and generate load operations for
639 /// arguments places on the stack.
641 SDValue MipsTargetLowering::
642 LowerCCCArguments(SDValue Op, SelectionDAG &DAG)
644 SDValue Root = Op.getOperand(0);
645 MachineFunction &MF = DAG.getMachineFunction();
646 MachineFrameInfo *MFI = MF.getFrameInfo();
647 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
649 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
650 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
652 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
654 // GP must be live into PIC and non-PIC call target.
655 AddLiveIn(MF, Mips::GP, Mips::CPURegsRegisterClass);
657 // Assign locations to all of the incoming arguments.
658 SmallVector<CCValAssign, 16> ArgLocs;
659 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
661 CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips);
662 SmallVector<SDValue, 16> ArgValues;
665 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
667 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
669 CCValAssign &VA = ArgLocs[i];
671 // Arguments stored on registers
673 MVT RegVT = VA.getLocVT();
674 TargetRegisterClass *RC = 0;
676 if (RegVT == MVT::i32)
677 RC = Mips::CPURegsRegisterClass;
678 else if (RegVT == MVT::f32) {
679 if (Subtarget->isSingleFloat())
680 RC = Mips::FGR32RegisterClass;
682 RC = Mips::AFGR32RegisterClass;
683 } else if (RegVT == MVT::f64) {
684 if (!Subtarget->isSingleFloat())
685 RC = Mips::AFGR64RegisterClass;
687 assert(0 && "RegVT not supported by FORMAL_ARGUMENTS Lowering");
689 // Transform the arguments stored on
690 // physical registers into virtual ones
691 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
692 SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
694 // If this is an 8 or 16-bit value, it is really passed promoted
695 // to 32 bits. Insert an assert[sz]ext to capture this, then
696 // truncate to the right size.
697 if (VA.getLocInfo() == CCValAssign::SExt)
698 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
699 DAG.getValueType(VA.getValVT()));
700 else if (VA.getLocInfo() == CCValAssign::ZExt)
701 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
702 DAG.getValueType(VA.getValVT()));
704 if (VA.getLocInfo() != CCValAssign::Full)
705 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
707 ArgValues.push_back(ArgValue);
709 // To meet ABI, when VARARGS are passed on registers, the registers
710 // must have their values written to the caller stack frame.
711 if ((isVarArg) && (Subtarget->isABI_O32())) {
712 if (StackPtr.Val == 0)
713 StackPtr = DAG.getRegister(StackReg, getPointerTy());
715 // The stack pointer offset is relative to the caller stack frame.
716 // Since the real stack size is unknown here, a negative SPOffset
717 // is used so there's a way to adjust these offsets when the stack
718 // size get known (on EliminateFrameIndex). A dummy SPOffset is
719 // used instead of a direct negative address (which is recorded to
720 // be used on emitPrologue) to avoid mis-calc of the first stack
721 // offset on PEI::calculateFrameObjectOffsets.
722 // Arguments are always 32-bit.
723 int FI = MFI->CreateFixedObject(4, 0);
724 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
725 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
727 // emit ISD::STORE whichs stores the
728 // parameter value to a stack Location
729 ArgValues.push_back(DAG.getStore(Root, ArgValue, PtrOff, NULL, 0));
732 } else { // VA.isRegLoc()
735 assert(VA.isMemLoc());
737 // The stack pointer offset is relative to the caller stack frame.
738 // Since the real stack size is unknown here, a negative SPOffset
739 // is used so there's a way to adjust these offsets when the stack
740 // size get known (on EliminateFrameIndex). A dummy SPOffset is
741 // used instead of a direct negative address (which is recorded to
742 // be used on emitPrologue) to avoid mis-calc of the first stack
743 // offset on PEI::calculateFrameObjectOffsets.
744 // Arguments are always 32-bit.
745 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
746 int FI = MFI->CreateFixedObject(ArgSize, 0);
747 MipsFI->recordLoadArgsFI(FI, -(ArgSize+
748 (FirstStackArgLoc + VA.getLocMemOffset())));
750 // Create load nodes to retrieve arguments from the stack
751 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
752 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
756 // The mips ABIs for returning structs by value requires that we copy
757 // the sret argument into $v0 for the return. Save the argument into
758 // a virtual register so that we can access it from the return points.
759 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
760 unsigned Reg = MipsFI->getSRetReturnReg();
762 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
763 MipsFI->setSRetReturnReg(Reg);
765 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
766 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root);
769 ArgValues.push_back(Root);
771 // Return the new list of results.
772 return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
773 ArgValues.size()).getValue(Op.ResNo);
776 //===----------------------------------------------------------------------===//
777 // Return Value Calling Convention Implementation
778 //===----------------------------------------------------------------------===//
780 SDValue MipsTargetLowering::
781 LowerRET(SDValue Op, SelectionDAG &DAG)
783 // CCValAssign - represent the assignment of
784 // the return value to a location
785 SmallVector<CCValAssign, 16> RVLocs;
786 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
787 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
789 // CCState - Info about the registers and stack slot.
790 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
792 // Analize return values of ISD::RET
793 CCInfo.AnalyzeReturn(Op.Val, RetCC_Mips);
795 // If this is the first return lowered for this function, add
796 // the regs to the liveout set for the function.
797 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
798 for (unsigned i = 0; i != RVLocs.size(); ++i)
799 if (RVLocs[i].isRegLoc())
800 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
803 // The chain is always operand #0
804 SDValue Chain = Op.getOperand(0);
807 // Copy the result values into the output registers.
808 for (unsigned i = 0; i != RVLocs.size(); ++i) {
809 CCValAssign &VA = RVLocs[i];
810 assert(VA.isRegLoc() && "Can only return in registers!");
812 // ISD::RET => ret chain, (regnum1,val1), ...
813 // So i*2+1 index only the regnums
814 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
816 // guarantee that all emitted copies are
817 // stuck together, avoiding something bad
818 Flag = Chain.getValue(1);
821 // The mips ABIs for returning structs by value requires that we copy
822 // the sret argument into $v0 for the return. We saved the argument into
823 // a virtual register in the entry block, so now we copy the value out
825 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
826 MachineFunction &MF = DAG.getMachineFunction();
827 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
828 unsigned Reg = MipsFI->getSRetReturnReg();
831 assert(0 && "sret virtual register not created in the entry block");
832 SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
834 Chain = DAG.getCopyToReg(Chain, Mips::V0, Val, Flag);
835 Flag = Chain.getValue(1);
838 // Return on Mips is always a "jr $ra"
840 return DAG.getNode(MipsISD::Ret, MVT::Other,
841 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
843 return DAG.getNode(MipsISD::Ret, MVT::Other,
844 Chain, DAG.getRegister(Mips::RA, MVT::i32));
847 //===----------------------------------------------------------------------===//
848 // Mips Inline Assembly Support
849 //===----------------------------------------------------------------------===//
851 /// getConstraintType - Given a constraint letter, return the type of
852 /// constraint it is for this target.
853 MipsTargetLowering::ConstraintType MipsTargetLowering::
854 getConstraintType(const std::string &Constraint) const
856 // Mips specific constrainy
857 // GCC config/mips/constraints.md
859 // 'd' : An address register. Equivalent to r
860 // unless generating MIPS16 code.
861 // 'y' : Equivalent to r; retained for
862 // backwards compatibility.
863 // 'f' : Floating Point registers.
864 if (Constraint.size() == 1) {
865 switch (Constraint[0]) {
870 return C_RegisterClass;
874 return TargetLowering::getConstraintType(Constraint);
877 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
878 /// return a list of registers that can be used to satisfy the constraint.
879 /// This should only be used for C_RegisterClass constraints.
880 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
881 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
883 if (Constraint.size() == 1) {
884 switch (Constraint[0]) {
886 return std::make_pair(0U, Mips::CPURegsRegisterClass);
888 if (VT == MVT::f32) {
889 if (Subtarget->isSingleFloat())
890 return std::make_pair(0U, Mips::FGR32RegisterClass);
892 return std::make_pair(0U, Mips::AFGR32RegisterClass);
895 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
896 return std::make_pair(0U, Mips::AFGR64RegisterClass);
899 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
902 /// Given a register class constraint, like 'r', if this corresponds directly
903 /// to an LLVM register class, return a register of 0 and the register class
905 std::vector<unsigned> MipsTargetLowering::
906 getRegClassForInlineAsmConstraint(const std::string &Constraint,
909 if (Constraint.size() != 1)
910 return std::vector<unsigned>();
912 switch (Constraint[0]) {
915 // GCC Mips Constraint Letters
918 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
919 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
920 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
924 if (VT == MVT::f32) {
925 if (Subtarget->isSingleFloat())
926 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
927 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
928 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
929 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
930 Mips::F30, Mips::F31, 0);
932 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
933 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
934 Mips::F28, Mips::F30, 0);
938 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
939 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
940 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
941 Mips::D14, Mips::D15, 0);
943 return std::vector<unsigned>();