1 //===-- MipsFrameLowering.cpp - Mips Frame Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsFrameLowering.h"
15 #include "MipsAnalyzeImmediate.h"
16 #include "MipsInstrInfo.h"
17 #include "MipsMachineFunction.h"
18 #include "MCTargetDesc/MipsBaseInfo.h"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineModuleInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/Target/TargetData.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Support/CommandLine.h"
32 //===----------------------------------------------------------------------===//
34 // Stack Frame Processing methods
35 // +----------------------------+
37 // The stack is allocated decrementing the stack pointer on
38 // the first instruction of a function prologue. Once decremented,
39 // all stack references are done thought a positive offset
40 // from the stack/frame pointer, so the stack is considering
41 // to grow up! Otherwise terrible hacks would have to be made
42 // to get this stack ABI compliant :)
44 // The stack frame required by the ABI (after call):
49 // . saved $GP (used in PIC)
50 // . Alloca allocations
52 // . CPU "Callee Saved" Registers
55 // . FPU "Callee Saved" Registers
56 // StackSize -----------
58 // Offset - offset from sp after stack allocation on function prologue
60 // The sp is the stack pointer subtracted/added from the stack size
61 // at the Prologue/Epilogue
63 // References to the previous stack (to obtain arguments) are done
64 // with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1))
67 // - reference to the actual stack frame
68 // for any local area var there is smt like : FI >= 0, StackOffset: 4
71 // - reference to previous stack frame
72 // suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16.
73 // The emitted instruction will be something like:
74 // lw REGX, 16+StackSize(SP)
76 // Since the total stack size is unknown on LowerFormalArguments, all
77 // stack references (ObjectOffset) created to reference the function
78 // arguments, are negative numbers. This way, on eliminateFrameIndex it's
79 // possible to detect those references and the offsets are adjusted to
80 // their real location.
82 //===----------------------------------------------------------------------===//
84 // hasFP - Return true if the specified function should have a dedicated frame
85 // pointer register. This is true if the function has variable sized allocas or
86 // if frame pointer elimination is disabled.
87 bool MipsFrameLowering::hasFP(const MachineFunction &MF) const {
88 const MachineFrameInfo *MFI = MF.getFrameInfo();
89 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
90 MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
93 bool MipsFrameLowering::targetHandlesStackFrameRounding() const {
97 void MipsFrameLowering::emitPrologue(MachineFunction &MF) const {
98 MachineBasicBlock &MBB = MF.front();
99 MachineFrameInfo *MFI = MF.getFrameInfo();
100 const MipsRegisterInfo *RegInfo =
101 static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
102 const MipsInstrInfo &TII =
103 *static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo());
104 MachineBasicBlock::iterator MBBI = MBB.begin();
105 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
106 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
107 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
108 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
109 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
110 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
112 // First, compute final stack size.
113 unsigned StackAlign = getStackAlignment();
114 uint64_t StackSize = RoundUpToAlignment(MFI->getStackSize(), StackAlign);
115 StackSize += RoundUpToAlignment(MFI->getMaxCallFrameSize(), StackAlign);
118 MFI->setStackSize(StackSize);
120 // No need to allocate space on the stack.
121 if (StackSize == 0 && !MFI->adjustsStack()) return;
123 MachineModuleInfo &MMI = MF.getMMI();
124 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
125 MachineLocation DstML, SrcML;
128 if (isInt<16>(-StackSize)) {// addi sp, sp, (-stacksize)
129 if (STI.inMips16Mode())
130 BuildMI(MBB, MBBI, dl,
131 TII.get(Mips::SaveRaF16)).addImm(StackSize); // cleanup
133 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(SP).addImm(-StackSize);
135 else { // Expand immediate that doesn't fit in 16-bit.
136 unsigned ATReg = STI.isABI_N64() ? Mips::AT_64 : Mips::AT;
138 MF.getInfo<MipsFunctionInfo>()->setEmitNOAT();
139 Mips::loadImmediate(-StackSize, STI.isABI_N64(), TII, MBB, MBBI, dl, false,
141 BuildMI(MBB, MBBI, dl, TII.get(ADDu), SP).addReg(SP).addReg(ATReg);
144 // emit ".cfi_def_cfa_offset StackSize"
145 MCSymbol *AdjustSPLabel = MMI.getContext().CreateTempSymbol();
146 BuildMI(MBB, MBBI, dl,
147 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel);
148 DstML = MachineLocation(MachineLocation::VirtualFP);
149 SrcML = MachineLocation(MachineLocation::VirtualFP, -StackSize);
150 Moves.push_back(MachineMove(AdjustSPLabel, DstML, SrcML));
152 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
155 // Find the instruction past the last instruction that saves a callee-saved
156 // register to the stack.
157 for (unsigned i = 0; i < CSI.size(); ++i)
160 // Iterate over list of callee-saved registers and emit .cfi_offset
162 MCSymbol *CSLabel = MMI.getContext().CreateTempSymbol();
163 BuildMI(MBB, MBBI, dl,
164 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel);
166 for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
167 E = CSI.end(); I != E; ++I) {
168 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
169 unsigned Reg = I->getReg();
171 // If Reg is a double precision register, emit two cfa_offsets,
172 // one for each of the paired single precision registers.
173 if (Mips::AFGR64RegClass.contains(Reg)) {
174 MachineLocation DstML0(MachineLocation::VirtualFP, Offset);
175 MachineLocation DstML1(MachineLocation::VirtualFP, Offset + 4);
176 MachineLocation SrcML0(RegInfo->getSubReg(Reg, Mips::sub_fpeven));
177 MachineLocation SrcML1(RegInfo->getSubReg(Reg, Mips::sub_fpodd));
180 std::swap(SrcML0, SrcML1);
182 Moves.push_back(MachineMove(CSLabel, DstML0, SrcML0));
183 Moves.push_back(MachineMove(CSLabel, DstML1, SrcML1));
185 // Reg is either in CPURegs or FGR32.
186 DstML = MachineLocation(MachineLocation::VirtualFP, Offset);
187 SrcML = MachineLocation(Reg);
188 Moves.push_back(MachineMove(CSLabel, DstML, SrcML));
193 // if framepointer enabled, set it to point to the stack pointer.
195 // Insert instruction "move $fp, $sp" at this location.
196 BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO);
198 // emit ".cfi_def_cfa_register $fp"
199 MCSymbol *SetFPLabel = MMI.getContext().CreateTempSymbol();
200 BuildMI(MBB, MBBI, dl,
201 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel);
202 DstML = MachineLocation(FP);
203 SrcML = MachineLocation(MachineLocation::VirtualFP);
204 Moves.push_back(MachineMove(SetFPLabel, DstML, SrcML));
208 void MipsFrameLowering::emitEpilogue(MachineFunction &MF,
209 MachineBasicBlock &MBB) const {
210 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
211 MachineFrameInfo *MFI = MF.getFrameInfo();
212 const MipsInstrInfo &TII =
213 *static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo());
214 DebugLoc dl = MBBI->getDebugLoc();
215 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
216 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
217 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
218 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
219 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
221 // if framepointer enabled, restore the stack pointer.
223 // Find the first instruction that restores a callee-saved register.
224 MachineBasicBlock::iterator I = MBBI;
226 for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i)
229 // Insert instruction "move $sp, $fp" at this location.
230 BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO);
233 // Get the number of bytes from FrameInfo
234 uint64_t StackSize = MFI->getStackSize();
240 if (isInt<16>(StackSize)) { // addi sp, sp, (-stacksize)
241 if (STI.inMips16Mode())
242 // assumes stacksize multiple of 8
243 BuildMI(MBB, MBBI, dl,
244 TII.get(Mips::RestoreRaF16)).addImm(StackSize);
246 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(SP).addImm(StackSize);
248 else { // Expand immediate that doesn't fit in 16-bit.
249 unsigned ATReg = STI.isABI_N64() ? Mips::AT_64 : Mips::AT;
251 MF.getInfo<MipsFunctionInfo>()->setEmitNOAT();
252 Mips::loadImmediate(StackSize, STI.isABI_N64(), TII, MBB, MBBI, dl, false,
254 BuildMI(MBB, MBBI, dl, TII.get(ADDu), SP).addReg(SP).addReg(ATReg);
258 void MipsFrameLowering::
259 processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
260 RegScavenger *RS) const {
261 MachineRegisterInfo &MRI = MF.getRegInfo();
262 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
264 // FIXME: remove this code if register allocator can correctly mark
265 // $fp and $ra used or unused.
267 // Mark $fp and $ra as used or unused.
269 MRI.setPhysRegUsed(FP);
272 bool MipsFrameLowering::
273 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
274 MachineBasicBlock::iterator MI,
275 const std::vector<CalleeSavedInfo> &CSI,
276 const TargetRegisterInfo *TRI) const {
277 MachineFunction *MF = MBB.getParent();
278 MachineBasicBlock *EntryBlock = MF->begin();
279 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
281 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
282 // Add the callee-saved register as live-in. Do not add if the register is
283 // RA and return address is taken, because it has already been added in
284 // method MipsTargetLowering::LowerRETURNADDR.
285 // It's killed at the spill, unless the register is RA and return address
287 unsigned Reg = CSI[i].getReg();
288 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64)
289 && MF->getFrameInfo()->isReturnAddressTaken();
290 if (!IsRAAndRetAddrIsTaken)
291 EntryBlock->addLiveIn(Reg);
293 // Insert the spill to the stack frame.
294 bool IsKill = !IsRAAndRetAddrIsTaken;
295 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
296 TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill,
297 CSI[i].getFrameIdx(), RC, TRI);