1 //=======- MipsFrameLowering.cpp - Mips Frame Information ------*- C++ -*-====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsFrameLowering.h"
15 #include "MipsInstrInfo.h"
16 #include "MipsMachineFunction.h"
17 #include "llvm/Function.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Target/TargetData.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Support/CommandLine.h"
30 //===----------------------------------------------------------------------===//
32 // Stack Frame Processing methods
33 // +----------------------------+
35 // The stack is allocated decrementing the stack pointer on
36 // the first instruction of a function prologue. Once decremented,
37 // all stack references are done thought a positive offset
38 // from the stack/frame pointer, so the stack is considering
39 // to grow up! Otherwise terrible hacks would have to be made
40 // to get this stack ABI compliant :)
42 // The stack frame required by the ABI (after call):
47 // . saved $GP (used in PIC)
48 // . Alloca allocations
50 // . CPU "Callee Saved" Registers
53 // . FPU "Callee Saved" Registers
54 // StackSize -----------
56 // Offset - offset from sp after stack allocation on function prologue
58 // The sp is the stack pointer subtracted/added from the stack size
59 // at the Prologue/Epilogue
61 // References to the previous stack (to obtain arguments) are done
62 // with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1))
65 // - reference to the actual stack frame
66 // for any local area var there is smt like : FI >= 0, StackOffset: 4
69 // - reference to previous stack frame
70 // suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16.
71 // The emitted instruction will be something like:
72 // lw REGX, 16+StackSize(SP)
74 // Since the total stack size is unknown on LowerFormalArguments, all
75 // stack references (ObjectOffset) created to reference the function
76 // arguments, are negative numbers. This way, on eliminateFrameIndex it's
77 // possible to detect those references and the offsets are adjusted to
78 // their real location.
80 //===----------------------------------------------------------------------===//
82 // hasFP - Return true if the specified function should have a dedicated frame
83 // pointer register. This is true if the function has variable sized allocas or
84 // if frame pointer elimination is disabled.
85 bool MipsFrameLowering::hasFP(const MachineFunction &MF) const {
86 const MachineFrameInfo *MFI = MF.getFrameInfo();
87 return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects();
90 void MipsFrameLowering::adjustMipsStackFrame(MachineFunction &MF) const {
91 MachineFrameInfo *MFI = MF.getFrameInfo();
92 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
93 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
94 unsigned StackAlign = getStackAlignment();
95 unsigned RegSize = STI.isGP32bit() ? 4 : 8;
96 bool HasGP = MipsFI->needGPSaveRestore();
98 // Min and Max CSI FrameIndex.
99 int MinCSFI = -1, MaxCSFI = -1;
101 // See the description at MipsMachineFunction.h
102 int TopCPUSavedRegOff = -1, TopFPUSavedRegOff = -1;
104 // Replace the dummy '0' SPOffset by the negative offsets, as explained on
105 // LowerFormalArguments. Leaving '0' for while is necessary to avoid the
106 // approach done by calculateFrameObjectOffsets to the stack frame.
107 MipsFI->adjustLoadArgsFI(MFI);
108 MipsFI->adjustStoreVarArgsFI(MFI);
110 // It happens that the default stack frame allocation order does not directly
111 // map to the convention used for mips. So we must fix it. We move the callee
112 // save register slots after the local variables area, as described in the
113 // stack frame above.
114 unsigned CalleeSavedAreaSize = 0;
116 MinCSFI = CSI[0].getFrameIdx();
117 MaxCSFI = CSI[CSI.size()-1].getFrameIdx();
119 for (unsigned i = 0, e = CSI.size(); i != e; ++i)
120 CalleeSavedAreaSize += MFI->getObjectAlignment(CSI[i].getFrameIdx());
122 unsigned StackOffset = HasGP ? (MipsFI->getGPStackOffset()+RegSize)
123 : (STI.isABI_O32() ? 16 : 0);
125 // Adjust local variables. They should come on the stack right
126 // after the arguments.
127 int LastOffsetFI = -1;
128 for (int i = 0, e = MFI->getObjectIndexEnd(); i != e; ++i) {
129 if (i >= MinCSFI && i <= MaxCSFI)
131 if (MFI->isDeadObjectIndex(i))
134 StackOffset + MFI->getObjectOffset(i) - CalleeSavedAreaSize;
135 if (LastOffsetFI == -1)
137 if (Offset > MFI->getObjectOffset(LastOffsetFI))
139 MFI->setObjectOffset(i, Offset);
142 // Adjust CPU Callee Saved Registers Area. Registers RA and FP must
143 // be saved in this CPU Area. This whole area must be aligned to the
144 // default Stack Alignment requirements.
145 if (LastOffsetFI >= 0)
146 StackOffset = MFI->getObjectOffset(LastOffsetFI)+
147 MFI->getObjectSize(LastOffsetFI);
148 StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
150 for (unsigned i = 0, e = CSI.size(); i != e ; ++i) {
151 unsigned Reg = CSI[i].getReg();
152 if (!Mips::CPURegsRegisterClass->contains(Reg))
154 MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset);
155 TopCPUSavedRegOff = StackOffset;
156 StackOffset += MFI->getObjectAlignment(CSI[i].getFrameIdx());
159 StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
161 // Adjust FPU Callee Saved Registers Area. This Area must be
162 // aligned to the default Stack Alignment requirements.
163 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
164 unsigned Reg = CSI[i].getReg();
165 if (Mips::CPURegsRegisterClass->contains(Reg))
167 MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset);
168 TopFPUSavedRegOff = StackOffset;
169 StackOffset += MFI->getObjectAlignment(CSI[i].getFrameIdx());
171 StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
174 MFI->setStackSize(StackOffset);
176 // Recalculate the final tops offset. The final values must be '0'
177 // if there isn't a callee saved register for CPU or FPU, otherwise
178 // a negative offset is needed.
179 if (TopCPUSavedRegOff >= 0)
180 MipsFI->setCPUTopSavedRegOff(TopCPUSavedRegOff-StackOffset);
182 if (TopFPUSavedRegOff >= 0)
183 MipsFI->setFPUTopSavedRegOff(TopFPUSavedRegOff-StackOffset);
187 // expand pair of register and immediate if the immediate doesn't fit in the
188 // 16-bit offset field.
190 // if OrigImm = 0x10000, OrigReg = $sp:
191 // generate the following sequence of instrs:
192 // lui $at, hi(0x10000)
193 // addu $at, $sp, $at
195 // (NewReg, NewImm) = ($at, lo(Ox10000))
197 static bool expandRegLargeImmPair(unsigned OrigReg, int OrigImm,
198 unsigned& NewReg, int& NewImm,
199 MachineBasicBlock& MBB,
200 MachineBasicBlock::iterator I) {
201 // OrigImm fits in the 16-bit field
202 if (OrigImm < 0x8000 && OrigImm >= -0x8000) {
208 MachineFunction* MF = MBB.getParent();
209 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
210 DebugLoc DL = I->getDebugLoc();
211 int ImmLo = OrigImm & 0xffff;
212 int ImmHi = (((unsigned)OrigImm & 0xffff0000) >> 16) +
213 ((OrigImm & 0x8000) != 0);
215 // FIXME: change this when mips goes MC".
216 BuildMI(MBB, I, DL, TII->get(Mips::NOAT));
217 BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::AT).addImm(ImmHi);
218 BuildMI(MBB, I, DL, TII->get(Mips::ADDu), Mips::AT).addReg(OrigReg)
226 void MipsFrameLowering::emitPrologue(MachineFunction &MF) const {
227 MachineBasicBlock &MBB = MF.front();
228 MachineFrameInfo *MFI = MF.getFrameInfo();
229 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
230 const MipsRegisterInfo *RegInfo =
231 static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
232 const MipsInstrInfo &TII =
233 *static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo());
234 MachineBasicBlock::iterator MBBI = MBB.begin();
235 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
236 bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_);
241 // Get the right frame order for Mips.
242 adjustMipsStackFrame(MF);
244 // Get the number of bytes to allocate from the FrameInfo.
245 unsigned StackSize = MFI->getStackSize();
247 // No need to allocate space on the stack.
248 if (StackSize == 0 && !MFI->adjustsStack()) return;
250 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOREORDER));
252 // TODO: check need from GP here.
253 if (isPIC && STI.isABI_O32())
254 BuildMI(MBB, MBBI, dl, TII.get(Mips::CPLOAD))
255 .addReg(RegInfo->getPICCallReg());
256 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO));
258 // Adjust stack : addi sp, sp, (-imm)
259 ATUsed = expandRegLargeImmPair(Mips::SP, -StackSize, NewReg, NewImm, MBB,
261 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP)
262 .addReg(NewReg).addImm(NewImm);
264 // FIXME: change this when mips goes MC".
266 BuildMI(MBB, MBBI, dl, TII.get(Mips::ATMACRO));
268 // if framepointer enabled, set it to point to the stack pointer.
271 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::FP)
272 .addReg(Mips::SP).addReg(Mips::ZERO);
274 // Restore GP from the saved stack location
275 if (MipsFI->needGPSaveRestore())
276 BuildMI(MBB, MBBI, dl, TII.get(Mips::CPRESTORE))
277 .addImm(MipsFI->getGPStackOffset());
280 void MipsFrameLowering::emitEpilogue(MachineFunction &MF,
281 MachineBasicBlock &MBB) const {
282 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
283 MachineFrameInfo *MFI = MF.getFrameInfo();
284 const MipsInstrInfo &TII =
285 *static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo());
286 DebugLoc dl = MBBI->getDebugLoc();
288 // Get the number of bytes from FrameInfo
289 int NumBytes = (int) MFI->getStackSize();
295 // if framepointer enabled, restore the stack pointer.
298 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::SP)
299 .addReg(Mips::FP).addReg(Mips::ZERO);
301 // adjust stack : insert addi sp, sp, (imm)
303 ATUsed = expandRegLargeImmPair(Mips::SP, NumBytes, NewReg, NewImm, MBB,
305 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP)
306 .addReg(NewReg).addImm(NewImm);
308 // FIXME: change this when mips goes MC".
310 BuildMI(MBB, MBBI, dl, TII.get(Mips::ATMACRO));
314 void MipsFrameLowering::
315 processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
316 RegScavenger *RS) const {
317 MachineRegisterInfo& MRI = MF.getRegInfo();
318 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
320 // FIXME: remove this code if register allocator can correctly mark
321 // $fp and $ra used or unused.
323 // Mark $fp and $ra as used or unused.
325 MRI.setPhysRegUsed(Mips::FP);
327 // The register allocator might determine $ra is used after seeing
328 // instruction "jr $ra", but we do not want PrologEpilogInserter to insert
329 // instructions to save/restore $ra unless there is a function call.
330 // To correct this, $ra is explicitly marked unused if there is no
332 if (MipsFI->hasCall())
333 MRI.setPhysRegUsed(Mips::RA);
335 MRI.setPhysRegUnused(Mips::RA);
338 void MipsFrameLowering::
339 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
340 const MipsRegisterInfo *RegInfo =
341 static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
342 RegInfo->processFunctionBeforeFrameFinalized(MF);