1 //===-- MipsastISel.cpp - Mips FastISel implementation
2 //---------------------===//
4 #include "llvm/CodeGen/FunctionLoweringInfo.h"
5 #include "llvm/CodeGen/FastISel.h"
6 #include "llvm/CodeGen/MachineInstrBuilder.h"
7 #include "llvm/IR/GlobalAlias.h"
8 #include "llvm/IR/GlobalVariable.h"
9 #include "llvm/Target/TargetInstrInfo.h"
10 #include "llvm/Target/TargetLibraryInfo.h"
11 #include "MipsRegisterInfo.h"
12 #include "MipsISelLowering.h"
13 #include "MipsMachineFunction.h"
14 #include "MipsSubtarget.h"
15 #include "MipsTargetMachine.h"
21 // All possible address modes.
22 typedef struct Address {
23 enum { RegBase, FrameIndexBase } BaseType;
32 // Innocuous defaults for our address.
33 Address() : BaseType(RegBase), Offset(0) { Base.Reg = 0; }
36 class MipsFastISel final : public FastISel {
38 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
39 /// make the right decision when generating code for different targets.
41 const TargetMachine &TM;
42 const TargetInstrInfo &TII;
43 const TargetLowering &TLI;
44 const MipsSubtarget *Subtarget;
45 MipsFunctionInfo *MFI;
47 // Convenience variables to avoid some queries.
53 explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
54 const TargetLibraryInfo *libInfo)
55 : FastISel(funcInfo, libInfo),
56 M(const_cast<Module &>(*funcInfo.Fn->getParent())),
57 TM(funcInfo.MF->getTarget()),
58 TII(*TM.getSubtargetImpl()->getInstrInfo()),
59 TLI(*TM.getSubtargetImpl()->getTargetLowering()),
60 Subtarget(&TM.getSubtarget<MipsSubtarget>()) {
61 MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
62 Context = &funcInfo.Fn->getContext();
63 TargetSupported = ((Subtarget->getRelocationModel() == Reloc::PIC_) &&
64 ((Subtarget->hasMips32r2() || Subtarget->hasMips32()) &&
65 (Subtarget->isABI_O32())));
68 bool fastSelectInstruction(const Instruction *I) override;
69 unsigned fastMaterializeConstant(const Constant *C) override;
71 bool ComputeAddress(const Value *Obj, Address &Addr);
74 bool EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
75 unsigned Alignment = 0);
76 bool EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
77 unsigned Alignment = 0);
78 bool SelectLoad(const Instruction *I);
79 bool SelectRet(const Instruction *I);
80 bool SelectStore(const Instruction *I);
81 bool SelectIntExt(const Instruction *I);
82 bool SelectTrunc(const Instruction *I);
83 bool SelectFPExt(const Instruction *I);
84 bool SelectFPTrunc(const Instruction *I);
86 bool isTypeLegal(Type *Ty, MVT &VT);
87 bool isLoadTypeLegal(Type *Ty, MVT &VT);
89 unsigned MaterializeFP(const ConstantFP *CFP, MVT VT);
90 unsigned MaterializeGV(const GlobalValue *GV, MVT VT);
91 unsigned MaterializeInt(const Constant *C, MVT VT);
92 unsigned Materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
94 bool EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
97 bool EmitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
99 bool EmitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
100 bool EmitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
102 bool EmitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
104 // for some reason, this default is not generated by tablegen
105 // so we explicitly generate it here.
107 unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
108 unsigned Op0, bool Op0IsKill, uint64_t imm1,
109 uint64_t imm2, unsigned Op3, bool Op3IsKill) {
113 MachineInstrBuilder EmitInst(unsigned Opc) {
114 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
117 MachineInstrBuilder EmitInst(unsigned Opc, unsigned DstReg) {
118 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
122 MachineInstrBuilder EmitInstStore(unsigned Opc, unsigned SrcReg,
123 unsigned MemReg, int64_t MemOffset) {
124 return EmitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
127 MachineInstrBuilder EmitInstLoad(unsigned Opc, unsigned DstReg,
128 unsigned MemReg, int64_t MemOffset) {
129 return EmitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
132 #include "MipsGenFastISel.inc"
135 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
136 EVT evt = TLI.getValueType(Ty, true);
137 // Only handle simple types.
138 if (evt == MVT::Other || !evt.isSimple())
140 VT = evt.getSimpleVT();
142 // Handle all legal types, i.e. a register that will directly hold this
144 return TLI.isTypeLegal(VT);
147 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
148 if (isTypeLegal(Ty, VT))
150 // We will extend this in a later patch:
151 // If this is a type than can be sign or zero-extended to a basic operation
152 // go ahead and accept it now.
153 if (VT == MVT::i8 || VT == MVT::i16)
158 bool MipsFastISel::ComputeAddress(const Value *Obj, Address &Addr) {
159 // This construct looks a big awkward but it is how other ports handle this
160 // and as this function is more fully completed, these cases which
161 // return false will have additional code in them.
163 if (isa<Instruction>(Obj))
165 else if (isa<ConstantExpr>(Obj))
167 Addr.Base.Reg = getRegForValue(Obj);
168 return Addr.Base.Reg != 0;
171 bool MipsFastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
172 unsigned Alignment) {
174 // more cases will be handled here in following patches.
177 switch (VT.SimpleTy) {
179 ResultReg = createResultReg(&Mips::GPR32RegClass);
184 ResultReg = createResultReg(&Mips::GPR32RegClass);
189 ResultReg = createResultReg(&Mips::GPR32RegClass);
194 ResultReg = createResultReg(&Mips::FGR32RegClass);
199 ResultReg = createResultReg(&Mips::AFGR64RegClass);
206 EmitInstLoad(Opc, ResultReg, Addr.Base.Reg, Addr.Offset);
210 // Materialize a constant into a register, and return the register
211 // number (or zero if we failed to handle it).
212 unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
213 EVT CEVT = TLI.getValueType(C->getType(), true);
215 // Only handle simple types.
216 if (!CEVT.isSimple())
218 MVT VT = CEVT.getSimpleVT();
220 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
221 return MaterializeFP(CFP, VT);
222 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
223 return MaterializeGV(GV, VT);
224 else if (isa<ConstantInt>(C))
225 return MaterializeInt(C, VT);
230 bool MipsFastISel::EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
231 unsigned Alignment) {
233 // more cases will be handled here in following patches.
236 switch (VT.SimpleTy) {
255 EmitInstStore(Opc, SrcReg, Addr.Base.Reg, Addr.Offset);
259 bool MipsFastISel::EmitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
262 switch (SrcVT.SimpleTy) {
272 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
273 EmitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
274 EmitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
278 bool MipsFastISel::EmitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
280 switch (SrcVT.SimpleTy) {
284 EmitInst(Mips::SEB, DestReg).addReg(SrcReg);
287 EmitInst(Mips::SEH, DestReg).addReg(SrcReg);
293 bool MipsFastISel::EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
294 unsigned DestReg, bool IsZExt) {
296 return EmitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
297 return EmitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
300 bool MipsFastISel::EmitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
302 if ((DestVT != MVT::i32) && (DestVT != MVT::i16))
304 if (Subtarget->hasMips32r2())
305 return EmitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
306 return EmitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
309 bool MipsFastISel::EmitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
311 switch (SrcVT.SimpleTy) {
315 EmitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(1);
318 EmitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xff);
321 EmitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xffff);
327 bool MipsFastISel::SelectLoad(const Instruction *I) {
328 // Atomic loads need special handling.
329 if (cast<LoadInst>(I)->isAtomic())
332 // Verify we have a legal type before going any further.
334 if (!isLoadTypeLegal(I->getType(), VT))
337 // See if we can handle this address.
339 if (!ComputeAddress(I->getOperand(0), Addr))
343 if (!EmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
345 updateValueMap(I, ResultReg);
349 bool MipsFastISel::SelectStore(const Instruction *I) {
350 Value *Op0 = I->getOperand(0);
353 // Atomic stores need special handling.
354 if (cast<StoreInst>(I)->isAtomic())
357 // Verify we have a legal type before going any further.
359 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
362 // Get the value to be stored into a register.
363 SrcReg = getRegForValue(Op0);
367 // See if we can handle this address.
369 if (!ComputeAddress(I->getOperand(1), Addr))
372 if (!EmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
377 bool MipsFastISel::SelectRet(const Instruction *I) {
378 const ReturnInst *Ret = cast<ReturnInst>(I);
380 if (!FuncInfo.CanLowerReturn)
382 if (Ret->getNumOperands() > 0) {
385 EmitInst(Mips::RetRA);
389 // Attempt to fast-select a floating-point extend instruction.
390 bool MipsFastISel::SelectFPExt(const Instruction *I) {
391 Value *Src = I->getOperand(0);
392 EVT SrcVT = TLI.getValueType(Src->getType(), true);
393 EVT DestVT = TLI.getValueType(I->getType(), true);
395 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
399 getRegForValue(Src); // his must be a 32 bit floating point register class
400 // maybe we should handle this differently
404 unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
405 EmitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
406 updateValueMap(I, DestReg);
410 // Attempt to fast-select a floating-point truncate instruction.
411 bool MipsFastISel::SelectFPTrunc(const Instruction *I) {
412 Value *Src = I->getOperand(0);
413 EVT SrcVT = TLI.getValueType(Src->getType(), true);
414 EVT DestVT = TLI.getValueType(I->getType(), true);
416 if (SrcVT != MVT::f64 || DestVT != MVT::f32)
419 unsigned SrcReg = getRegForValue(Src);
423 unsigned DestReg = createResultReg(&Mips::FGR32RegClass);
427 EmitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
428 updateValueMap(I, DestReg);
432 bool MipsFastISel::SelectIntExt(const Instruction *I) {
433 Type *DestTy = I->getType();
434 Value *Src = I->getOperand(0);
435 Type *SrcTy = Src->getType();
437 bool isZExt = isa<ZExtInst>(I);
438 unsigned SrcReg = getRegForValue(Src);
443 SrcEVT = TLI.getValueType(SrcTy, true);
444 DestEVT = TLI.getValueType(DestTy, true);
445 if (!SrcEVT.isSimple())
447 if (!DestEVT.isSimple())
450 MVT SrcVT = SrcEVT.getSimpleVT();
451 MVT DestVT = DestEVT.getSimpleVT();
452 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
454 if (!EmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))
456 updateValueMap(I, ResultReg);
460 bool MipsFastISel::SelectTrunc(const Instruction *I) {
461 // The high bits for a type smaller than the register size are assumed to be
463 Value *Op = I->getOperand(0);
466 SrcVT = TLI.getValueType(Op->getType(), true);
467 DestVT = TLI.getValueType(I->getType(), true);
469 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
471 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
474 unsigned SrcReg = getRegForValue(Op);
478 // Because the high bits are undefined, a truncate doesn't generate
480 updateValueMap(I, SrcReg);
484 bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
485 if (!TargetSupported)
487 switch (I->getOpcode()) {
490 case Instruction::Load:
491 return SelectLoad(I);
492 case Instruction::Store:
493 return SelectStore(I);
494 case Instruction::Ret:
496 case Instruction::Trunc:
497 return SelectTrunc(I);
498 case Instruction::ZExt:
499 case Instruction::SExt:
500 return SelectIntExt(I);
501 case Instruction::FPTrunc:
502 return SelectFPTrunc(I);
503 case Instruction::FPExt:
504 return SelectFPExt(I);
509 unsigned MipsFastISel::MaterializeFP(const ConstantFP *CFP, MVT VT) {
510 int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
511 if (VT == MVT::f32) {
512 const TargetRegisterClass *RC = &Mips::FGR32RegClass;
513 unsigned DestReg = createResultReg(RC);
514 unsigned TempReg = Materialize32BitInt(Imm, &Mips::GPR32RegClass);
515 EmitInst(Mips::MTC1, DestReg).addReg(TempReg);
517 } else if (VT == MVT::f64) {
518 const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
519 unsigned DestReg = createResultReg(RC);
520 unsigned TempReg1 = Materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
522 Materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
523 EmitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
529 unsigned MipsFastISel::MaterializeGV(const GlobalValue *GV, MVT VT) {
530 // For now 32-bit only.
533 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
534 unsigned DestReg = createResultReg(RC);
535 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
536 bool IsThreadLocal = GVar && GVar->isThreadLocal();
537 // TLS not supported at this time.
540 EmitInst(Mips::LW, DestReg)
541 .addReg(MFI->getGlobalBaseReg())
542 .addGlobalAddress(GV, 0, MipsII::MO_GOT);
543 if ((GV->hasInternalLinkage() ||
544 (GV->hasLocalLinkage() && !isa<Function>(GV)))) {
545 unsigned TempReg = createResultReg(RC);
546 EmitInst(Mips::ADDiu, TempReg)
548 .addGlobalAddress(GV, 0, MipsII::MO_ABS_LO);
554 unsigned MipsFastISel::MaterializeInt(const Constant *C, MVT VT) {
555 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
557 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
558 const ConstantInt *CI = cast<ConstantInt>(C);
560 if ((VT != MVT::i1) && CI->isNegative())
561 Imm = CI->getSExtValue();
563 Imm = CI->getZExtValue();
564 return Materialize32BitInt(Imm, RC);
567 unsigned MipsFastISel::Materialize32BitInt(int64_t Imm,
568 const TargetRegisterClass *RC) {
569 unsigned ResultReg = createResultReg(RC);
571 if (isInt<16>(Imm)) {
572 unsigned Opc = Mips::ADDiu;
573 EmitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
575 } else if (isUInt<16>(Imm)) {
576 EmitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
579 unsigned Lo = Imm & 0xFFFF;
580 unsigned Hi = (Imm >> 16) & 0xFFFF;
582 // Both Lo and Hi have nonzero bits.
583 unsigned TmpReg = createResultReg(RC);
584 EmitInst(Mips::LUi, TmpReg).addImm(Hi);
585 EmitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
587 EmitInst(Mips::LUi, ResultReg).addImm(Hi);
594 FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
595 const TargetLibraryInfo *libInfo) {
596 return new MipsFastISel(funcInfo, libInfo);