1 //===-- MipsastISel.cpp - Mips FastISel implementation
2 //---------------------===//
4 #include "llvm/CodeGen/FunctionLoweringInfo.h"
5 #include "llvm/CodeGen/FastISel.h"
6 #include "llvm/CodeGen/MachineInstrBuilder.h"
7 #include "llvm/IR/GlobalAlias.h"
8 #include "llvm/IR/GlobalVariable.h"
9 #include "llvm/Target/TargetInstrInfo.h"
10 #include "llvm/Target/TargetLibraryInfo.h"
11 #include "MipsRegisterInfo.h"
12 #include "MipsISelLowering.h"
13 #include "MipsMachineFunction.h"
14 #include "MipsSubtarget.h"
15 #include "MipsTargetMachine.h"
21 // All possible address modes.
22 typedef struct Address {
23 enum { RegBase, FrameIndexBase } BaseType;
32 // Innocuous defaults for our address.
33 Address() : BaseType(RegBase), Offset(0) { Base.Reg = 0; }
36 class MipsFastISel final : public FastISel {
38 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
39 /// make the right decision when generating code for different targets.
41 const TargetMachine &TM;
42 const TargetInstrInfo &TII;
43 const TargetLowering &TLI;
44 const MipsSubtarget &Subtarget;
45 MipsFunctionInfo *MFI;
47 // Convenience variables to avoid some queries.
53 explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
54 const TargetLibraryInfo *libInfo)
55 : FastISel(funcInfo, libInfo),
56 M(const_cast<Module &>(*funcInfo.Fn->getParent())),
57 TM(funcInfo.MF->getTarget()), TII(*TM.getInstrInfo()),
58 TLI(*TM.getTargetLowering()),
59 Subtarget(TM.getSubtarget<MipsSubtarget>()) {
60 MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
61 Context = &funcInfo.Fn->getContext();
62 TargetSupported = ((Subtarget.getRelocationModel() == Reloc::PIC_) &&
63 (Subtarget.hasMips32r2() && (Subtarget.isABI_O32())));
66 bool TargetSelectInstruction(const Instruction *I) override;
67 unsigned TargetMaterializeConstant(const Constant *C) override;
69 bool ComputeAddress(const Value *Obj, Address &Addr);
72 bool EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
73 unsigned Alignment = 0);
74 bool SelectRet(const Instruction *I);
75 bool SelectStore(const Instruction *I);
77 bool isTypeLegal(Type *Ty, MVT &VT);
78 bool isLoadTypeLegal(Type *Ty, MVT &VT);
80 unsigned MaterializeFP(const ConstantFP *CFP, MVT VT);
81 unsigned MaterializeGV(const GlobalValue *GV, MVT VT);
82 unsigned MaterializeInt(const Constant *C, MVT VT);
83 unsigned Materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
85 // for some reason, this default is not generated by tablegen
86 // so we explicitly generate it here.
88 unsigned FastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
89 unsigned Op0, bool Op0IsKill, uint64_t imm1,
90 uint64_t imm2, unsigned Op3, bool Op3IsKill) {
94 #include "MipsGenFastISel.inc"
97 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
98 EVT evt = TLI.getValueType(Ty, true);
99 // Only handle simple types.
100 if (evt == MVT::Other || !evt.isSimple())
102 VT = evt.getSimpleVT();
104 // Handle all legal types, i.e. a register that will directly hold this
106 return TLI.isTypeLegal(VT);
109 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
110 if (isTypeLegal(Ty, VT))
112 // We will extend this in a later patch:
113 // If this is a type than can be sign or zero-extended to a basic operation
114 // go ahead and accept it now.
118 bool MipsFastISel::ComputeAddress(const Value *Obj, Address &Addr) {
119 // This construct looks a big awkward but it is how other ports handle this
120 // and as this function is more fully completed, these cases which
121 // return false will have additional code in them.
123 if (isa<Instruction>(Obj))
125 else if (isa<ConstantExpr>(Obj))
127 Addr.Base.Reg = getRegForValue(Obj);
128 return Addr.Base.Reg != 0;
131 // Materialize a constant into a register, and return the register
132 // number (or zero if we failed to handle it).
133 unsigned MipsFastISel::TargetMaterializeConstant(const Constant *C) {
134 EVT CEVT = TLI.getValueType(C->getType(), true);
136 // Only handle simple types.
137 if (!CEVT.isSimple())
139 MVT VT = CEVT.getSimpleVT();
141 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
142 return MaterializeFP(CFP, VT);
143 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
144 return MaterializeGV(GV, VT);
145 else if (isa<ConstantInt>(C))
146 return MaterializeInt(C, VT);
151 bool MipsFastISel::EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
152 unsigned Alignment) {
154 // more cases will be handled here in following patches.
158 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::SW))
160 .addReg(Addr.Base.Reg)
161 .addImm(Addr.Offset);
165 bool MipsFastISel::SelectStore(const Instruction *I) {
166 Value *Op0 = I->getOperand(0);
169 // Atomic stores need special handling.
170 if (cast<StoreInst>(I)->isAtomic())
173 // Verify we have a legal type before going any further.
175 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
178 // Get the value to be stored into a register.
179 SrcReg = getRegForValue(Op0);
183 // See if we can handle this address.
185 if (!ComputeAddress(I->getOperand(1), Addr))
188 if (!EmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
193 bool MipsFastISel::SelectRet(const Instruction *I) {
194 const ReturnInst *Ret = cast<ReturnInst>(I);
196 if (!FuncInfo.CanLowerReturn)
198 if (Ret->getNumOperands() > 0) {
201 unsigned RetOpc = Mips::RetRA;
202 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(RetOpc));
206 bool MipsFastISel::TargetSelectInstruction(const Instruction *I) {
207 if (!TargetSupported)
209 switch (I->getOpcode()) {
212 case Instruction::Store:
213 return SelectStore(I);
214 case Instruction::Ret:
221 unsigned MipsFastISel::MaterializeFP(const ConstantFP *CFP, MVT VT) {
225 unsigned MipsFastISel::MaterializeGV(const GlobalValue *GV, MVT VT) {
226 // For now 32-bit only.
229 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
230 unsigned DestReg = createResultReg(RC);
231 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
232 bool IsThreadLocal = GVar && GVar->isThreadLocal();
233 // TLS not supported at this time.
236 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LW), DestReg)
237 .addReg(MFI->getGlobalBaseReg())
238 .addGlobalAddress(GV, 0, MipsII::MO_GOT);
241 unsigned MipsFastISel::MaterializeInt(const Constant *C, MVT VT) {
242 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
244 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
245 const ConstantInt *CI = cast<ConstantInt>(C);
247 if (CI->isNegative())
248 Imm = CI->getSExtValue();
250 Imm = CI->getZExtValue();
251 return Materialize32BitInt(Imm, RC);
254 unsigned MipsFastISel::Materialize32BitInt(int64_t Imm,
255 const TargetRegisterClass *RC) {
256 unsigned ResultReg = createResultReg(RC);
258 if (isInt<16>(Imm)) {
259 unsigned Opc = Mips::ADDiu;
260 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
264 } else if (isUInt<16>(Imm)) {
265 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::ORi),
271 unsigned Lo = Imm & 0xFFFF;
272 unsigned Hi = (Imm >> 16) & 0xFFFF;
274 // Both Lo and Hi have nonzero bits.
275 unsigned TmpReg = createResultReg(RC);
276 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LUi),
278 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::ORi),
284 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LUi),
285 ResultReg).addImm(Hi);
291 FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
292 const TargetLibraryInfo *libInfo) {
293 return new MipsFastISel(funcInfo, libInfo);