1 //===-- MipsDelaySlotFiller.cpp - Mips Delay Slot Filler ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Simple pass to fill delay slots with useful instructions.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "delay-slot-filler"
17 #include "MipsTargetMachine.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/SmallPtrSet.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/Analysis/ValueTracking.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetRegisterInfo.h"
33 STATISTIC(FilledSlots, "Number of delay slots filled");
34 STATISTIC(UsefulSlots, "Number of delay slots filled with instructions that"
37 static cl::opt<bool> DisableDelaySlotFiller(
38 "disable-mips-delay-filler",
40 cl::desc("Fill all delay slots with NOPs."),
43 // This option can be used to silence complaints by machine verifier passes.
44 static cl::opt<bool> SkipDelaySlotFiller(
45 "skip-mips-delay-filler",
47 cl::desc("Skip MIPS' delay slot filling pass."),
50 static cl::opt<bool> DisableForwardSearch(
51 "disable-mips-df-forward-search",
53 cl::desc("Disallow MIPS delay filler to search forward."),
59 RegDefsUses(TargetMachine &TM);
60 void init(const MachineInstr &MI);
62 /// This function sets all caller-saved registers in Defs.
63 void setCallerSaved(const MachineInstr &MI);
65 bool update(const MachineInstr &MI, unsigned Begin, unsigned End);
68 bool checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses, unsigned Reg,
71 /// Returns true if Reg or its alias is in RegSet.
72 bool isRegInSet(const BitVector &RegSet, unsigned Reg) const;
74 const TargetRegisterInfo &TRI;
78 /// Base class for inspecting loads and stores.
79 class InspectMemInstr {
81 virtual bool hasHazard(const MachineInstr &MI) = 0;
82 virtual ~InspectMemInstr() {}
85 /// This subclass rejects any memory instructions.
86 class NoMemInstr : public InspectMemInstr {
88 virtual bool hasHazard(const MachineInstr &MI);
91 /// This subclass uses memory dependence information to determine whether a
92 /// memory instruction can be moved to a delay slot.
93 class MemDefsUses : public InspectMemInstr {
95 MemDefsUses(const MachineFrameInfo *MFI);
97 /// Return true if MI cannot be moved to delay slot.
98 virtual bool hasHazard(const MachineInstr &MI);
101 /// Update Defs and Uses. Return true if there exist dependences that
102 /// disqualify the delay slot candidate between V and values in Uses and Defs.
103 bool updateDefsUses(const Value *V, bool MayStore);
105 /// Get the list of underlying objects of MI's memory operand.
106 bool getUnderlyingObjects(const MachineInstr &MI,
107 SmallVectorImpl<const Value *> &Objects) const;
109 const MachineFrameInfo *MFI;
110 SmallPtrSet<const Value*, 4> Uses, Defs;
112 /// Flags indicating whether loads or stores have been seen.
113 bool SeenLoad, SeenStore;
115 /// Flags indicating whether loads or stores with no underlying objects have
117 bool SeenNoObjLoad, SeenNoObjStore;
119 /// Memory instructions are not allowed to move to delay slot if this flag
124 class Filler : public MachineFunctionPass {
126 Filler(TargetMachine &tm)
127 : MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()) { }
129 virtual const char *getPassName() const {
130 return "Mips Delay Slot Filler";
133 bool runOnMachineFunction(MachineFunction &F) {
134 if (SkipDelaySlotFiller)
137 bool Changed = false;
138 for (MachineFunction::iterator FI = F.begin(), FE = F.end();
140 Changed |= runOnMachineBasicBlock(*FI);
145 typedef MachineBasicBlock::iterator Iter;
146 typedef MachineBasicBlock::reverse_iterator ReverseIter;
148 bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
150 /// This function checks if it is valid to move Candidate to the delay slot
151 /// and returns true if it isn't. It also updates memory and register
152 /// dependence information.
153 bool delayHasHazard(const MachineInstr &Candidate, RegDefsUses &RegDU,
154 InspectMemInstr &IM) const;
156 /// This function searches range [Begin, End) for an instruction that can be
157 /// moved to the delay slot. Returns true on success.
158 template<typename IterTy>
159 bool searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
160 RegDefsUses &RegDU, InspectMemInstr &IM, IterTy &Filler) const;
162 /// This function searches in the backward direction for an instruction that
163 /// can be moved to the delay slot. Returns true on success.
164 bool searchBackward(MachineBasicBlock &MBB, Iter Slot) const;
166 /// This function searches MBB in the forward direction for an instruction
167 /// that can be moved to the delay slot. Returns true on success.
168 bool searchForward(MachineBasicBlock &MBB, Iter Slot) const;
170 bool terminateSearch(const MachineInstr &Candidate) const;
173 const TargetInstrInfo *TII;
178 } // end of anonymous namespace
180 RegDefsUses::RegDefsUses(TargetMachine &TM)
181 : TRI(*TM.getRegisterInfo()), Defs(TRI.getNumRegs(), false),
182 Uses(TRI.getNumRegs(), false) {}
184 void RegDefsUses::init(const MachineInstr &MI) {
185 // Add all register operands which are explicit and non-variadic.
186 update(MI, 0, MI.getDesc().getNumOperands());
188 // If MI is a call, add RA to Defs to prevent users of RA from going into
193 // Add all implicit register operands of branch instructions except
196 update(MI, MI.getDesc().getNumOperands(), MI.getNumOperands());
197 Defs.reset(Mips::AT);
201 void RegDefsUses::setCallerSaved(const MachineInstr &MI) {
204 // If MI is a call, add all caller-saved registers to Defs.
205 BitVector CallerSavedRegs(TRI.getNumRegs(), true);
207 CallerSavedRegs.reset(Mips::ZERO);
208 CallerSavedRegs.reset(Mips::ZERO_64);
210 for (const MCPhysReg *R = TRI.getCalleeSavedRegs(); *R; ++R)
211 for (MCRegAliasIterator AI(*R, &TRI, true); AI.isValid(); ++AI)
212 CallerSavedRegs.reset(*AI);
214 Defs |= CallerSavedRegs;
217 bool RegDefsUses::update(const MachineInstr &MI, unsigned Begin, unsigned End) {
218 BitVector NewDefs(TRI.getNumRegs()), NewUses(TRI.getNumRegs());
219 bool HasHazard = false;
221 for (unsigned I = Begin; I != End; ++I) {
222 const MachineOperand &MO = MI.getOperand(I);
224 if (MO.isReg() && MO.getReg())
225 HasHazard |= checkRegDefsUses(NewDefs, NewUses, MO.getReg(), MO.isDef());
234 bool RegDefsUses::checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses,
235 unsigned Reg, bool IsDef) const {
238 // check whether Reg has already been defined or used.
239 return (isRegInSet(Defs, Reg) || isRegInSet(Uses, Reg));
243 // check whether Reg has already been defined.
244 return isRegInSet(Defs, Reg);
247 bool RegDefsUses::isRegInSet(const BitVector &RegSet, unsigned Reg) const {
248 // Check Reg and all aliased Registers.
249 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
250 if (RegSet.test(*AI))
255 bool NoMemInstr::hasHazard(const MachineInstr &MI) {
256 // Return true if MI accesses memory.
257 return (MI.mayStore() || MI.mayLoad());
260 MemDefsUses::MemDefsUses(const MachineFrameInfo *MFI_)
261 : MFI(MFI_), SeenLoad(false), SeenStore(false), SeenNoObjLoad(false),
262 SeenNoObjStore(false), ForbidMemInstr(false) {}
264 bool MemDefsUses::hasHazard(const MachineInstr &MI) {
265 if (!MI.mayStore() && !MI.mayLoad())
271 bool OrigSeenLoad = SeenLoad, OrigSeenStore = SeenStore;
273 SeenLoad |= MI.mayLoad();
274 SeenStore |= MI.mayStore();
276 // If MI is an ordered or volatile memory reference, disallow moving
277 // subsequent loads and stores to delay slot.
278 if (MI.hasOrderedMemoryRef() && (OrigSeenLoad || OrigSeenStore)) {
279 ForbidMemInstr = true;
283 bool HasHazard = false;
284 SmallVector<const Value *, 4> Objs;
286 // Check underlying object list.
287 if (getUnderlyingObjects(MI, Objs)) {
288 for (SmallVector<const Value *, 4>::const_iterator I = Objs.begin();
289 I != Objs.end(); ++I)
290 HasHazard |= updateDefsUses(*I, MI.mayStore());
295 // No underlying objects found.
296 HasHazard = MI.mayStore() && (OrigSeenLoad || OrigSeenStore);
297 HasHazard |= MI.mayLoad() || OrigSeenStore;
299 SeenNoObjLoad |= MI.mayLoad();
300 SeenNoObjStore |= MI.mayStore();
305 bool MemDefsUses::updateDefsUses(const Value *V, bool MayStore) {
307 return !Defs.insert(V) || Uses.count(V) || SeenNoObjStore || SeenNoObjLoad;
310 return Defs.count(V) || SeenNoObjStore;
314 getUnderlyingObjects(const MachineInstr &MI,
315 SmallVectorImpl<const Value *> &Objects) const {
316 if (!MI.hasOneMemOperand() || !(*MI.memoperands_begin())->getValue())
319 const Value *V = (*MI.memoperands_begin())->getValue();
321 SmallVector<Value *, 4> Objs;
322 GetUnderlyingObjects(const_cast<Value *>(V), Objs);
324 for (SmallVector<Value*, 4>::iterator I = Objs.begin(), E = Objs.end();
326 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(*I)) {
327 if (PSV->isAliased(MFI))
329 } else if (!isIdentifiedObject(V))
332 Objects.push_back(*I);
338 /// runOnMachineBasicBlock - Fill in delay slots for the given basic block.
339 /// We assume there is only one delay slot per delayed instruction.
340 bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
341 bool Changed = false;
343 for (Iter I = MBB.begin(); I != MBB.end(); ++I) {
344 if (!I->hasDelaySlot())
350 // Delay slot filling is disabled at -O0.
351 if (!DisableDelaySlotFiller && (TM.getOptLevel() != CodeGenOpt::None) &&
352 (searchBackward(MBB, I) || searchForward(MBB, I)))
355 // Bundle the NOP to the instruction with the delay slot.
356 BuildMI(MBB, llvm::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
357 MIBundleBuilder(MBB, I, llvm::next(llvm::next(I)));
363 /// createMipsDelaySlotFillerPass - Returns a pass that fills in delay
364 /// slots in Mips MachineFunctions
365 FunctionPass *llvm::createMipsDelaySlotFillerPass(MipsTargetMachine &tm) {
366 return new Filler(tm);
369 template<typename IterTy>
370 bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
371 RegDefsUses &RegDU, InspectMemInstr& IM,
372 IterTy &Filler) const {
373 for (IterTy I = Begin; I != End; ++I) {
375 if (I->isDebugValue())
378 if (terminateSearch(*I))
381 assert((!I->isCall() && !I->isReturn() && !I->isBranch()) &&
382 "Cannot put calls, returns or branches in delay slot.");
384 if (delayHasHazard(*I, RegDU, IM))
394 bool Filler::searchBackward(MachineBasicBlock &MBB, Iter Slot) const {
395 RegDefsUses RegDU(TM);
396 MemDefsUses MemDU(MBB.getParent()->getFrameInfo());
401 if (searchRange(MBB, ReverseIter(Slot), MBB.rend(), RegDU, MemDU, Filler)) {
402 MBB.splice(llvm::next(Slot), &MBB, llvm::next(Filler).base());
403 MIBundleBuilder(MBB, Slot, llvm::next(llvm::next(Slot)));
411 bool Filler::searchForward(MachineBasicBlock &MBB, Iter Slot) const {
412 // Can handle only calls.
416 RegDefsUses RegDU(TM);
420 RegDU.setCallerSaved(*Slot);
422 if (searchRange(MBB, llvm::next(Slot), MBB.end(), RegDU, NM, Filler)) {
423 MBB.splice(llvm::next(Slot), &MBB, Filler);
424 MIBundleBuilder(MBB, Slot, llvm::next(llvm::next(Slot)));
432 bool Filler::delayHasHazard(const MachineInstr &Candidate, RegDefsUses &RegDU,
433 InspectMemInstr &IM) const {
434 bool HasHazard = (Candidate.isImplicitDef() || Candidate.isKill());
436 HasHazard |= IM.hasHazard(Candidate);
437 HasHazard |= RegDU.update(Candidate, 0, Candidate.getNumOperands());
442 bool Filler::terminateSearch(const MachineInstr &Candidate) const {
443 return (Candidate.isTerminator() || Candidate.isCall() ||
444 Candidate.isLabel() || Candidate.isInlineAsm() ||
445 Candidate.hasUnmodeledSideEffects());