lib/Target/Mips/MipsDSPInstrInfo.td

   1 //===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes Mips DSP ASE instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // ImmLeaf
  15 def immZExt1 : ImmLeaf<i32, [{return isUInt<1>(Imm);}]>;
  16 def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>;
  17 def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>;
  18 def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>;
  19 def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>;
  20 def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>;
  21 def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>;
  22
  23 // Mips-specific dsp nodes
  24 def SDT_MipsExtr : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
  25                                         SDTCisVT<2, untyped>]>;
  26 def SDT_MipsShilo : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
  27                                          SDTCisSameAs<0, 2>, SDTCisVT<1, i32>]>;
  28 def SDT_MipsDPA : SDTypeProfile<1, 3, [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
  29                                        SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
  30 def SDT_MipsSHIFT_DSP : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
  31                                              SDTCisVT<2, i32>]>;
  32
  33 class MipsDSPBase<string Opc, SDTypeProfile Prof> :
  34   SDNode<!strconcat("MipsISD::", Opc), Prof>;
  35
  36 class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> :
  37   SDNode<!strconcat("MipsISD::", Opc), Prof, [SDNPHasChain, SDNPSideEffect]>;
  38
  39 def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>;
  40 def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>;
  41 def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>;
  42 def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>;
  43 def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>;
  44 def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>;
  45
  46 def MipsSHILO : MipsDSPBase<"SHILO", SDT_MipsShilo>;
  47 def MipsMTHLIP : MipsDSPSideEffectBase<"MTHLIP", SDT_MipsShilo>;
  48
  49 def MipsMULSAQ_S_W_PH : MipsDSPSideEffectBase<"MULSAQ_S_W_PH", SDT_MipsDPA>;
  50 def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>;
  51 def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>;
  52 def MipsMAQ_SA_W_PHL : MipsDSPSideEffectBase<"MAQ_SA_W_PHL", SDT_MipsDPA>;
  53 def MipsMAQ_SA_W_PHR : MipsDSPSideEffectBase<"MAQ_SA_W_PHR", SDT_MipsDPA>;
  54
  55 def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>;
  56 def MipsDPAU_H_QBR : MipsDSPBase<"DPAU_H_QBR", SDT_MipsDPA>;
  57 def MipsDPSU_H_QBL : MipsDSPBase<"DPSU_H_QBL", SDT_MipsDPA>;
  58 def MipsDPSU_H_QBR : MipsDSPBase<"DPSU_H_QBR", SDT_MipsDPA>;
  59 def MipsDPAQ_S_W_PH : MipsDSPSideEffectBase<"DPAQ_S_W_PH", SDT_MipsDPA>;
  60 def MipsDPSQ_S_W_PH : MipsDSPSideEffectBase<"DPSQ_S_W_PH", SDT_MipsDPA>;
  61 def MipsDPAQ_SA_L_W : MipsDSPSideEffectBase<"DPAQ_SA_L_W", SDT_MipsDPA>;
  62 def MipsDPSQ_SA_L_W : MipsDSPSideEffectBase<"DPSQ_SA_L_W", SDT_MipsDPA>;
  63
  64 def MipsDPA_W_PH : MipsDSPBase<"DPA_W_PH", SDT_MipsDPA>;
  65 def MipsDPS_W_PH : MipsDSPBase<"DPS_W_PH", SDT_MipsDPA>;
  66 def MipsDPAQX_S_W_PH : MipsDSPSideEffectBase<"DPAQX_S_W_PH", SDT_MipsDPA>;
  67 def MipsDPAQX_SA_W_PH : MipsDSPSideEffectBase<"DPAQX_SA_W_PH", SDT_MipsDPA>;
  68 def MipsDPAX_W_PH : MipsDSPBase<"DPAX_W_PH", SDT_MipsDPA>;
  69 def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>;
  70 def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>;
  71 def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>;
  72 def MipsMULSA_W_PH : MipsDSPBase<"MULSA_W_PH", SDT_MipsDPA>;
  73
  74 def MipsMULT : MipsDSPBase<"MULT", SDT_MipsDPA>;
  75 def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>;
  76 def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA>;
  77 def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA>;
  78 def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA>;
  79 def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>;
  80 def MipsSHLL_DSP : MipsDSPBase<"SHLL_DSP", SDT_MipsSHIFT_DSP>;
  81 def MipsSHRA_DSP : MipsDSPBase<"SHRA_DSP", SDT_MipsSHIFT_DSP>;
  82 def MipsSHRL_DSP : MipsDSPBase<"SHRL_DSP", SDT_MipsSHIFT_DSP>;
  83 def MipsSETCC_DSP : MipsDSPBase<"SETCC_DSP", SDTSetCC>;
  84 def MipsSELECT_CC_DSP : MipsDSPBase<"SELECT_CC_DSP", SDTSelectCC>;
  85
  86 // Flags.
  87 class Uses<list<Register> Regs> {
  88   list<Register> Uses = Regs;
  89 }
  90
  91 class Defs<list<Register> Regs> {
  92   list<Register> Defs = Regs;
  93 }
  94
  95 // Instruction encoding.
  96 class ADDU_QB_ENC : ADDU_QB_FMT<0b00000>;
  97 class ADDU_S_QB_ENC : ADDU_QB_FMT<0b00100>;
  98 class SUBU_QB_ENC : ADDU_QB_FMT<0b00001>;
  99 class SUBU_S_QB_ENC : ADDU_QB_FMT<0b00101>;
 100 class ADDQ_PH_ENC : ADDU_QB_FMT<0b01010>;
 101 class ADDQ_S_PH_ENC : ADDU_QB_FMT<0b01110>;
 102 class SUBQ_PH_ENC : ADDU_QB_FMT<0b01011>;
 103 class SUBQ_S_PH_ENC : ADDU_QB_FMT<0b01111>;
 104 class ADDQ_S_W_ENC : ADDU_QB_FMT<0b10110>;
 105 class SUBQ_S_W_ENC : ADDU_QB_FMT<0b10111>;
 106 class ADDSC_ENC : ADDU_QB_FMT<0b10000>;
 107 class ADDWC_ENC : ADDU_QB_FMT<0b10001>;
 108 class MODSUB_ENC : ADDU_QB_FMT<0b10010>;
 109 class RADDU_W_QB_ENC : RADDU_W_QB_FMT<0b10100>;
 110 class ABSQ_S_PH_ENC : ABSQ_S_PH_R2_FMT<0b01001>;
 111 class ABSQ_S_W_ENC : ABSQ_S_PH_R2_FMT<0b10001>;
 112 class PRECRQ_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01100>;
 113 class PRECRQ_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10100>;
 114 class PRECRQ_RS_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10101>;
 115 class PRECRQU_S_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01111>;
 116 class PRECEQ_W_PHL_ENC : ABSQ_S_PH_R2_FMT<0b01100>;
 117 class PRECEQ_W_PHR_ENC : ABSQ_S_PH_R2_FMT<0b01101>;
 118 class PRECEQU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b00100>;
 119 class PRECEQU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b00101>;
 120 class PRECEQU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b00110>;
 121 class PRECEQU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b00111>;
 122 class PRECEU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b11100>;
 123 class PRECEU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b11101>;
 124 class PRECEU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b11110>;
 125 class PRECEU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b11111>;
 126 class SHLL_QB_ENC : SHLL_QB_FMT<0b00000>;
 127 class SHLLV_QB_ENC : SHLL_QB_FMT<0b00010>;
 128 class SHRL_QB_ENC : SHLL_QB_FMT<0b00001>;
 129 class SHRLV_QB_ENC : SHLL_QB_FMT<0b00011>;
 130 class SHLL_PH_ENC : SHLL_QB_FMT<0b01000>;
 131 class SHLLV_PH_ENC : SHLL_QB_FMT<0b01010>;
 132 class SHLL_S_PH_ENC : SHLL_QB_FMT<0b01100>;
 133 class SHLLV_S_PH_ENC : SHLL_QB_FMT<0b01110>;
 134 class SHRA_PH_ENC : SHLL_QB_FMT<0b01001>;
 135 class SHRAV_PH_ENC : SHLL_QB_FMT<0b01011>;
 136 class SHRA_R_PH_ENC : SHLL_QB_FMT<0b01101>;
 137 class SHRAV_R_PH_ENC : SHLL_QB_FMT<0b01111>;
 138 class SHLL_S_W_ENC : SHLL_QB_FMT<0b10100>;
 139 class SHLLV_S_W_ENC : SHLL_QB_FMT<0b10110>;
 140 class SHRA_R_W_ENC : SHLL_QB_FMT<0b10101>;
 141 class SHRAV_R_W_ENC : SHLL_QB_FMT<0b10111>;
 142 class MULEU_S_PH_QBL_ENC : ADDU_QB_FMT<0b00110>;
 143 class MULEU_S_PH_QBR_ENC : ADDU_QB_FMT<0b00111>;
 144 class MULEQ_S_W_PHL_ENC : ADDU_QB_FMT<0b11100>;
 145 class MULEQ_S_W_PHR_ENC : ADDU_QB_FMT<0b11101>;
 146 class MULQ_RS_PH_ENC : ADDU_QB_FMT<0b11111>;
 147 class MULSAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00110>;
 148 class MAQ_S_W_PHL_ENC : DPA_W_PH_FMT<0b10100>;
 149 class MAQ_S_W_PHR_ENC : DPA_W_PH_FMT<0b10110>;
 150 class MAQ_SA_W_PHL_ENC : DPA_W_PH_FMT<0b10000>;
 151 class MAQ_SA_W_PHR_ENC : DPA_W_PH_FMT<0b10010>;
 152 class MFHI_ENC : MFHI_FMT<0b010000>;
 153 class MFLO_ENC : MFHI_FMT<0b010010>;
 154 class MTHI_ENC : MTHI_FMT<0b010001>;
 155 class MTLO_ENC : MTHI_FMT<0b010011>;
 156 class DPAU_H_QBL_ENC : DPA_W_PH_FMT<0b00011>;
 157 class DPAU_H_QBR_ENC : DPA_W_PH_FMT<0b00111>;
 158 class DPSU_H_QBL_ENC : DPA_W_PH_FMT<0b01011>;
 159 class DPSU_H_QBR_ENC : DPA_W_PH_FMT<0b01111>;
 160 class DPAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00100>;
 161 class DPSQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00101>;
 162 class DPAQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01100>;
 163 class DPSQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01101>;
 164 class MULT_DSP_ENC : MULT_FMT<0b000000, 0b011000>;
 165 class MULTU_DSP_ENC : MULT_FMT<0b000000, 0b011001>;
 166 class MADD_DSP_ENC : MULT_FMT<0b011100, 0b000000>;
 167 class MADDU_DSP_ENC : MULT_FMT<0b011100, 0b000001>;
 168 class MSUB_DSP_ENC : MULT_FMT<0b011100, 0b000100>;
 169 class MSUBU_DSP_ENC : MULT_FMT<0b011100, 0b000101>;
 170 class CMPU_EQ_QB_ENC : CMP_EQ_QB_R2_FMT<0b00000>;
 171 class CMPU_LT_QB_ENC : CMP_EQ_QB_R2_FMT<0b00001>;
 172 class CMPU_LE_QB_ENC : CMP_EQ_QB_R2_FMT<0b00010>;
 173 class CMPGU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b00100>;
 174 class CMPGU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b00101>;
 175 class CMPGU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b00110>;
 176 class CMP_EQ_PH_ENC : CMP_EQ_QB_R2_FMT<0b01000>;
 177 class CMP_LT_PH_ENC : CMP_EQ_QB_R2_FMT<0b01001>;
 178 class CMP_LE_PH_ENC : CMP_EQ_QB_R2_FMT<0b01010>;
 179 class BITREV_ENC : ABSQ_S_PH_R2_FMT<0b11011>;
 180 class PACKRL_PH_ENC : CMP_EQ_QB_R3_FMT<0b01110>;
 181 class REPL_QB_ENC : REPL_FMT<0b00010>;
 182 class REPL_PH_ENC : REPL_FMT<0b01010>;
 183 class REPLV_QB_ENC : ABSQ_S_PH_R2_FMT<0b00011>;
 184 class REPLV_PH_ENC : ABSQ_S_PH_R2_FMT<0b01011>;
 185 class PICK_QB_ENC : CMP_EQ_QB_R3_FMT<0b00011>;
 186 class PICK_PH_ENC : CMP_EQ_QB_R3_FMT<0b01011>;
 187 class LWX_ENC : LX_FMT<0b00000>;
 188 class LHX_ENC : LX_FMT<0b00100>;
 189 class LBUX_ENC : LX_FMT<0b00110>;
 190 class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>;
 191 class INSV_ENC : INSV_FMT<0b001100>;
 192
 193 class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>;
 194 class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>;
 195 class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>;
 196 class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>;
 197 class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>;
 198 class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>;
 199 class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>;
 200 class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>;
 201 class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>;
 202 class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>;
 203 class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>;
 204 class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>;
 205 class SHILO_ENC : SHILO_R1_FMT<0b11010>;
 206 class SHILOV_ENC : SHILO_R2_FMT<0b11011>;
 207 class MTHLIP_ENC : SHILO_R2_FMT<0b11111>;
 208
 209 class RDDSP_ENC : RDDSP_FMT<0b10010>;
 210 class WRDSP_ENC : WRDSP_FMT<0b10011>;
 211 class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>;
 212 class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>;
 213 class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>;
 214 class SUBU_S_PH_ENC : ADDU_QB_FMT<0b01101>;
 215 class CMPGDU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b11000>;
 216 class CMPGDU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b11001>;
 217 class CMPGDU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b11010>;
 218 class ABSQ_S_QB_ENC : ABSQ_S_PH_R2_FMT<0b00001>;
 219 class ADDUH_QB_ENC : ADDUH_QB_FMT<0b00000>;
 220 class ADDUH_R_QB_ENC : ADDUH_QB_FMT<0b00010>;
 221 class SUBUH_QB_ENC : ADDUH_QB_FMT<0b00001>;
 222 class SUBUH_R_QB_ENC : ADDUH_QB_FMT<0b00011>;
 223 class ADDQH_PH_ENC : ADDUH_QB_FMT<0b01000>;
 224 class ADDQH_R_PH_ENC : ADDUH_QB_FMT<0b01010>;
 225 class SUBQH_PH_ENC : ADDUH_QB_FMT<0b01001>;
 226 class SUBQH_R_PH_ENC : ADDUH_QB_FMT<0b01011>;
 227 class ADDQH_W_ENC : ADDUH_QB_FMT<0b10000>;
 228 class ADDQH_R_W_ENC : ADDUH_QB_FMT<0b10010>;
 229 class SUBQH_W_ENC : ADDUH_QB_FMT<0b10001>;
 230 class SUBQH_R_W_ENC : ADDUH_QB_FMT<0b10011>;
 231 class MUL_PH_ENC : ADDUH_QB_FMT<0b01100>;
 232 class MUL_S_PH_ENC : ADDUH_QB_FMT<0b01110>;
 233 class MULQ_S_W_ENC : ADDUH_QB_FMT<0b10110>;
 234 class MULQ_RS_W_ENC : ADDUH_QB_FMT<0b10111>;
 235 class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>;
 236 class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>;
 237 class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>;
 238 class DPAQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11000>;
 239 class DPAQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11010>;
 240 class DPAX_W_PH_ENC : DPA_W_PH_FMT<0b01000>;
 241 class DPSX_W_PH_ENC : DPA_W_PH_FMT<0b01001>;
 242 class DPSQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11001>;
 243 class DPSQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11011>;
 244 class MULSA_W_PH_ENC : DPA_W_PH_FMT<0b00010>;
 245 class PRECR_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01101>;
 246 class PRECR_SRA_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11110>;
 247 class PRECR_SRA_R_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11111>;
 248 class SHRA_QB_ENC : SHLL_QB_FMT<0b00100>;
 249 class SHRAV_QB_ENC : SHLL_QB_FMT<0b00110>;
 250 class SHRA_R_QB_ENC : SHLL_QB_FMT<0b00101>;
 251 class SHRAV_R_QB_ENC : SHLL_QB_FMT<0b00111>;
 252 class SHRL_PH_ENC : SHLL_QB_FMT<0b11001>;
 253 class SHRLV_PH_ENC : SHLL_QB_FMT<0b11011>;
 254 class APPEND_ENC : APPEND_FMT<0b00000>;
 255 class BALIGN_ENC : APPEND_FMT<0b10000>;
 256 class PREPEND_ENC : APPEND_FMT<0b00001>;
 257
 258 // Instruction desc.
 259 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 260                         InstrItinClass itin, RegisterOperand ROD,
 261                         RegisterOperand ROS,  RegisterOperand ROT = ROS> {
 262   dag OutOperandList = (outs ROD:$rd);
 263   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 264   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 265   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
 266   InstrItinClass Itinerary = itin;
 267   string BaseOpcode = instr_asm;
 268 }
 269
 270 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 271                            InstrItinClass itin, RegisterOperand ROD,
 272                            RegisterOperand ROS = ROD> {
 273   dag OutOperandList = (outs ROD:$rd);
 274   dag InOperandList = (ins ROS:$rs);
 275   string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
 276   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))];
 277   InstrItinClass Itinerary = itin;
 278 }
 279
 280 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 281                              InstrItinClass itin, RegisterOperand ROS,
 282                              RegisterOperand ROT = ROS> {
 283   dag OutOperandList = (outs);
 284   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 285   string AsmString = !strconcat(instr_asm, "\t$rs, $rt");
 286   list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)];
 287   InstrItinClass Itinerary = itin;
 288 }
 289
 290 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 291                              InstrItinClass itin, RegisterOperand ROD,
 292                              RegisterOperand ROS,  RegisterOperand ROT = ROS> {
 293   dag OutOperandList = (outs ROD:$rd);
 294   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 295   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 296   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
 297   InstrItinClass Itinerary = itin;
 298   string BaseOpcode = instr_asm;
 299 }
 300
 301 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 302                                InstrItinClass itin, RegisterOperand ROT,
 303                                RegisterOperand ROS = ROT> {
 304   dag OutOperandList = (outs ROT:$rt);
 305   dag InOperandList = (ins ROS:$rs, uimm5:$sa, ROS:$src);
 306   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
 307   list<dag> Pattern = [(set ROT:$rt, (OpNode ROS:$src, ROS:$rs, immZExt5:$sa))];
 308   InstrItinClass Itinerary = itin;
 309   string Constraints = "$src = $rt";
 310   string BaseOpcode = instr_asm;
 311 }
 312
 313 class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 314                              InstrItinClass itin, RegisterOperand ROD,
 315                              RegisterOperand ROT = ROD> {
 316   dag OutOperandList = (outs ROD:$rd);
 317   dag InOperandList = (ins ROT:$rt);
 318   string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
 319   list<dag> Pattern = [(set ROD:$rd, (OpNode ROT:$rt))];
 320   InstrItinClass Itinerary = itin;
 321   string BaseOpcode = instr_asm;
 322 }
 323
 324 class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 325                      ImmLeaf immPat, InstrItinClass itin, RegisterOperand RO> {
 326   dag OutOperandList = (outs RO:$rd);
 327   dag InOperandList = (ins uimm16:$imm);
 328   string AsmString = !strconcat(instr_asm, "\t$rd, $imm");
 329   list<dag> Pattern = [(set RO:$rd, (OpNode immPat:$imm))];
 330   InstrItinClass Itinerary = itin;
 331 }
 332
 333 class SHLL_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 334                            InstrItinClass itin, RegisterOperand RO> {
 335   dag OutOperandList = (outs RO:$rd);
 336   dag InOperandList =  (ins RO:$rt, GPR32Opnd:$rs_sa);
 337   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 338   list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs_sa))];
 339   InstrItinClass Itinerary = itin;
 340   string BaseOpcode = instr_asm;
 341 }
 342
 343 class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 344                            SDPatternOperator ImmPat, InstrItinClass itin,
 345                            RegisterOperand RO, Operand ImmOpnd> {
 346   dag OutOperandList = (outs RO:$rd);
 347   dag InOperandList = (ins RO:$rt, ImmOpnd:$rs_sa);
 348   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 349   list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, ImmPat:$rs_sa))];
 350   InstrItinClass Itinerary = itin;
 351   bit hasSideEffects = 1;
 352   string BaseOpcode = instr_asm;
 353 }
 354
 355 class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 356                    InstrItinClass itin> {
 357   dag OutOperandList = (outs GPR32Opnd:$rd);
 358   dag InOperandList = (ins PtrRC:$base, PtrRC:$index);
 359   string AsmString = !strconcat(instr_asm, "\t$rd, ${index}(${base})");
 360   list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode iPTR:$base, iPTR:$index))];
 361   InstrItinClass Itinerary = itin;
 362   bit mayLoad = 1;
 363   string BaseOpcode = instr_asm;
 364 }
 365
 366 class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 367                          InstrItinClass itin, RegisterOperand ROD,
 368                          RegisterOperand ROS = ROD,  RegisterOperand ROT = ROD> {
 369   dag OutOperandList = (outs ROD:$rd);
 370   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 371   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 372   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
 373   InstrItinClass Itinerary = itin;
 374   string BaseOpcode = instr_asm;
 375 }
 376
 377 class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 378                        Operand ImmOp, SDPatternOperator Imm, InstrItinClass itin> {
 379   dag OutOperandList = (outs GPR32Opnd:$rt);
 380   dag InOperandList = (ins GPR32Opnd:$rs, ImmOp:$sa, GPR32Opnd:$src);
 381   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
 382   list<dag> Pattern =  [(set GPR32Opnd:$rt,
 383                         (OpNode GPR32Opnd:$src, GPR32Opnd:$rs, Imm:$sa))];
 384   InstrItinClass Itinerary = itin;
 385   string Constraints = "$src = $rt";
 386 }
 387
 388 class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 389                               InstrItinClass itin> {
 390   dag OutOperandList = (outs GPR32Opnd:$rt);
 391   dag InOperandList = (ins ACC64DSPOpnd:$ac, GPR32Opnd:$shift_rs);
 392   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 393   InstrItinClass Itinerary = itin;
 394   string BaseOpcode = instr_asm;
 395 }
 396
 397 class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 398                               InstrItinClass itin> {
 399   dag OutOperandList = (outs GPR32Opnd:$rt);
 400   dag InOperandList = (ins ACC64DSPOpnd:$ac, uimm16:$shift_rs);
 401   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 402   InstrItinClass Itinerary = itin;
 403   string BaseOpcode = instr_asm;
 404 }
 405
 406 class SHILO_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 407   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 408   dag InOperandList = (ins simm16:$shift, ACC64DSPOpnd:$acin);
 409   string AsmString = !strconcat(instr_asm, "\t$ac, $shift");
 410   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 411                         (OpNode immSExt6:$shift, ACC64DSPOpnd:$acin))];
 412   string Constraints = "$acin = $ac";
 413 }
 414
 415 class SHILO_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 416   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 417   dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin);
 418   string AsmString = !strconcat(instr_asm, "\t$ac, $rs");
 419   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 420                         (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))];
 421   string Constraints = "$acin = $ac";
 422 }
 423
 424 class MTHLIP_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 425   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 426   dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin);
 427   string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
 428   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 429                         (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))];
 430   string Constraints = "$acin = $ac";
 431 }
 432
 433 class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 434                       InstrItinClass itin> {
 435   dag OutOperandList = (outs GPR32Opnd:$rd);
 436   dag InOperandList = (ins uimm16:$mask);
 437   string AsmString = !strconcat(instr_asm, "\t$rd, $mask");
 438   list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode immZExt10:$mask))];
 439   InstrItinClass Itinerary = itin;
 440 }
 441
 442 class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 443                       InstrItinClass itin> {
 444   dag OutOperandList = (outs);
 445   dag InOperandList = (ins GPR32Opnd:$rs, uimm16:$mask);
 446   string AsmString = !strconcat(instr_asm, "\t$rs, $mask");
 447   list<dag> Pattern = [(OpNode GPR32Opnd:$rs, immZExt10:$mask)];
 448   InstrItinClass Itinerary = itin;
 449 }
 450
 451 class DPA_W_PH_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 452   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 453   dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin);
 454   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 455   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 456                         (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))];
 457   string Constraints = "$acin = $ac";
 458   string BaseOpcode = instr_asm;
 459 }
 460
 461 class MULT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 462                      InstrItinClass itin> {
 463   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 464   dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt);
 465   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 466   list<dag> Pattern = [(set ACC64DSPOpnd:$ac, (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt))];
 467   InstrItinClass Itinerary = itin;
 468   bit isCommutable = 1;
 469   string BaseOpcode = instr_asm;
 470 }
 471
 472 class MADD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 473                      InstrItinClass itin> {
 474   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 475   dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin);
 476   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 477   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 478                         (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))];
 479   InstrItinClass Itinerary = itin;
 480   string Constraints = "$acin = $ac";
 481   string BaseOpcode = instr_asm;
 482 }
 483
 484 class MFHI_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,
 485                      InstrItinClass itin> {
 486   dag OutOperandList = (outs GPR32Opnd:$rd);
 487   dag InOperandList = (ins RO:$ac);
 488   string AsmString = !strconcat(instr_asm, "\t$rd, $ac");
 489   list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode RO:$ac))];
 490   InstrItinClass Itinerary = itin;
 491   string BaseOpcode = instr_asm;
 492 }
 493
 494 class MTHI_DESC_BASE<string instr_asm, RegisterOperand RO, InstrItinClass itin> {
 495   dag OutOperandList = (outs RO:$ac);
 496   dag InOperandList = (ins GPR32Opnd:$rs);
 497   string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
 498   InstrItinClass Itinerary = itin;
 499   string BaseOpcode = instr_asm;
 500 }
 501
 502 class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> :
 503   MipsPseudo<(outs GPR32Opnd:$dst), (ins), [(set GPR32Opnd:$dst, (OpNode))]> {
 504   bit usesCustomInserter = 1;
 505 }
 506
 507 class BPOSGE32_DESC_BASE<string instr_asm, InstrItinClass itin> {
 508   dag OutOperandList = (outs);
 509   dag InOperandList = (ins brtarget:$offset);
 510   string AsmString = !strconcat(instr_asm, "\t$offset");
 511   InstrItinClass Itinerary = itin;
 512   bit isBranch = 1;
 513   bit isTerminator = 1;
 514   bit hasDelaySlot = 1;
 515 }
 516
 517 class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 518                      InstrItinClass itin> {
 519   dag OutOperandList = (outs GPR32Opnd:$rt);
 520   dag InOperandList = (ins GPR32Opnd:$src, GPR32Opnd:$rs);
 521   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 522   list<dag> Pattern = [(set GPR32Opnd:$rt, (OpNode GPR32Opnd:$src, GPR32Opnd:$rs))];
 523   InstrItinClass Itinerary = itin;
 524   string Constraints = "$src = $rt";
 525   string BaseOpcode = instr_asm;
 526 }
 527
 528 //===----------------------------------------------------------------------===//
 529 // MIPS DSP Rev 1
 530 //===----------------------------------------------------------------------===//
 531
 532 // Addition/subtraction
 533 class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", null_frag, NoItinerary,
 534                                        DSPROpnd, DSPROpnd>, IsCommutable,
 535                      Defs<[DSPOutFlag20]>;
 536
 537 class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb,
 538                                          NoItinerary, DSPROpnd, DSPROpnd>,
 539                        IsCommutable, Defs<[DSPOutFlag20]>;
 540
 541 class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", null_frag, NoItinerary,
 542                                        DSPROpnd, DSPROpnd>,
 543                      Defs<[DSPOutFlag20]>;
 544
 545 class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb,
 546                                          NoItinerary, DSPROpnd, DSPROpnd>,
 547                        Defs<[DSPOutFlag20]>;
 548
 549 class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", null_frag, NoItinerary,
 550                                        DSPROpnd, DSPROpnd>, IsCommutable,
 551                      Defs<[DSPOutFlag20]>;
 552
 553 class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph,
 554                                          NoItinerary, DSPROpnd, DSPROpnd>,
 555                        IsCommutable, Defs<[DSPOutFlag20]>;
 556
 557 class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", null_frag, NoItinerary,
 558                                        DSPROpnd, DSPROpnd>,
 559                      Defs<[DSPOutFlag20]>;
 560
 561 class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph,
 562                                          NoItinerary, DSPROpnd, DSPROpnd>,
 563                        Defs<[DSPOutFlag20]>;
 564
 565 class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w,
 566                                         NoItinerary, GPR32Opnd, GPR32Opnd>,
 567                       IsCommutable, Defs<[DSPOutFlag20]>;
 568
 569 class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w,
 570                                         NoItinerary, GPR32Opnd, GPR32Opnd>,
 571                       Defs<[DSPOutFlag20]>;
 572
 573 class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", null_frag, NoItinerary,
 574                                      GPR32Opnd, GPR32Opnd>, IsCommutable,
 575                    Defs<[DSPCarry]>;
 576
 577 class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", null_frag, NoItinerary,
 578                                      GPR32Opnd, GPR32Opnd>,
 579                    IsCommutable, Uses<[DSPCarry]>, Defs<[DSPOutFlag20]>;
 580
 581 class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub, NoItinerary,
 582                                       GPR32Opnd, GPR32Opnd>;
 583
 584 class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb,
 585                                              NoItinerary, GPR32Opnd, DSPROpnd>;
 586
 587 // Absolute value
 588 class ABSQ_S_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.ph", int_mips_absq_s_ph,
 589                                               NoItinerary, DSPROpnd>,
 590                        Defs<[DSPOutFlag20]>;
 591
 592 class ABSQ_S_W_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.w", int_mips_absq_s_w,
 593                                              NoItinerary, GPR32Opnd>,
 594                       Defs<[DSPOutFlag20]>;
 595
 596 // Precision reduce/expand
 597 class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph",
 598                                                  int_mips_precrq_qb_ph,
 599                                                  NoItinerary, DSPROpnd, DSPROpnd>;
 600
 601 class PRECRQ_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.ph.w",
 602                                                 int_mips_precrq_ph_w,
 603                                                 NoItinerary, DSPROpnd, GPR32Opnd>;
 604
 605 class PRECRQ_RS_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq_rs.ph.w",
 606                                                    int_mips_precrq_rs_ph_w,
 607                                                    NoItinerary, DSPROpnd,
 608                                                    GPR32Opnd>,
 609                             Defs<[DSPOutFlag22]>;
 610
 611 class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph",
 612                                                     int_mips_precrqu_s_qb_ph,
 613                                                     NoItinerary, DSPROpnd,
 614                                                     DSPROpnd>,
 615                              Defs<[DSPOutFlag22]>;
 616
 617 class PRECEQ_W_PHL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phl",
 618                                                  int_mips_preceq_w_phl,
 619                                                  NoItinerary, GPR32Opnd, DSPROpnd>;
 620
 621 class PRECEQ_W_PHR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phr",
 622                                                  int_mips_preceq_w_phr,
 623                                                  NoItinerary, GPR32Opnd, DSPROpnd>;
 624
 625 class PRECEQU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbl",
 626                                                    int_mips_precequ_ph_qbl,
 627                                                    NoItinerary, DSPROpnd>;
 628
 629 class PRECEQU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbr",
 630                                                    int_mips_precequ_ph_qbr,
 631                                                    NoItinerary, DSPROpnd>;
 632
 633 class PRECEQU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbla",
 634                                                     int_mips_precequ_ph_qbla,
 635                                                     NoItinerary, DSPROpnd>;
 636
 637 class PRECEQU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbra",
 638                                                     int_mips_precequ_ph_qbra,
 639                                                     NoItinerary, DSPROpnd>;
 640
 641 class PRECEU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbl",
 642                                                   int_mips_preceu_ph_qbl,
 643                                                   NoItinerary, DSPROpnd>;
 644
 645 class PRECEU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbr",
 646                                                   int_mips_preceu_ph_qbr,
 647                                                   NoItinerary, DSPROpnd>;
 648
 649 class PRECEU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbla",
 650                                                    int_mips_preceu_ph_qbla,
 651                                                    NoItinerary, DSPROpnd>;
 652
 653 class PRECEU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbra",
 654                                                    int_mips_preceu_ph_qbra,
 655                                                    NoItinerary, DSPROpnd>;
 656
 657 // Shift
 658 class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", null_frag, immZExt3,
 659                                           NoItinerary, DSPROpnd, uimm3>,
 660                      Defs<[DSPOutFlag22]>;
 661
 662 class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb,
 663                                            NoItinerary, DSPROpnd>,
 664                       Defs<[DSPOutFlag22]>;
 665
 666 class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", null_frag, immZExt3,
 667                                           NoItinerary, DSPROpnd, uimm3>;
 668
 669 class SHRLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.qb", int_mips_shrl_qb,
 670                                            NoItinerary, DSPROpnd>;
 671
 672 class SHLL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll.ph", null_frag, immZExt4,
 673                                           NoItinerary, DSPROpnd, uimm4>,
 674                      Defs<[DSPOutFlag22]>;
 675
 676 class SHLLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv.ph", int_mips_shll_ph,
 677                                            NoItinerary, DSPROpnd>,
 678                       Defs<[DSPOutFlag22]>;
 679
 680 class SHLL_S_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.ph", int_mips_shll_s_ph,
 681                                             immZExt4, NoItinerary, DSPROpnd,
 682                                             uimm4>,
 683                        Defs<[DSPOutFlag22]>;
 684
 685 class SHLLV_S_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.ph", int_mips_shll_s_ph,
 686                                              NoItinerary, DSPROpnd>,
 687                         Defs<[DSPOutFlag22]>;
 688
 689 class SHRA_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra.ph", null_frag, immZExt4,
 690                                           NoItinerary, DSPROpnd, uimm4>;
 691
 692 class SHRAV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav.ph", int_mips_shra_ph,
 693                                            NoItinerary, DSPROpnd>;
 694
 695 class SHRA_R_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.ph", int_mips_shra_r_ph,
 696                                             immZExt4, NoItinerary, DSPROpnd,
 697                                             uimm4>;
 698
 699 class SHRAV_R_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.ph", int_mips_shra_r_ph,
 700                                              NoItinerary, DSPROpnd>;
 701
 702 class SHLL_S_W_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.w", int_mips_shll_s_w,
 703                                            immZExt5, NoItinerary, GPR32Opnd,
 704                                            uimm5>,
 705                       Defs<[DSPOutFlag22]>;
 706
 707 class SHLLV_S_W_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.w", int_mips_shll_s_w,
 708                                             NoItinerary, GPR32Opnd>,
 709                        Defs<[DSPOutFlag22]>;
 710
 711 class SHRA_R_W_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.w", int_mips_shra_r_w,
 712                                            immZExt5, NoItinerary, GPR32Opnd,
 713                                            uimm5>;
 714
 715 class SHRAV_R_W_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.w", int_mips_shra_r_w,
 716                                             NoItinerary, GPR32Opnd>;
 717
 718 // Multiplication
 719 class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl",
 720                                               int_mips_muleu_s_ph_qbl,
 721                                               NoItinerary, DSPROpnd, DSPROpnd>,
 722                             Defs<[DSPOutFlag21]>;
 723
 724 class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr",
 725                                               int_mips_muleu_s_ph_qbr,
 726                                               NoItinerary, DSPROpnd, DSPROpnd>,
 727                             Defs<[DSPOutFlag21]>;
 728
 729 class MULEQ_S_W_PHL_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phl",
 730                                              int_mips_muleq_s_w_phl,
 731                                              NoItinerary, GPR32Opnd, DSPROpnd>,
 732                            IsCommutable, Defs<[DSPOutFlag21]>;
 733
 734 class MULEQ_S_W_PHR_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phr",
 735                                              int_mips_muleq_s_w_phr,
 736                                              NoItinerary, GPR32Opnd, DSPROpnd>,
 737                            IsCommutable, Defs<[DSPOutFlag21]>;
 738
 739 class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph,
 740                                           NoItinerary, DSPROpnd, DSPROpnd>,
 741                         IsCommutable, Defs<[DSPOutFlag21]>;
 742
 743 class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph",
 744                                               MipsMULSAQ_S_W_PH>,
 745                            Defs<[DSPOutFlag16_19]>;
 746
 747 class MAQ_S_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phl", MipsMAQ_S_W_PHL>,
 748                          Defs<[DSPOutFlag16_19]>;
 749
 750 class MAQ_S_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phr", MipsMAQ_S_W_PHR>,
 751                          Defs<[DSPOutFlag16_19]>;
 752
 753 class MAQ_SA_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phl", MipsMAQ_SA_W_PHL>,
 754                           Defs<[DSPOutFlag16_19]>;
 755
 756 class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr", MipsMAQ_SA_W_PHR>,
 757                           Defs<[DSPOutFlag16_19]>;
 758
 759 // Move from/to hi/lo.
 760 class MFHI_DESC : MFHI_DESC_BASE<"mfhi", ACC64DSPOpnd, MipsMFHI, NoItinerary>;
 761 class MFLO_DESC : MFHI_DESC_BASE<"mflo", ACC64DSPOpnd, MipsMFLO, NoItinerary>;
 762 class MTHI_DESC : MTHI_DESC_BASE<"mthi", HI32DSPOpnd, NoItinerary>;
 763 class MTLO_DESC : MTHI_DESC_BASE<"mtlo", LO32DSPOpnd, NoItinerary>;
 764
 765 // Dot product with accumulate/subtract
 766 class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl", MipsDPAU_H_QBL>;
 767
 768 class DPAU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbr", MipsDPAU_H_QBR>;
 769
 770 class DPSU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbl", MipsDPSU_H_QBL>;
 771
 772 class DPSU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbr", MipsDPSU_H_QBR>;
 773
 774 class DPAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaq_s.w.ph", MipsDPAQ_S_W_PH>,
 775                          Defs<[DSPOutFlag16_19]>;
 776
 777 class DPSQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsq_s.w.ph", MipsDPSQ_S_W_PH>,
 778                          Defs<[DSPOutFlag16_19]>;
 779
 780 class DPAQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpaq_sa.l.w", MipsDPAQ_SA_L_W>,
 781                          Defs<[DSPOutFlag16_19]>;
 782
 783 class DPSQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpsq_sa.l.w", MipsDPSQ_SA_L_W>,
 784                          Defs<[DSPOutFlag16_19]>;
 785
 786 class MULT_DSP_DESC  : MULT_DESC_BASE<"mult", MipsMult, NoItinerary>;
 787 class MULTU_DSP_DESC : MULT_DESC_BASE<"multu", MipsMultu, NoItinerary>;
 788 class MADD_DSP_DESC  : MADD_DESC_BASE<"madd", MipsMAdd, NoItinerary>;
 789 class MADDU_DSP_DESC : MADD_DESC_BASE<"maddu", MipsMAddu, NoItinerary>;
 790 class MSUB_DSP_DESC  : MADD_DESC_BASE<"msub", MipsMSub, NoItinerary>;
 791 class MSUBU_DSP_DESC : MADD_DESC_BASE<"msubu", MipsMSubu, NoItinerary>;
 792
 793 // Comparison
 794 class CMPU_EQ_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.eq.qb",
 795                                                int_mips_cmpu_eq_qb, NoItinerary,
 796                                                DSPROpnd>,
 797                         IsCommutable, Defs<[DSPCCond]>;
 798
 799 class CMPU_LT_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.lt.qb",
 800                                                int_mips_cmpu_lt_qb, NoItinerary,
 801                                                DSPROpnd>, Defs<[DSPCCond]>;
 802
 803 class CMPU_LE_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.le.qb",
 804                                                int_mips_cmpu_le_qb, NoItinerary,
 805                                                DSPROpnd>, Defs<[DSPCCond]>;
 806
 807 class CMPGU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.eq.qb",
 808                                                 int_mips_cmpgu_eq_qb,
 809                                                 NoItinerary, GPR32Opnd, DSPROpnd>,
 810                          IsCommutable;
 811
 812 class CMPGU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.lt.qb",
 813                                                 int_mips_cmpgu_lt_qb,
 814                                                 NoItinerary, GPR32Opnd, DSPROpnd>;
 815
 816 class CMPGU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.le.qb",
 817                                                 int_mips_cmpgu_le_qb,
 818                                                 NoItinerary, GPR32Opnd, DSPROpnd>;
 819
 820 class CMP_EQ_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.eq.ph", int_mips_cmp_eq_ph,
 821                                               NoItinerary, DSPROpnd>,
 822                        IsCommutable, Defs<[DSPCCond]>;
 823
 824 class CMP_LT_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.lt.ph", int_mips_cmp_lt_ph,
 825                                               NoItinerary, DSPROpnd>,
 826                        Defs<[DSPCCond]>;
 827
 828 class CMP_LE_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.le.ph", int_mips_cmp_le_ph,
 829                                               NoItinerary, DSPROpnd>,
 830                        Defs<[DSPCCond]>;
 831
 832 // Misc
 833 class BITREV_DESC : ABSQ_S_PH_R2_DESC_BASE<"bitrev", int_mips_bitrev,
 834                                            NoItinerary, GPR32Opnd>;
 835
 836 class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph,
 837                                               NoItinerary, DSPROpnd, DSPROpnd>;
 838
 839 class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, immZExt8,
 840                                     NoItinerary, DSPROpnd>;
 841
 842 class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, immZExt10,
 843                                     NoItinerary, DSPROpnd>;
 844
 845 class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb,
 846                                              NoItinerary, DSPROpnd, GPR32Opnd>;
 847
 848 class REPLV_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.ph", int_mips_repl_ph,
 849                                              NoItinerary, DSPROpnd, GPR32Opnd>;
 850
 851 class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb,
 852                                             NoItinerary, DSPROpnd, DSPROpnd>,
 853                      Uses<[DSPCCond]>;
 854
 855 class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph,
 856                                             NoItinerary, DSPROpnd, DSPROpnd>,
 857                      Uses<[DSPCCond]>;
 858
 859 class LWX_DESC : LX_DESC_BASE<"lwx", int_mips_lwx, NoItinerary>;
 860
 861 class LHX_DESC : LX_DESC_BASE<"lhx", int_mips_lhx, NoItinerary>;
 862
 863 class LBUX_DESC : LX_DESC_BASE<"lbux", int_mips_lbux, NoItinerary>;
 864
 865 class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", NoItinerary>;
 866
 867 // Extr
 868 class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>,
 869                   Uses<[DSPPos]>, Defs<[DSPEFI]>;
 870
 871 class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>,
 872                    Uses<[DSPPos]>, Defs<[DSPEFI]>;
 873
 874 class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>,
 875                     Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
 876
 877 class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", MipsEXTPDP,
 878                                              NoItinerary>,
 879                      Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
 880
 881 class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>,
 882                     Defs<[DSPOutFlag23]>;
 883
 884 class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", MipsEXTR_W,
 885                                              NoItinerary>, Defs<[DSPOutFlag23]>;
 886
 887 class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", MipsEXTR_R_W,
 888                                               NoItinerary>,
 889                       Defs<[DSPOutFlag23]>;
 890
 891 class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", MipsEXTR_R_W,
 892                                                NoItinerary>,
 893                        Defs<[DSPOutFlag23]>;
 894
 895 class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W,
 896                                                NoItinerary>,
 897                        Defs<[DSPOutFlag23]>;
 898
 899 class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W,
 900                                                 NoItinerary>,
 901                         Defs<[DSPOutFlag23]>;
 902
 903 class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", MipsEXTR_S_H,
 904                                               NoItinerary>,
 905                       Defs<[DSPOutFlag23]>;
 906
 907 class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", MipsEXTR_S_H,
 908                                                NoItinerary>,
 909                        Defs<[DSPOutFlag23]>;
 910
 911 class SHILO_DESC : SHILO_R1_DESC_BASE<"shilo", MipsSHILO>;
 912
 913 class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov", MipsSHILO>;
 914
 915 class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip", MipsMTHLIP>, Defs<[DSPPos]>;
 916
 917 class RDDSP_DESC : RDDSP_DESC_BASE<"rddsp", int_mips_rddsp, NoItinerary>;
 918
 919 class WRDSP_DESC : WRDSP_DESC_BASE<"wrdsp", int_mips_wrdsp, NoItinerary>;
 920
 921 class INSV_DESC : INSV_DESC_BASE<"insv", int_mips_insv, NoItinerary>,
 922                   Uses<[DSPPos, DSPSCount]>;
 923
 924 //===----------------------------------------------------------------------===//
 925 // MIPS DSP Rev 2
 926 // Addition/subtraction
 927 class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph, NoItinerary,
 928                                        DSPROpnd, DSPROpnd>, IsCommutable,
 929                      Defs<[DSPOutFlag20]>;
 930
 931 class ADDU_S_PH_DESC : ADDU_QB_DESC_BASE<"addu_s.ph", int_mips_addu_s_ph,
 932                                          NoItinerary, DSPROpnd, DSPROpnd>,
 933                        IsCommutable, Defs<[DSPOutFlag20]>;
 934
 935 class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary,
 936                                        DSPROpnd, DSPROpnd>,
 937                      Defs<[DSPOutFlag20]>;
 938
 939 class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph,
 940                                          NoItinerary, DSPROpnd, DSPROpnd>,
 941                        Defs<[DSPOutFlag20]>;
 942
 943 class ADDUH_QB_DESC : ADDUH_QB_DESC_BASE<"adduh.qb", int_mips_adduh_qb,
 944                                          NoItinerary, DSPROpnd>, IsCommutable;
 945
 946 class ADDUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"adduh_r.qb", int_mips_adduh_r_qb,
 947                                            NoItinerary, DSPROpnd>, IsCommutable;
 948
 949 class SUBUH_QB_DESC : ADDUH_QB_DESC_BASE<"subuh.qb", int_mips_subuh_qb,
 950                                          NoItinerary, DSPROpnd>;
 951
 952 class SUBUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"subuh_r.qb", int_mips_subuh_r_qb,
 953                                            NoItinerary, DSPROpnd>;
 954
 955 class ADDQH_PH_DESC : ADDUH_QB_DESC_BASE<"addqh.ph", int_mips_addqh_ph,
 956                                          NoItinerary, DSPROpnd>, IsCommutable;
 957
 958 class ADDQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"addqh_r.ph", int_mips_addqh_r_ph,
 959                                            NoItinerary, DSPROpnd>, IsCommutable;
 960
 961 class SUBQH_PH_DESC : ADDUH_QB_DESC_BASE<"subqh.ph", int_mips_subqh_ph,
 962                                          NoItinerary, DSPROpnd>;
 963
 964 class SUBQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"subqh_r.ph", int_mips_subqh_r_ph,
 965                                            NoItinerary, DSPROpnd>;
 966
 967 class ADDQH_W_DESC : ADDUH_QB_DESC_BASE<"addqh.w", int_mips_addqh_w,
 968                                         NoItinerary, GPR32Opnd>, IsCommutable;
 969
 970 class ADDQH_R_W_DESC : ADDUH_QB_DESC_BASE<"addqh_r.w", int_mips_addqh_r_w,
 971                                           NoItinerary, GPR32Opnd>, IsCommutable;
 972
 973 class SUBQH_W_DESC : ADDUH_QB_DESC_BASE<"subqh.w", int_mips_subqh_w,
 974                                         NoItinerary, GPR32Opnd>;
 975
 976 class SUBQH_R_W_DESC : ADDUH_QB_DESC_BASE<"subqh_r.w", int_mips_subqh_r_w,
 977                                           NoItinerary, GPR32Opnd>;
 978
 979 // Comparison
 980 class CMPGDU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.eq.qb",
 981                                                  int_mips_cmpgdu_eq_qb,
 982                                                  NoItinerary, GPR32Opnd, DSPROpnd>,
 983                           IsCommutable, Defs<[DSPCCond]>;
 984
 985 class CMPGDU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.lt.qb",
 986                                                  int_mips_cmpgdu_lt_qb,
 987                                                  NoItinerary, GPR32Opnd, DSPROpnd>,
 988                           Defs<[DSPCCond]>;
 989
 990 class CMPGDU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.le.qb",
 991                                                  int_mips_cmpgdu_le_qb,
 992                                                  NoItinerary, GPR32Opnd, DSPROpnd>,
 993                           Defs<[DSPCCond]>;
 994
 995 // Absolute
 996 class ABSQ_S_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.qb", int_mips_absq_s_qb,
 997                                               NoItinerary, DSPROpnd>,
 998                        Defs<[DSPOutFlag20]>;
 999
1000 // Multiplication
1001 class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", null_frag, NoItinerary,
1002                                        DSPROpnd>, IsCommutable,
1003                     Defs<[DSPOutFlag21]>;
1004
1005 class MUL_S_PH_DESC : ADDUH_QB_DESC_BASE<"mul_s.ph", int_mips_mul_s_ph,
1006                                          NoItinerary, DSPROpnd>, IsCommutable,
1007                       Defs<[DSPOutFlag21]>;
1008
1009 class MULQ_S_W_DESC : ADDUH_QB_DESC_BASE<"mulq_s.w", int_mips_mulq_s_w,
1010                                          NoItinerary, GPR32Opnd>, IsCommutable,
1011                       Defs<[DSPOutFlag21]>;
1012
1013 class MULQ_RS_W_DESC : ADDUH_QB_DESC_BASE<"mulq_rs.w", int_mips_mulq_rs_w,
1014                                           NoItinerary, GPR32Opnd>, IsCommutable,
1015                        Defs<[DSPOutFlag21]>;
1016
1017 class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph,
1018                                          NoItinerary, DSPROpnd, DSPROpnd>,
1019                        IsCommutable, Defs<[DSPOutFlag21]>;
1020
1021 // Dot product with accumulate/subtract
1022 class DPA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpa.w.ph", MipsDPA_W_PH>;
1023
1024 class DPS_W_PH_DESC : DPA_W_PH_DESC_BASE<"dps.w.ph", MipsDPS_W_PH>;
1025
1026 class DPAQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_s.w.ph", MipsDPAQX_S_W_PH>,
1027                           Defs<[DSPOutFlag16_19]>;
1028
1029 class DPAQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_sa.w.ph",
1030                                               MipsDPAQX_SA_W_PH>,
1031                            Defs<[DSPOutFlag16_19]>;
1032
1033 class DPAX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpax.w.ph", MipsDPAX_W_PH>;
1034
1035 class DPSX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsx.w.ph", MipsDPSX_W_PH>;
1036
1037 class DPSQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_s.w.ph", MipsDPSQX_S_W_PH>,
1038                           Defs<[DSPOutFlag16_19]>;
1039
1040 class DPSQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_sa.w.ph",
1041                                               MipsDPSQX_SA_W_PH>,
1042                            Defs<[DSPOutFlag16_19]>;
1043
1044 class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph", MipsMULSA_W_PH>;
1045
1046 // Precision reduce/expand
1047 class PRECR_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precr.qb.ph",
1048                                                 int_mips_precr_qb_ph,
1049                                                 NoItinerary, DSPROpnd, DSPROpnd>;
1050
1051 class PRECR_SRA_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra.ph.w",
1052                                                      int_mips_precr_sra_ph_w,
1053                                                      NoItinerary, DSPROpnd,
1054                                                      GPR32Opnd>;
1055
1056 class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w",
1057                                                       int_mips_precr_sra_r_ph_w,
1058                                                        NoItinerary, DSPROpnd,
1059                                                        GPR32Opnd>;
1060
1061 // Shift
1062 class SHRA_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra.qb", null_frag, immZExt3,
1063                                           NoItinerary, DSPROpnd, uimm3>;
1064
1065 class SHRAV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav.qb", int_mips_shra_qb,
1066                                            NoItinerary, DSPROpnd>;
1067
1068 class SHRA_R_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.qb", int_mips_shra_r_qb,
1069                                             immZExt3, NoItinerary, DSPROpnd,
1070                                             uimm3>;
1071
1072 class SHRAV_R_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.qb", int_mips_shra_r_qb,
1073                                              NoItinerary, DSPROpnd>;
1074
1075 class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", null_frag, immZExt4,
1076                                           NoItinerary, DSPROpnd, uimm4>;
1077
1078 class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph,
1079                                            NoItinerary, DSPROpnd>;
1080
1081 // Misc
1082 class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, uimm5, immZExt5,
1083                                      NoItinerary>;
1084
1085 class BALIGN_DESC : APPEND_DESC_BASE<"balign", int_mips_balign, uimm2, immZExt2,
1086                                      NoItinerary>;
1087
1088 class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, uimm5,
1089                                       immZExt5, NoItinerary>;
1090
1091 // Pseudos.
1092 def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32,
1093                                                 NoItinerary>, Uses<[DSPPos]>;
1094
1095 // Instruction defs.
1096 // MIPS DSP Rev 1
1097 def ADDU_QB : DspMMRel, ADDU_QB_ENC, ADDU_QB_DESC;
1098 def ADDU_S_QB : DspMMRel, ADDU_S_QB_ENC, ADDU_S_QB_DESC;
1099 def SUBU_QB : DspMMRel, SUBU_QB_ENC, SUBU_QB_DESC;
1100 def SUBU_S_QB : DspMMRel, SUBU_S_QB_ENC, SUBU_S_QB_DESC;
1101 def ADDQ_PH : DspMMRel, ADDQ_PH_ENC, ADDQ_PH_DESC;
1102 def ADDQ_S_PH : DspMMRel, ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
1103 def SUBQ_PH : DspMMRel, SUBQ_PH_ENC, SUBQ_PH_DESC;
1104 def SUBQ_S_PH : DspMMRel, SUBQ_S_PH_ENC, SUBQ_S_PH_DESC;
1105 def ADDQ_S_W : DspMMRel, ADDQ_S_W_ENC, ADDQ_S_W_DESC;
1106 def SUBQ_S_W : DspMMRel, SUBQ_S_W_ENC, SUBQ_S_W_DESC;
1107 def ADDSC : DspMMRel, ADDSC_ENC, ADDSC_DESC;
1108 def ADDWC : DspMMRel, ADDWC_ENC, ADDWC_DESC;
1109 def MODSUB : MODSUB_ENC, MODSUB_DESC;
1110 def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC;
1111 def ABSQ_S_PH : DspMMRel, ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
1112 def ABSQ_S_W : DspMMRel, ABSQ_S_W_ENC, ABSQ_S_W_DESC;
1113 def PRECRQ_QB_PH : DspMMRel, PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
1114 def PRECRQ_PH_W : DspMMRel, PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;
1115 def PRECRQ_RS_PH_W : DspMMRel, PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC;
1116 def PRECRQU_S_QB_PH : DspMMRel, PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC;
1117 def PRECEQ_W_PHL : DspMMRel, PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC;
1118 def PRECEQ_W_PHR : DspMMRel, PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC;
1119 def PRECEQU_PH_QBL : DspMMRel, PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC;
1120 def PRECEQU_PH_QBR : DspMMRel, PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC;
1121 def PRECEQU_PH_QBLA : DspMMRel, PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC;
1122 def PRECEQU_PH_QBRA : DspMMRel, PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC;
1123 def PRECEU_PH_QBL : DspMMRel, PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC;
1124 def PRECEU_PH_QBR : DspMMRel, PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC;
1125 def PRECEU_PH_QBLA : DspMMRel, PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC;
1126 def PRECEU_PH_QBRA : DspMMRel, PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC;
1127 def SHLL_QB : DspMMRel, SHLL_QB_ENC, SHLL_QB_DESC;
1128 def SHLLV_QB : DspMMRel, SHLLV_QB_ENC, SHLLV_QB_DESC;
1129 def SHRL_QB : DspMMRel, SHRL_QB_ENC, SHRL_QB_DESC;
1130 def SHRLV_QB : DspMMRel, SHRLV_QB_ENC, SHRLV_QB_DESC;
1131 def SHLL_PH : DspMMRel, SHLL_PH_ENC, SHLL_PH_DESC;
1132 def SHLLV_PH : DspMMRel, SHLLV_PH_ENC, SHLLV_PH_DESC;
1133 def SHLL_S_PH : DspMMRel, SHLL_S_PH_ENC, SHLL_S_PH_DESC;
1134 def SHLLV_S_PH : DspMMRel, SHLLV_S_PH_ENC, SHLLV_S_PH_DESC;
1135 def SHRA_PH : DspMMRel, SHRA_PH_ENC, SHRA_PH_DESC;
1136 def SHRAV_PH : DspMMRel, SHRAV_PH_ENC, SHRAV_PH_DESC;
1137 def SHRA_R_PH : DspMMRel, SHRA_R_PH_ENC, SHRA_R_PH_DESC;
1138 def SHRAV_R_PH : DspMMRel, SHRAV_R_PH_ENC, SHRAV_R_PH_DESC;
1139 def SHLL_S_W : DspMMRel, SHLL_S_W_ENC, SHLL_S_W_DESC;
1140 def SHLLV_S_W : DspMMRel, SHLLV_S_W_ENC, SHLLV_S_W_DESC;
1141 def SHRA_R_W : DspMMRel, SHRA_R_W_ENC, SHRA_R_W_DESC;
1142 def SHRAV_R_W : DspMMRel, SHRAV_R_W_ENC, SHRAV_R_W_DESC;
1143 def MULEU_S_PH_QBL : DspMMRel, MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC;
1144 def MULEU_S_PH_QBR : DspMMRel, MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC;
1145 def MULEQ_S_W_PHL : DspMMRel, MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC;
1146 def MULEQ_S_W_PHR : DspMMRel, MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC;
1147 def MULQ_RS_PH : DspMMRel, MULQ_RS_PH_ENC, MULQ_RS_PH_DESC;
1148 def MULSAQ_S_W_PH : MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC;
1149 def MAQ_S_W_PHL : DspMMRel, MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC;
1150 def MAQ_S_W_PHR : DspMMRel, MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC;
1151 def MAQ_SA_W_PHL : DspMMRel, MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC;
1152 def MAQ_SA_W_PHR : DspMMRel, MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC;
1153 def MFHI_DSP : DspMMRel, MFHI_ENC, MFHI_DESC;
1154 def MFLO_DSP : DspMMRel, MFLO_ENC, MFLO_DESC;
1155 def MTHI_DSP : DspMMRel, MTHI_ENC, MTHI_DESC;
1156 def MTLO_DSP : DspMMRel, MTLO_ENC, MTLO_DESC;
1157 def DPAU_H_QBL : DspMMRel, DPAU_H_QBL_ENC, DPAU_H_QBL_DESC;
1158 def DPAU_H_QBR : DspMMRel, DPAU_H_QBR_ENC, DPAU_H_QBR_DESC;
1159 def DPSU_H_QBL : DspMMRel, DPSU_H_QBL_ENC, DPSU_H_QBL_DESC;
1160 def DPSU_H_QBR : DspMMRel, DPSU_H_QBR_ENC, DPSU_H_QBR_DESC;
1161 def DPAQ_S_W_PH : DspMMRel, DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC;
1162 def DPSQ_S_W_PH : DspMMRel, DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC;
1163 def DPAQ_SA_L_W : DspMMRel, DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC;
1164 def DPSQ_SA_L_W : DspMMRel, DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC;
1165 def MULT_DSP : DspMMRel, MULT_DSP_ENC, MULT_DSP_DESC;
1166 def MULTU_DSP : DspMMRel, MULTU_DSP_ENC, MULTU_DSP_DESC;
1167 def MADD_DSP : DspMMRel, MADD_DSP_ENC, MADD_DSP_DESC;
1168 def MADDU_DSP : DspMMRel, MADDU_DSP_ENC, MADDU_DSP_DESC;
1169 def MSUB_DSP : DspMMRel, MSUB_DSP_ENC, MSUB_DSP_DESC;
1170 def MSUBU_DSP : DspMMRel, MSUBU_DSP_ENC, MSUBU_DSP_DESC;
1171 def CMPU_EQ_QB : CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC;
1172 def CMPU_LT_QB : CMPU_LT_QB_ENC, CMPU_LT_QB_DESC;
1173 def CMPU_LE_QB : CMPU_LE_QB_ENC, CMPU_LE_QB_DESC;
1174 def CMPGU_EQ_QB : CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC;
1175 def CMPGU_LT_QB : CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC;
1176 def CMPGU_LE_QB : CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC;
1177 def CMP_EQ_PH : CMP_EQ_PH_ENC, CMP_EQ_PH_DESC;
1178 def CMP_LT_PH : CMP_LT_PH_ENC, CMP_LT_PH_DESC;
1179 def CMP_LE_PH : CMP_LE_PH_ENC, CMP_LE_PH_DESC;
1180 def BITREV : BITREV_ENC, BITREV_DESC;
1181 def PACKRL_PH : PACKRL_PH_ENC, PACKRL_PH_DESC;
1182 def REPL_QB : REPL_QB_ENC, REPL_QB_DESC;
1183 def REPL_PH : REPL_PH_ENC, REPL_PH_DESC;
1184 def REPLV_QB : REPLV_QB_ENC, REPLV_QB_DESC;
1185 def REPLV_PH : REPLV_PH_ENC, REPLV_PH_DESC;
1186 def PICK_QB : PICK_QB_ENC, PICK_QB_DESC;
1187 def PICK_PH : PICK_PH_ENC, PICK_PH_DESC;
1188 def LWX : DspMMRel, LWX_ENC, LWX_DESC;
1189 def LHX : DspMMRel, LHX_ENC, LHX_DESC;
1190 def LBUX : DspMMRel, LBUX_ENC, LBUX_DESC;
1191 def BPOSGE32 : BPOSGE32_ENC, BPOSGE32_DESC;
1192 def INSV : DspMMRel, INSV_ENC, INSV_DESC;
1193 def EXTP : DspMMRel, EXTP_ENC, EXTP_DESC;
1194 def EXTPV : DspMMRel, EXTPV_ENC, EXTPV_DESC;
1195 def EXTPDP : DspMMRel, EXTPDP_ENC, EXTPDP_DESC;
1196 def EXTPDPV : DspMMRel, EXTPDPV_ENC, EXTPDPV_DESC;
1197 def EXTR_W : DspMMRel, EXTR_W_ENC, EXTR_W_DESC;
1198 def EXTRV_W : DspMMRel, EXTRV_W_ENC, EXTRV_W_DESC;
1199 def EXTR_R_W : DspMMRel, EXTR_R_W_ENC, EXTR_R_W_DESC;
1200 def EXTRV_R_W : DspMMRel, EXTRV_R_W_ENC, EXTRV_R_W_DESC;
1201 def EXTR_RS_W : DspMMRel, EXTR_RS_W_ENC, EXTR_RS_W_DESC;
1202 def EXTRV_RS_W : DspMMRel, EXTRV_RS_W_ENC, EXTRV_RS_W_DESC;
1203 def EXTR_S_H : DspMMRel, EXTR_S_H_ENC, EXTR_S_H_DESC;
1204 def EXTRV_S_H : DspMMRel, EXTRV_S_H_ENC, EXTRV_S_H_DESC;
1205 def SHILO : SHILO_ENC, SHILO_DESC;
1206 def SHILOV : SHILOV_ENC, SHILOV_DESC;
1207 def MTHLIP : MTHLIP_ENC, MTHLIP_DESC;
1208 def RDDSP : RDDSP_ENC, RDDSP_DESC;
1209 def WRDSP : WRDSP_ENC, WRDSP_DESC;
1210
1211 // MIPS DSP Rev 2
1212 let Predicates = [HasDSPR2] in {
1213
1214 def ADDU_PH : DspMMRel, ADDU_PH_ENC, ADDU_PH_DESC;
1215 def ADDU_S_PH : DspMMRel, ADDU_S_PH_ENC, ADDU_S_PH_DESC;
1216 def SUBU_PH : DspMMRel, SUBU_PH_ENC, SUBU_PH_DESC;
1217 def SUBU_S_PH : DspMMRel, SUBU_S_PH_ENC, SUBU_S_PH_DESC;
1218 def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC;
1219 def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC;
1220 def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC;
1221 def ABSQ_S_QB : DspMMRel, ABSQ_S_QB_ENC, ABSQ_S_QB_DESC;
1222 def ADDUH_QB : DspMMRel, ADDUH_QB_ENC, ADDUH_QB_DESC;
1223 def ADDUH_R_QB : DspMMRel, ADDUH_R_QB_ENC, ADDUH_R_QB_DESC;
1224 def SUBUH_QB : DspMMRel, SUBUH_QB_ENC, SUBUH_QB_DESC;
1225 def SUBUH_R_QB : DspMMRel, SUBUH_R_QB_ENC, SUBUH_R_QB_DESC;
1226 def ADDQH_PH : DspMMRel, ADDQH_PH_ENC, ADDQH_PH_DESC;
1227 def ADDQH_R_PH : DspMMRel, ADDQH_R_PH_ENC, ADDQH_R_PH_DESC;
1228 def SUBQH_PH : DspMMRel, SUBQH_PH_ENC, SUBQH_PH_DESC;
1229 def SUBQH_R_PH : DspMMRel, SUBQH_R_PH_ENC, SUBQH_R_PH_DESC;
1230 def ADDQH_W : DspMMRel, ADDQH_W_ENC, ADDQH_W_DESC;
1231 def ADDQH_R_W : DspMMRel, ADDQH_R_W_ENC, ADDQH_R_W_DESC;
1232 def SUBQH_W : DspMMRel, SUBQH_W_ENC, SUBQH_W_DESC;
1233 def SUBQH_R_W : DspMMRel, SUBQH_R_W_ENC, SUBQH_R_W_DESC;
1234 def MUL_PH : DspMMRel, MUL_PH_ENC, MUL_PH_DESC;
1235 def MUL_S_PH : DspMMRel, MUL_S_PH_ENC, MUL_S_PH_DESC;
1236 def MULQ_S_W : DspMMRel, MULQ_S_W_ENC, MULQ_S_W_DESC;
1237 def MULQ_RS_W : DspMMRel, MULQ_RS_W_ENC, MULQ_RS_W_DESC;
1238 def MULQ_S_PH : DspMMRel, MULQ_S_PH_ENC, MULQ_S_PH_DESC;
1239 def DPA_W_PH : DspMMRel, DPA_W_PH_ENC, DPA_W_PH_DESC;
1240 def DPS_W_PH : DspMMRel, DPS_W_PH_ENC, DPS_W_PH_DESC;
1241 def DPAQX_S_W_PH : DspMMRel, DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC;
1242 def DPAQX_SA_W_PH : DspMMRel, DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC;
1243 def DPAX_W_PH : DspMMRel, DPAX_W_PH_ENC, DPAX_W_PH_DESC;
1244 def DPSX_W_PH : DspMMRel, DPSX_W_PH_ENC, DPSX_W_PH_DESC;
1245 def DPSQX_S_W_PH : DspMMRel, DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC;
1246 def DPSQX_SA_W_PH : DspMMRel, DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC;
1247 def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC;
1248 def PRECR_QB_PH : DspMMRel, PRECR_QB_PH_ENC, PRECR_QB_PH_DESC;
1249 def PRECR_SRA_PH_W : DspMMRel, PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC;
1250 def PRECR_SRA_R_PH_W : DspMMRel, PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC;
1251 def SHRA_QB : DspMMRel, SHRA_QB_ENC, SHRA_QB_DESC;
1252 def SHRAV_QB : DspMMRel, SHRAV_QB_ENC, SHRAV_QB_DESC;
1253 def SHRA_R_QB : DspMMRel, SHRA_R_QB_ENC, SHRA_R_QB_DESC;
1254 def SHRAV_R_QB : DspMMRel, SHRAV_R_QB_ENC, SHRAV_R_QB_DESC;
1255 def SHRL_PH : DspMMRel, SHRL_PH_ENC, SHRL_PH_DESC;
1256 def SHRLV_PH : DspMMRel, SHRLV_PH_ENC, SHRLV_PH_DESC;
1257 def APPEND : APPEND_ENC, APPEND_DESC;
1258 def BALIGN : BALIGN_ENC, BALIGN_DESC;
1259 def PREPEND : PREPEND_ENC, PREPEND_DESC;
1260
1261 }
1262
1263 // Pseudos.
1264 let isPseudo = 1, isCodeGenOnly = 1 in {
1265   // Pseudo instructions for loading and storing accumulator registers.
1266   def LOAD_ACC64DSP  : Load<"", ACC64DSPOpnd>;
1267   def STORE_ACC64DSP : Store<"", ACC64DSPOpnd>;
1268
1269   // Pseudos for loading and storing ccond field of DSP control register.
1270   def LOAD_CCOND_DSP  : Load<"load_ccond_dsp", DSPCC>;
1271   def STORE_CCOND_DSP : Store<"store_ccond_dsp", DSPCC>;
1272 }
1273
1274 // Pseudo CMP and PICK instructions.
1275 class PseudoCMP<Instruction RealInst> :
1276   PseudoDSP<(outs DSPCC:$cmp), (ins DSPROpnd:$rs, DSPROpnd:$rt), []>,
1277   PseudoInstExpansion<(RealInst DSPROpnd:$rs, DSPROpnd:$rt)>, NeverHasSideEffects;
1278
1279 class PseudoPICK<Instruction RealInst> :
1280   PseudoDSP<(outs DSPROpnd:$rd), (ins DSPCC:$cmp, DSPROpnd:$rs, DSPROpnd:$rt), []>,
1281   PseudoInstExpansion<(RealInst DSPROpnd:$rd, DSPROpnd:$rs, DSPROpnd:$rt)>,
1282   NeverHasSideEffects;
1283
1284 def PseudoCMP_EQ_PH : PseudoCMP<CMP_EQ_PH>;
1285 def PseudoCMP_LT_PH : PseudoCMP<CMP_LT_PH>;
1286 def PseudoCMP_LE_PH : PseudoCMP<CMP_LE_PH>;
1287 def PseudoCMPU_EQ_QB : PseudoCMP<CMPU_EQ_QB>;
1288 def PseudoCMPU_LT_QB : PseudoCMP<CMPU_LT_QB>;
1289 def PseudoCMPU_LE_QB : PseudoCMP<CMPU_LE_QB>;
1290
1291 def PseudoPICK_PH : PseudoPICK<PICK_PH>;
1292 def PseudoPICK_QB : PseudoPICK<PICK_QB>;
1293
1294 def PseudoMTLOHI_DSP : PseudoMTLOHI<ACC64DSP, GPR32>;
1295
1296 // Patterns.
1297 class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :
1298   Pat<pattern, result>, Requires<[pred]>;
1299
1300 class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
1301                     RegisterClass SrcRC> :
1302    DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
1303           (COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
1304
1305 def : BitconvertPat<i32, v2i16, GPR32, DSPR>;
1306 def : BitconvertPat<i32, v4i8, GPR32, DSPR>;
1307 def : BitconvertPat<v2i16, i32, DSPR, GPR32>;
1308 def : BitconvertPat<v4i8, i32, DSPR, GPR32>;
1309
1310 def : DSPPat<(v2i16 (load addr:$a)),
1311              (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1312 def : DSPPat<(v4i8 (load addr:$a)),
1313              (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1314 def : DSPPat<(store (v2i16 DSPR:$val), addr:$a),
1315              (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1316 def : DSPPat<(store (v4i8 DSPR:$val), addr:$a),
1317              (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1318
1319 // Binary operations.
1320 class DSPBinPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
1321                 Predicate Pred = HasDSP> :
1322   DSPPat<(Node ValTy:$a, ValTy:$b), (Inst ValTy:$a, ValTy:$b), Pred>;
1323
1324 def : DSPBinPat<ADDQ_PH, v2i16, int_mips_addq_ph>;
1325 def : DSPBinPat<ADDQ_PH, v2i16, add>;
1326 def : DSPBinPat<SUBQ_PH, v2i16, int_mips_subq_ph>;
1327 def : DSPBinPat<SUBQ_PH, v2i16, sub>;
1328 def : DSPBinPat<MUL_PH, v2i16, int_mips_mul_ph, HasDSPR2>;
1329 def : DSPBinPat<MUL_PH, v2i16, mul, HasDSPR2>;
1330 def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>;
1331 def : DSPBinPat<ADDU_QB, v4i8, add>;
1332 def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>;
1333 def : DSPBinPat<SUBU_QB, v4i8, sub>;
1334 def : DSPBinPat<ADDSC, i32, int_mips_addsc>;
1335 def : DSPBinPat<ADDSC, i32, addc>;
1336 def : DSPBinPat<ADDWC, i32, int_mips_addwc>;
1337 def : DSPBinPat<ADDWC, i32, adde>;
1338
1339 // Shift immediate patterns.
1340 class DSPShiftPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
1341                   SDPatternOperator Imm, Predicate Pred = HasDSP> :
1342   DSPPat<(Node ValTy:$a, Imm:$shamt), (Inst ValTy:$a, Imm:$shamt), Pred>;
1343
1344 def : DSPShiftPat<SHLL_PH, v2i16, MipsSHLL_DSP, imm>;
1345 def : DSPShiftPat<SHRA_PH, v2i16, MipsSHRA_DSP, imm>;
1346 def : DSPShiftPat<SHRL_PH, v2i16, MipsSHRL_DSP, imm, HasDSPR2>;
1347 def : DSPShiftPat<SHLL_PH, v2i16, int_mips_shll_ph, immZExt4>;
1348 def : DSPShiftPat<SHRA_PH, v2i16, int_mips_shra_ph, immZExt4>;
1349 def : DSPShiftPat<SHRL_PH, v2i16, int_mips_shrl_ph, immZExt4, HasDSPR2>;
1350 def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, imm>;
1351 def : DSPShiftPat<SHRA_QB, v4i8, MipsSHRA_DSP, imm, HasDSPR2>;
1352 def : DSPShiftPat<SHRL_QB, v4i8, MipsSHRL_DSP, imm>;
1353 def : DSPShiftPat<SHLL_QB, v4i8, int_mips_shll_qb, immZExt3>;
1354 def : DSPShiftPat<SHRA_QB, v4i8, int_mips_shra_qb, immZExt3, HasDSPR2>;
1355 def : DSPShiftPat<SHRL_QB, v4i8, int_mips_shrl_qb, immZExt3>;
1356
1357 // SETCC/SELECT_CC patterns.
1358 class DSPSetCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
1359                   CondCode CC> :
1360   DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
1361          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
1362                       (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR)),
1363                       (ValTy ZERO)))>;
1364
1365 class DSPSetCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
1366                      CondCode CC> :
1367   DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
1368          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
1369                       (ValTy ZERO),
1370                       (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR))))>;
1371
1372 class DSPSelectCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
1373                      CondCode CC> :
1374   DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),
1375          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $c, $d))>;
1376
1377 class DSPSelectCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
1378                         CondCode CC> :
1379   DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),
1380          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $d, $c))>;
1381
1382 def : DSPSetCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1383 def : DSPSetCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1384 def : DSPSetCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
1385 def : DSPSetCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1386 def : DSPSetCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
1387 def : DSPSetCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;
1388 def : DSPSetCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1389 def : DSPSetCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1390 def : DSPSetCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1391 def : DSPSetCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1392 def : DSPSetCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1393 def : DSPSetCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1394
1395 def : DSPSelectCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1396 def : DSPSelectCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1397 def : DSPSelectCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
1398 def : DSPSelectCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1399 def : DSPSelectCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
1400 def : DSPSelectCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;
1401 def : DSPSelectCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1402 def : DSPSelectCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1403 def : DSPSelectCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1404 def : DSPSelectCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1405 def : DSPSelectCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1406 def : DSPSelectCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1407
1408 // Extr patterns.
1409 class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> :
1410   DSPPat<(i32 (OpNode GPR32:$rs, ACC64DSP:$ac)),
1411          (Instr ACC64DSP:$ac, GPR32:$rs)>;
1412
1413 class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> :
1414   DSPPat<(i32 (OpNode immZExt5:$shift, ACC64DSP:$ac)),
1415          (Instr ACC64DSP:$ac, immZExt5:$shift)>;
1416
1417 def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>;
1418 def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>;
1419 def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>;
1420 def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>;
1421 def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>;
1422 def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>;
1423 def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>;
1424 def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>;
1425 def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>;
1426 def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>;
1427 def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>;
1428 def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>;
1429
1430 // Indexed load patterns.
1431 class IndexedLoadPat<SDPatternOperator LoadNode, Instruction Instr> :
1432   DSPPat<(i32 (LoadNode (add i32:$base, i32:$index))),
1433          (Instr i32:$base, i32:$index)>;
1434
1435 let AddedComplexity = 20 in {
1436   def : IndexedLoadPat<zextloadi8, LBUX>;
1437   def : IndexedLoadPat<sextloadi16, LHX>;
1438   def : IndexedLoadPat<load, LWX>;
1439 }