lib/Target/Mips/MipsDSPInstrInfo.td

   1 //===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes Mips DSP ASE instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // ImmLeaf
  15 def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>;
  16 def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>;
  17 def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>;
  18 def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>;
  19 def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>;
  20 def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>;
  21
  22 // Mips-specific dsp nodes
  23 def SDT_MipsExtr : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
  24                                         SDTCisVT<2, untyped>]>;
  25 def SDT_MipsShilo : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
  26                                          SDTCisSameAs<0, 2>, SDTCisVT<1, i32>]>;
  27 def SDT_MipsDPA : SDTypeProfile<1, 3, [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
  28                                        SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
  29 def SDT_MipsSHIFT_DSP : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
  30                                              SDTCisVT<2, i32>]>;
  31
  32 class MipsDSPBase<string Opc, SDTypeProfile Prof> :
  33   SDNode<!strconcat("MipsISD::", Opc), Prof>;
  34
  35 class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> :
  36   SDNode<!strconcat("MipsISD::", Opc), Prof, [SDNPHasChain, SDNPSideEffect]>;
  37
  38 def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>;
  39 def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>;
  40 def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>;
  41 def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>;
  42 def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>;
  43 def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>;
  44
  45 def MipsSHILO : MipsDSPBase<"SHILO", SDT_MipsShilo>;
  46 def MipsMTHLIP : MipsDSPSideEffectBase<"MTHLIP", SDT_MipsShilo>;
  47
  48 def MipsMULSAQ_S_W_PH : MipsDSPSideEffectBase<"MULSAQ_S_W_PH", SDT_MipsDPA>;
  49 def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>;
  50 def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>;
  51 def MipsMAQ_SA_W_PHL : MipsDSPSideEffectBase<"MAQ_SA_W_PHL", SDT_MipsDPA>;
  52 def MipsMAQ_SA_W_PHR : MipsDSPSideEffectBase<"MAQ_SA_W_PHR", SDT_MipsDPA>;
  53
  54 def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>;
  55 def MipsDPAU_H_QBR : MipsDSPBase<"DPAU_H_QBR", SDT_MipsDPA>;
  56 def MipsDPSU_H_QBL : MipsDSPBase<"DPSU_H_QBL", SDT_MipsDPA>;
  57 def MipsDPSU_H_QBR : MipsDSPBase<"DPSU_H_QBR", SDT_MipsDPA>;
  58 def MipsDPAQ_S_W_PH : MipsDSPSideEffectBase<"DPAQ_S_W_PH", SDT_MipsDPA>;
  59 def MipsDPSQ_S_W_PH : MipsDSPSideEffectBase<"DPSQ_S_W_PH", SDT_MipsDPA>;
  60 def MipsDPAQ_SA_L_W : MipsDSPSideEffectBase<"DPAQ_SA_L_W", SDT_MipsDPA>;
  61 def MipsDPSQ_SA_L_W : MipsDSPSideEffectBase<"DPSQ_SA_L_W", SDT_MipsDPA>;
  62
  63 def MipsDPA_W_PH : MipsDSPBase<"DPA_W_PH", SDT_MipsDPA>;
  64 def MipsDPS_W_PH : MipsDSPBase<"DPS_W_PH", SDT_MipsDPA>;
  65 def MipsDPAQX_S_W_PH : MipsDSPSideEffectBase<"DPAQX_S_W_PH", SDT_MipsDPA>;
  66 def MipsDPAQX_SA_W_PH : MipsDSPSideEffectBase<"DPAQX_SA_W_PH", SDT_MipsDPA>;
  67 def MipsDPAX_W_PH : MipsDSPBase<"DPAX_W_PH", SDT_MipsDPA>;
  68 def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>;
  69 def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>;
  70 def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>;
  71 def MipsMULSA_W_PH : MipsDSPBase<"MULSA_W_PH", SDT_MipsDPA>;
  72
  73 def MipsMULT : MipsDSPBase<"MULT", SDT_MipsDPA>;
  74 def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>;
  75 def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA>;
  76 def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA>;
  77 def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA>;
  78 def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>;
  79 def MipsSHLL_DSP : MipsDSPBase<"SHLL_DSP", SDT_MipsSHIFT_DSP>;
  80 def MipsSHRA_DSP : MipsDSPBase<"SHRA_DSP", SDT_MipsSHIFT_DSP>;
  81 def MipsSHRL_DSP : MipsDSPBase<"SHRL_DSP", SDT_MipsSHIFT_DSP>;
  82 def MipsSETCC_DSP : MipsDSPBase<"SETCC_DSP", SDTSetCC>;
  83 def MipsSELECT_CC_DSP : MipsDSPBase<"SELECT_CC_DSP", SDTSelectCC>;
  84
  85 // Flags.
  86 class Uses<list<Register> Regs> {
  87   list<Register> Uses = Regs;
  88 }
  89
  90 class Defs<list<Register> Regs> {
  91   list<Register> Defs = Regs;
  92 }
  93
  94 // Instruction encoding.
  95 class ADDU_QB_ENC : ADDU_QB_FMT<0b00000>;
  96 class ADDU_S_QB_ENC : ADDU_QB_FMT<0b00100>;
  97 class SUBU_QB_ENC : ADDU_QB_FMT<0b00001>;
  98 class SUBU_S_QB_ENC : ADDU_QB_FMT<0b00101>;
  99 class ADDQ_PH_ENC : ADDU_QB_FMT<0b01010>;
 100 class ADDQ_S_PH_ENC : ADDU_QB_FMT<0b01110>;
 101 class SUBQ_PH_ENC : ADDU_QB_FMT<0b01011>;
 102 class SUBQ_S_PH_ENC : ADDU_QB_FMT<0b01111>;
 103 class ADDQ_S_W_ENC : ADDU_QB_FMT<0b10110>;
 104 class SUBQ_S_W_ENC : ADDU_QB_FMT<0b10111>;
 105 class ADDSC_ENC : ADDU_QB_FMT<0b10000>;
 106 class ADDWC_ENC : ADDU_QB_FMT<0b10001>;
 107 class MODSUB_ENC : ADDU_QB_FMT<0b10010>;
 108 class RADDU_W_QB_ENC : RADDU_W_QB_FMT<0b10100>;
 109 class ABSQ_S_PH_ENC : ABSQ_S_PH_R2_FMT<0b01001>;
 110 class ABSQ_S_W_ENC : ABSQ_S_PH_R2_FMT<0b10001>;
 111 class PRECRQ_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01100>;
 112 class PRECRQ_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10100>;
 113 class PRECRQ_RS_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10101>;
 114 class PRECRQU_S_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01111>;
 115 class PRECEQ_W_PHL_ENC : ABSQ_S_PH_R2_FMT<0b01100>;
 116 class PRECEQ_W_PHR_ENC : ABSQ_S_PH_R2_FMT<0b01101>;
 117 class PRECEQU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b00100>;
 118 class PRECEQU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b00101>;
 119 class PRECEQU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b00110>;
 120 class PRECEQU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b00111>;
 121 class PRECEU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b11100>;
 122 class PRECEU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b11101>;
 123 class PRECEU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b11110>;
 124 class PRECEU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b11111>;
 125 class SHLL_QB_ENC : SHLL_QB_FMT<0b00000>;
 126 class SHLLV_QB_ENC : SHLL_QB_FMT<0b00010>;
 127 class SHRL_QB_ENC : SHLL_QB_FMT<0b00001>;
 128 class SHRLV_QB_ENC : SHLL_QB_FMT<0b00011>;
 129 class SHLL_PH_ENC : SHLL_QB_FMT<0b01000>;
 130 class SHLLV_PH_ENC : SHLL_QB_FMT<0b01010>;
 131 class SHLL_S_PH_ENC : SHLL_QB_FMT<0b01100>;
 132 class SHLLV_S_PH_ENC : SHLL_QB_FMT<0b01110>;
 133 class SHRA_PH_ENC : SHLL_QB_FMT<0b01001>;
 134 class SHRAV_PH_ENC : SHLL_QB_FMT<0b01011>;
 135 class SHRA_R_PH_ENC : SHLL_QB_FMT<0b01101>;
 136 class SHRAV_R_PH_ENC : SHLL_QB_FMT<0b01111>;
 137 class SHLL_S_W_ENC : SHLL_QB_FMT<0b10100>;
 138 class SHLLV_S_W_ENC : SHLL_QB_FMT<0b10110>;
 139 class SHRA_R_W_ENC : SHLL_QB_FMT<0b10101>;
 140 class SHRAV_R_W_ENC : SHLL_QB_FMT<0b10111>;
 141 class MULEU_S_PH_QBL_ENC : ADDU_QB_FMT<0b00110>;
 142 class MULEU_S_PH_QBR_ENC : ADDU_QB_FMT<0b00111>;
 143 class MULEQ_S_W_PHL_ENC : ADDU_QB_FMT<0b11100>;
 144 class MULEQ_S_W_PHR_ENC : ADDU_QB_FMT<0b11101>;
 145 class MULQ_RS_PH_ENC : ADDU_QB_FMT<0b11111>;
 146 class MULSAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00110>;
 147 class MAQ_S_W_PHL_ENC : DPA_W_PH_FMT<0b10100>;
 148 class MAQ_S_W_PHR_ENC : DPA_W_PH_FMT<0b10110>;
 149 class MAQ_SA_W_PHL_ENC : DPA_W_PH_FMT<0b10000>;
 150 class MAQ_SA_W_PHR_ENC : DPA_W_PH_FMT<0b10010>;
 151 class MFHI_ENC : MFHI_FMT<0b010000>;
 152 class MFLO_ENC : MFHI_FMT<0b010010>;
 153 class MTHI_ENC : MTHI_FMT<0b010001>;
 154 class MTLO_ENC : MTHI_FMT<0b010011>;
 155 class DPAU_H_QBL_ENC : DPA_W_PH_FMT<0b00011>;
 156 class DPAU_H_QBR_ENC : DPA_W_PH_FMT<0b00111>;
 157 class DPSU_H_QBL_ENC : DPA_W_PH_FMT<0b01011>;
 158 class DPSU_H_QBR_ENC : DPA_W_PH_FMT<0b01111>;
 159 class DPAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00100>;
 160 class DPSQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00101>;
 161 class DPAQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01100>;
 162 class DPSQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01101>;
 163 class MULT_DSP_ENC : MULT_FMT<0b000000, 0b011000>;
 164 class MULTU_DSP_ENC : MULT_FMT<0b000000, 0b011001>;
 165 class MADD_DSP_ENC : MULT_FMT<0b011100, 0b000000>;
 166 class MADDU_DSP_ENC : MULT_FMT<0b011100, 0b000001>;
 167 class MSUB_DSP_ENC : MULT_FMT<0b011100, 0b000100>;
 168 class MSUBU_DSP_ENC : MULT_FMT<0b011100, 0b000101>;
 169 class CMPU_EQ_QB_ENC : CMP_EQ_QB_R2_FMT<0b00000>;
 170 class CMPU_LT_QB_ENC : CMP_EQ_QB_R2_FMT<0b00001>;
 171 class CMPU_LE_QB_ENC : CMP_EQ_QB_R2_FMT<0b00010>;
 172 class CMPGU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b00100>;
 173 class CMPGU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b00101>;
 174 class CMPGU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b00110>;
 175 class CMP_EQ_PH_ENC : CMP_EQ_QB_R2_FMT<0b01000>;
 176 class CMP_LT_PH_ENC : CMP_EQ_QB_R2_FMT<0b01001>;
 177 class CMP_LE_PH_ENC : CMP_EQ_QB_R2_FMT<0b01010>;
 178 class BITREV_ENC : ABSQ_S_PH_R2_FMT<0b11011>;
 179 class PACKRL_PH_ENC : CMP_EQ_QB_R3_FMT<0b01110>;
 180 class REPL_QB_ENC : REPL_FMT<0b00010>;
 181 class REPL_PH_ENC : REPL_FMT<0b01010>;
 182 class REPLV_QB_ENC : ABSQ_S_PH_R2_FMT<0b00011>;
 183 class REPLV_PH_ENC : ABSQ_S_PH_R2_FMT<0b01011>;
 184 class PICK_QB_ENC : CMP_EQ_QB_R3_FMT<0b00011>;
 185 class PICK_PH_ENC : CMP_EQ_QB_R3_FMT<0b01011>;
 186 class LWX_ENC : LX_FMT<0b00000>;
 187 class LHX_ENC : LX_FMT<0b00100>;
 188 class LBUX_ENC : LX_FMT<0b00110>;
 189 class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>;
 190 class INSV_ENC : INSV_FMT<0b001100>;
 191
 192 class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>;
 193 class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>;
 194 class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>;
 195 class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>;
 196 class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>;
 197 class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>;
 198 class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>;
 199 class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>;
 200 class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>;
 201 class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>;
 202 class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>;
 203 class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>;
 204 class SHILO_ENC : SHILO_R1_FMT<0b11010>;
 205 class SHILOV_ENC : SHILO_R2_FMT<0b11011>;
 206 class MTHLIP_ENC : SHILO_R2_FMT<0b11111>;
 207
 208 class RDDSP_ENC : RDDSP_FMT<0b10010>;
 209 class WRDSP_ENC : WRDSP_FMT<0b10011>;
 210 class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>;
 211 class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>;
 212 class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>;
 213 class SUBU_S_PH_ENC : ADDU_QB_FMT<0b01101>;
 214 class CMPGDU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b11000>;
 215 class CMPGDU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b11001>;
 216 class CMPGDU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b11010>;
 217 class ABSQ_S_QB_ENC : ABSQ_S_PH_R2_FMT<0b00001>;
 218 class ADDUH_QB_ENC : ADDUH_QB_FMT<0b00000>;
 219 class ADDUH_R_QB_ENC : ADDUH_QB_FMT<0b00010>;
 220 class SUBUH_QB_ENC : ADDUH_QB_FMT<0b00001>;
 221 class SUBUH_R_QB_ENC : ADDUH_QB_FMT<0b00011>;
 222 class ADDQH_PH_ENC : ADDUH_QB_FMT<0b01000>;
 223 class ADDQH_R_PH_ENC : ADDUH_QB_FMT<0b01010>;
 224 class SUBQH_PH_ENC : ADDUH_QB_FMT<0b01001>;
 225 class SUBQH_R_PH_ENC : ADDUH_QB_FMT<0b01011>;
 226 class ADDQH_W_ENC : ADDUH_QB_FMT<0b10000>;
 227 class ADDQH_R_W_ENC : ADDUH_QB_FMT<0b10010>;
 228 class SUBQH_W_ENC : ADDUH_QB_FMT<0b10001>;
 229 class SUBQH_R_W_ENC : ADDUH_QB_FMT<0b10011>;
 230 class MUL_PH_ENC : ADDUH_QB_FMT<0b01100>;
 231 class MUL_S_PH_ENC : ADDUH_QB_FMT<0b01110>;
 232 class MULQ_S_W_ENC : ADDUH_QB_FMT<0b10110>;
 233 class MULQ_RS_W_ENC : ADDUH_QB_FMT<0b10111>;
 234 class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>;
 235 class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>;
 236 class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>;
 237 class DPAQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11000>;
 238 class DPAQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11010>;
 239 class DPAX_W_PH_ENC : DPA_W_PH_FMT<0b01000>;
 240 class DPSX_W_PH_ENC : DPA_W_PH_FMT<0b01001>;
 241 class DPSQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11001>;
 242 class DPSQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11011>;
 243 class MULSA_W_PH_ENC : DPA_W_PH_FMT<0b00010>;
 244 class PRECR_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01101>;
 245 class PRECR_SRA_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11110>;
 246 class PRECR_SRA_R_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11111>;
 247 class SHRA_QB_ENC : SHLL_QB_FMT<0b00100>;
 248 class SHRAV_QB_ENC : SHLL_QB_FMT<0b00110>;
 249 class SHRA_R_QB_ENC : SHLL_QB_FMT<0b00101>;
 250 class SHRAV_R_QB_ENC : SHLL_QB_FMT<0b00111>;
 251 class SHRL_PH_ENC : SHLL_QB_FMT<0b11001>;
 252 class SHRLV_PH_ENC : SHLL_QB_FMT<0b11011>;
 253 class APPEND_ENC : APPEND_FMT<0b00000>;
 254 class BALIGN_ENC : APPEND_FMT<0b10000>;
 255 class PREPEND_ENC : APPEND_FMT<0b00001>;
 256
 257 // Instruction desc.
 258 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 259                         InstrItinClass itin, RegisterOperand ROD,
 260                         RegisterOperand ROS,  RegisterOperand ROT = ROS> {
 261   dag OutOperandList = (outs ROD:$rd);
 262   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 263   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 264   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
 265   InstrItinClass Itinerary = itin;
 266   string BaseOpcode = instr_asm;
 267 }
 268
 269 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 270                            InstrItinClass itin, RegisterOperand ROD,
 271                            RegisterOperand ROS = ROD> {
 272   dag OutOperandList = (outs ROD:$rd);
 273   dag InOperandList = (ins ROS:$rs);
 274   string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
 275   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))];
 276   InstrItinClass Itinerary = itin;
 277 }
 278
 279 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 280                              InstrItinClass itin, RegisterOperand ROS,
 281                              RegisterOperand ROT = ROS> {
 282   dag OutOperandList = (outs);
 283   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 284   string AsmString = !strconcat(instr_asm, "\t$rs, $rt");
 285   list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)];
 286   InstrItinClass Itinerary = itin;
 287 }
 288
 289 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 290                              InstrItinClass itin, RegisterOperand ROD,
 291                              RegisterOperand ROS,  RegisterOperand ROT = ROS> {
 292   dag OutOperandList = (outs ROD:$rd);
 293   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 294   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 295   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
 296   InstrItinClass Itinerary = itin;
 297 }
 298
 299 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 300                                InstrItinClass itin, RegisterOperand ROT,
 301                                RegisterOperand ROS = ROT> {
 302   dag OutOperandList = (outs ROT:$rt);
 303   dag InOperandList = (ins ROS:$rs, uimm5:$sa, ROS:$src);
 304   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
 305   list<dag> Pattern = [(set ROT:$rt, (OpNode ROS:$src, ROS:$rs, immZExt5:$sa))];
 306   InstrItinClass Itinerary = itin;
 307   string Constraints = "$src = $rt";
 308 }
 309
 310 class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 311                              InstrItinClass itin, RegisterOperand ROD,
 312                              RegisterOperand ROT = ROD> {
 313   dag OutOperandList = (outs ROD:$rd);
 314   dag InOperandList = (ins ROT:$rt);
 315   string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
 316   list<dag> Pattern = [(set ROD:$rd, (OpNode ROT:$rt))];
 317   InstrItinClass Itinerary = itin;
 318   string BaseOpcode = instr_asm;
 319 }
 320
 321 class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 322                      ImmLeaf immPat, InstrItinClass itin, RegisterOperand RO> {
 323   dag OutOperandList = (outs RO:$rd);
 324   dag InOperandList = (ins uimm16:$imm);
 325   string AsmString = !strconcat(instr_asm, "\t$rd, $imm");
 326   list<dag> Pattern = [(set RO:$rd, (OpNode immPat:$imm))];
 327   InstrItinClass Itinerary = itin;
 328 }
 329
 330 class SHLL_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 331                            InstrItinClass itin, RegisterOperand RO> {
 332   dag OutOperandList = (outs RO:$rd);
 333   dag InOperandList =  (ins RO:$rt, GPR32Opnd:$rs_sa);
 334   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 335   list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs_sa))];
 336   InstrItinClass Itinerary = itin;
 337 }
 338
 339 class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 340                            SDPatternOperator ImmPat, InstrItinClass itin,
 341                            RegisterOperand RO> {
 342   dag OutOperandList = (outs RO:$rd);
 343   dag InOperandList = (ins RO:$rt, uimm16:$rs_sa);
 344   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 345   list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, ImmPat:$rs_sa))];
 346   InstrItinClass Itinerary = itin;
 347   bit hasSideEffects = 1;
 348 }
 349
 350 class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 351                    InstrItinClass itin> {
 352   dag OutOperandList = (outs GPR32Opnd:$rd);
 353   dag InOperandList = (ins PtrRC:$base, PtrRC:$index);
 354   string AsmString = !strconcat(instr_asm, "\t$rd, ${index}(${base})");
 355   list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode iPTR:$base, iPTR:$index))];
 356   InstrItinClass Itinerary = itin;
 357   bit mayLoad = 1;
 358 }
 359
 360 class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 361                          InstrItinClass itin, RegisterOperand ROD,
 362                          RegisterOperand ROS = ROD,  RegisterOperand ROT = ROD> {
 363   dag OutOperandList = (outs ROD:$rd);
 364   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 365   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 366   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
 367   InstrItinClass Itinerary = itin;
 368   string BaseOpcode = instr_asm;
 369 }
 370
 371 class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 372                        SDPatternOperator ImmOp, InstrItinClass itin> {
 373   dag OutOperandList = (outs GPR32Opnd:$rt);
 374   dag InOperandList = (ins GPR32Opnd:$rs, uimm5:$sa, GPR32Opnd:$src);
 375   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
 376   list<dag> Pattern =  [(set GPR32Opnd:$rt,
 377                         (OpNode GPR32Opnd:$src, GPR32Opnd:$rs, ImmOp:$sa))];
 378   InstrItinClass Itinerary = itin;
 379   string Constraints = "$src = $rt";
 380 }
 381
 382 class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 383                               InstrItinClass itin> {
 384   dag OutOperandList = (outs GPR32Opnd:$rt);
 385   dag InOperandList = (ins ACC64DSPOpnd:$ac, GPR32Opnd:$shift_rs);
 386   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 387   InstrItinClass Itinerary = itin;
 388 }
 389
 390 class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 391                               InstrItinClass itin> {
 392   dag OutOperandList = (outs GPR32Opnd:$rt);
 393   dag InOperandList = (ins ACC64DSPOpnd:$ac, uimm16:$shift_rs);
 394   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 395   InstrItinClass Itinerary = itin;
 396 }
 397
 398 class SHILO_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 399   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 400   dag InOperandList = (ins simm16:$shift, ACC64DSPOpnd:$acin);
 401   string AsmString = !strconcat(instr_asm, "\t$ac, $shift");
 402   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 403                         (OpNode immSExt6:$shift, ACC64DSPOpnd:$acin))];
 404   string Constraints = "$acin = $ac";
 405 }
 406
 407 class SHILO_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 408   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 409   dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin);
 410   string AsmString = !strconcat(instr_asm, "\t$ac, $rs");
 411   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 412                         (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))];
 413   string Constraints = "$acin = $ac";
 414 }
 415
 416 class MTHLIP_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 417   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 418   dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin);
 419   string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
 420   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 421                         (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))];
 422   string Constraints = "$acin = $ac";
 423 }
 424
 425 class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 426                       InstrItinClass itin> {
 427   dag OutOperandList = (outs GPR32Opnd:$rd);
 428   dag InOperandList = (ins uimm16:$mask);
 429   string AsmString = !strconcat(instr_asm, "\t$rd, $mask");
 430   list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode immZExt10:$mask))];
 431   InstrItinClass Itinerary = itin;
 432 }
 433
 434 class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 435                       InstrItinClass itin> {
 436   dag OutOperandList = (outs);
 437   dag InOperandList = (ins GPR32Opnd:$rs, uimm16:$mask);
 438   string AsmString = !strconcat(instr_asm, "\t$rs, $mask");
 439   list<dag> Pattern = [(OpNode GPR32Opnd:$rs, immZExt10:$mask)];
 440   InstrItinClass Itinerary = itin;
 441 }
 442
 443 class DPA_W_PH_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 444   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 445   dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin);
 446   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 447   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 448                         (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))];
 449   string Constraints = "$acin = $ac";
 450   string BaseOpcode = instr_asm;
 451 }
 452
 453 class MULT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 454                      InstrItinClass itin> {
 455   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 456   dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt);
 457   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 458   list<dag> Pattern = [(set ACC64DSPOpnd:$ac, (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt))];
 459   InstrItinClass Itinerary = itin;
 460   bit isCommutable = 1;
 461   string BaseOpcode = instr_asm;
 462 }
 463
 464 class MADD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 465                      InstrItinClass itin> {
 466   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 467   dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin);
 468   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 469   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 470                         (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))];
 471   InstrItinClass Itinerary = itin;
 472   string Constraints = "$acin = $ac";
 473   string BaseOpcode = instr_asm;
 474 }
 475
 476 class MFHI_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,
 477                      InstrItinClass itin> {
 478   dag OutOperandList = (outs GPR32Opnd:$rd);
 479   dag InOperandList = (ins RO:$ac);
 480   string AsmString = !strconcat(instr_asm, "\t$rd, $ac");
 481   list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode RO:$ac))];
 482   InstrItinClass Itinerary = itin;
 483 }
 484
 485 class MTHI_DESC_BASE<string instr_asm, RegisterOperand RO, InstrItinClass itin> {
 486   dag OutOperandList = (outs RO:$ac);
 487   dag InOperandList = (ins GPR32Opnd:$rs);
 488   string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
 489   InstrItinClass Itinerary = itin;
 490 }
 491
 492 class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> :
 493   MipsPseudo<(outs GPR32Opnd:$dst), (ins), [(set GPR32Opnd:$dst, (OpNode))]> {
 494   bit usesCustomInserter = 1;
 495 }
 496
 497 class BPOSGE32_DESC_BASE<string instr_asm, InstrItinClass itin> {
 498   dag OutOperandList = (outs);
 499   dag InOperandList = (ins brtarget:$offset);
 500   string AsmString = !strconcat(instr_asm, "\t$offset");
 501   InstrItinClass Itinerary = itin;
 502   bit isBranch = 1;
 503   bit isTerminator = 1;
 504   bit hasDelaySlot = 1;
 505 }
 506
 507 class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 508                      InstrItinClass itin> {
 509   dag OutOperandList = (outs GPR32Opnd:$rt);
 510   dag InOperandList = (ins GPR32Opnd:$src, GPR32Opnd:$rs);
 511   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 512   list<dag> Pattern = [(set GPR32Opnd:$rt, (OpNode GPR32Opnd:$src, GPR32Opnd:$rs))];
 513   InstrItinClass Itinerary = itin;
 514   string Constraints = "$src = $rt";
 515   string BaseOpcode = instr_asm;
 516 }
 517
 518 //===----------------------------------------------------------------------===//
 519 // MIPS DSP Rev 1
 520 //===----------------------------------------------------------------------===//
 521
 522 // Addition/subtraction
 523 class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", null_frag, NoItinerary,
 524                                        DSPROpnd, DSPROpnd>, IsCommutable,
 525                      Defs<[DSPOutFlag20]>;
 526
 527 class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb,
 528                                          NoItinerary, DSPROpnd, DSPROpnd>,
 529                        IsCommutable, Defs<[DSPOutFlag20]>;
 530
 531 class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", null_frag, NoItinerary,
 532                                        DSPROpnd, DSPROpnd>,
 533                      Defs<[DSPOutFlag20]>;
 534
 535 class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb,
 536                                          NoItinerary, DSPROpnd, DSPROpnd>,
 537                        Defs<[DSPOutFlag20]>;
 538
 539 class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", null_frag, NoItinerary,
 540                                        DSPROpnd, DSPROpnd>, IsCommutable,
 541                      Defs<[DSPOutFlag20]>;
 542
 543 class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph,
 544                                          NoItinerary, DSPROpnd, DSPROpnd>,
 545                        IsCommutable, Defs<[DSPOutFlag20]>;
 546
 547 class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", null_frag, NoItinerary,
 548                                        DSPROpnd, DSPROpnd>,
 549                      Defs<[DSPOutFlag20]>;
 550
 551 class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph,
 552                                          NoItinerary, DSPROpnd, DSPROpnd>,
 553                        Defs<[DSPOutFlag20]>;
 554
 555 class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w,
 556                                         NoItinerary, GPR32Opnd, GPR32Opnd>,
 557                       IsCommutable, Defs<[DSPOutFlag20]>;
 558
 559 class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w,
 560                                         NoItinerary, GPR32Opnd, GPR32Opnd>,
 561                       Defs<[DSPOutFlag20]>;
 562
 563 class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", null_frag, NoItinerary,
 564                                      GPR32Opnd, GPR32Opnd>, IsCommutable,
 565                    Defs<[DSPCarry]>;
 566
 567 class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", null_frag, NoItinerary,
 568                                      GPR32Opnd, GPR32Opnd>,
 569                    IsCommutable, Uses<[DSPCarry]>, Defs<[DSPOutFlag20]>;
 570
 571 class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub, NoItinerary,
 572                                       GPR32Opnd, GPR32Opnd>;
 573
 574 class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb,
 575                                              NoItinerary, GPR32Opnd, DSPROpnd>;
 576
 577 // Absolute value
 578 class ABSQ_S_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.ph", int_mips_absq_s_ph,
 579                                               NoItinerary, DSPROpnd>,
 580                        Defs<[DSPOutFlag20]>;
 581
 582 class ABSQ_S_W_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.w", int_mips_absq_s_w,
 583                                              NoItinerary, GPR32Opnd>,
 584                       Defs<[DSPOutFlag20]>;
 585
 586 // Precision reduce/expand
 587 class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph",
 588                                                  int_mips_precrq_qb_ph,
 589                                                  NoItinerary, DSPROpnd, DSPROpnd>;
 590
 591 class PRECRQ_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.ph.w",
 592                                                 int_mips_precrq_ph_w,
 593                                                 NoItinerary, DSPROpnd, GPR32Opnd>;
 594
 595 class PRECRQ_RS_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq_rs.ph.w",
 596                                                    int_mips_precrq_rs_ph_w,
 597                                                    NoItinerary, DSPROpnd,
 598                                                    GPR32Opnd>,
 599                             Defs<[DSPOutFlag22]>;
 600
 601 class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph",
 602                                                     int_mips_precrqu_s_qb_ph,
 603                                                     NoItinerary, DSPROpnd,
 604                                                     DSPROpnd>,
 605                              Defs<[DSPOutFlag22]>;
 606
 607 class PRECEQ_W_PHL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phl",
 608                                                  int_mips_preceq_w_phl,
 609                                                  NoItinerary, GPR32Opnd, DSPROpnd>;
 610
 611 class PRECEQ_W_PHR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phr",
 612                                                  int_mips_preceq_w_phr,
 613                                                  NoItinerary, GPR32Opnd, DSPROpnd>;
 614
 615 class PRECEQU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbl",
 616                                                    int_mips_precequ_ph_qbl,
 617                                                    NoItinerary, DSPROpnd>;
 618
 619 class PRECEQU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbr",
 620                                                    int_mips_precequ_ph_qbr,
 621                                                    NoItinerary, DSPROpnd>;
 622
 623 class PRECEQU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbla",
 624                                                     int_mips_precequ_ph_qbla,
 625                                                     NoItinerary, DSPROpnd>;
 626
 627 class PRECEQU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbra",
 628                                                     int_mips_precequ_ph_qbra,
 629                                                     NoItinerary, DSPROpnd>;
 630
 631 class PRECEU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbl",
 632                                                   int_mips_preceu_ph_qbl,
 633                                                   NoItinerary, DSPROpnd>;
 634
 635 class PRECEU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbr",
 636                                                   int_mips_preceu_ph_qbr,
 637                                                   NoItinerary, DSPROpnd>;
 638
 639 class PRECEU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbla",
 640                                                    int_mips_preceu_ph_qbla,
 641                                                    NoItinerary, DSPROpnd>;
 642
 643 class PRECEU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbra",
 644                                                    int_mips_preceu_ph_qbra,
 645                                                    NoItinerary, DSPROpnd>;
 646
 647 // Shift
 648 class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", null_frag, immZExt3,
 649                                           NoItinerary, DSPROpnd>,
 650                      Defs<[DSPOutFlag22]>;
 651
 652 class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb,
 653                                            NoItinerary, DSPROpnd>,
 654                       Defs<[DSPOutFlag22]>;
 655
 656 class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", null_frag, immZExt3,
 657                                           NoItinerary, DSPROpnd>;
 658
 659 class SHRLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.qb", int_mips_shrl_qb,
 660                                            NoItinerary, DSPROpnd>;
 661
 662 class SHLL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll.ph", null_frag, immZExt4,
 663                                           NoItinerary, DSPROpnd>,
 664                      Defs<[DSPOutFlag22]>;
 665
 666 class SHLLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv.ph", int_mips_shll_ph,
 667                                            NoItinerary, DSPROpnd>,
 668                       Defs<[DSPOutFlag22]>;
 669
 670 class SHLL_S_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.ph", int_mips_shll_s_ph,
 671                                             immZExt4, NoItinerary, DSPROpnd>,
 672                        Defs<[DSPOutFlag22]>;
 673
 674 class SHLLV_S_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.ph", int_mips_shll_s_ph,
 675                                              NoItinerary, DSPROpnd>,
 676                         Defs<[DSPOutFlag22]>;
 677
 678 class SHRA_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra.ph", null_frag, immZExt4,
 679                                           NoItinerary, DSPROpnd>;
 680
 681 class SHRAV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav.ph", int_mips_shra_ph,
 682                                            NoItinerary, DSPROpnd>;
 683
 684 class SHRA_R_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.ph", int_mips_shra_r_ph,
 685                                             immZExt4, NoItinerary, DSPROpnd>;
 686
 687 class SHRAV_R_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.ph", int_mips_shra_r_ph,
 688                                              NoItinerary, DSPROpnd>;
 689
 690 class SHLL_S_W_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.w", int_mips_shll_s_w,
 691                                            immZExt5, NoItinerary, GPR32Opnd>,
 692                       Defs<[DSPOutFlag22]>;
 693
 694 class SHLLV_S_W_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.w", int_mips_shll_s_w,
 695                                             NoItinerary, GPR32Opnd>,
 696                        Defs<[DSPOutFlag22]>;
 697
 698 class SHRA_R_W_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.w", int_mips_shra_r_w,
 699                                            immZExt5, NoItinerary, GPR32Opnd>;
 700
 701 class SHRAV_R_W_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.w", int_mips_shra_r_w,
 702                                             NoItinerary, GPR32Opnd>;
 703
 704 // Multiplication
 705 class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl",
 706                                               int_mips_muleu_s_ph_qbl,
 707                                               NoItinerary, DSPROpnd, DSPROpnd>,
 708                             Defs<[DSPOutFlag21]>;
 709
 710 class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr",
 711                                               int_mips_muleu_s_ph_qbr,
 712                                               NoItinerary, DSPROpnd, DSPROpnd>,
 713                             Defs<[DSPOutFlag21]>;
 714
 715 class MULEQ_S_W_PHL_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phl",
 716                                              int_mips_muleq_s_w_phl,
 717                                              NoItinerary, GPR32Opnd, DSPROpnd>,
 718                            IsCommutable, Defs<[DSPOutFlag21]>;
 719
 720 class MULEQ_S_W_PHR_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phr",
 721                                              int_mips_muleq_s_w_phr,
 722                                              NoItinerary, GPR32Opnd, DSPROpnd>,
 723                            IsCommutable, Defs<[DSPOutFlag21]>;
 724
 725 class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph,
 726                                           NoItinerary, DSPROpnd, DSPROpnd>,
 727                         IsCommutable, Defs<[DSPOutFlag21]>;
 728
 729 class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph",
 730                                               MipsMULSAQ_S_W_PH>,
 731                            Defs<[DSPOutFlag16_19]>;
 732
 733 class MAQ_S_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phl", MipsMAQ_S_W_PHL>,
 734                          Defs<[DSPOutFlag16_19]>;
 735
 736 class MAQ_S_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phr", MipsMAQ_S_W_PHR>,
 737                          Defs<[DSPOutFlag16_19]>;
 738
 739 class MAQ_SA_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phl", MipsMAQ_SA_W_PHL>,
 740                           Defs<[DSPOutFlag16_19]>;
 741
 742 class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr", MipsMAQ_SA_W_PHR>,
 743                           Defs<[DSPOutFlag16_19]>;
 744
 745 // Move from/to hi/lo.
 746 class MFHI_DESC : MFHI_DESC_BASE<"mfhi", ACC64DSPOpnd, MipsMFHI, NoItinerary>;
 747 class MFLO_DESC : MFHI_DESC_BASE<"mflo", ACC64DSPOpnd, MipsMFLO, NoItinerary>;
 748 class MTHI_DESC : MTHI_DESC_BASE<"mthi", HI32DSPOpnd, NoItinerary>;
 749 class MTLO_DESC : MTHI_DESC_BASE<"mtlo", LO32DSPOpnd, NoItinerary>;
 750
 751 // Dot product with accumulate/subtract
 752 class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl", MipsDPAU_H_QBL>;
 753
 754 class DPAU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbr", MipsDPAU_H_QBR>;
 755
 756 class DPSU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbl", MipsDPSU_H_QBL>;
 757
 758 class DPSU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbr", MipsDPSU_H_QBR>;
 759
 760 class DPAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaq_s.w.ph", MipsDPAQ_S_W_PH>,
 761                          Defs<[DSPOutFlag16_19]>;
 762
 763 class DPSQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsq_s.w.ph", MipsDPSQ_S_W_PH>,
 764                          Defs<[DSPOutFlag16_19]>;
 765
 766 class DPAQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpaq_sa.l.w", MipsDPAQ_SA_L_W>,
 767                          Defs<[DSPOutFlag16_19]>;
 768
 769 class DPSQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpsq_sa.l.w", MipsDPSQ_SA_L_W>,
 770                          Defs<[DSPOutFlag16_19]>;
 771
 772 class MULT_DSP_DESC  : MULT_DESC_BASE<"mult", MipsMult, NoItinerary>;
 773 class MULTU_DSP_DESC : MULT_DESC_BASE<"multu", MipsMultu, NoItinerary>;
 774 class MADD_DSP_DESC  : MADD_DESC_BASE<"madd", MipsMAdd, NoItinerary>;
 775 class MADDU_DSP_DESC : MADD_DESC_BASE<"maddu", MipsMAddu, NoItinerary>;
 776 class MSUB_DSP_DESC  : MADD_DESC_BASE<"msub", MipsMSub, NoItinerary>;
 777 class MSUBU_DSP_DESC : MADD_DESC_BASE<"msubu", MipsMSubu, NoItinerary>;
 778
 779 // Comparison
 780 class CMPU_EQ_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.eq.qb",
 781                                                int_mips_cmpu_eq_qb, NoItinerary,
 782                                                DSPROpnd>,
 783                         IsCommutable, Defs<[DSPCCond]>;
 784
 785 class CMPU_LT_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.lt.qb",
 786                                                int_mips_cmpu_lt_qb, NoItinerary,
 787                                                DSPROpnd>, Defs<[DSPCCond]>;
 788
 789 class CMPU_LE_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.le.qb",
 790                                                int_mips_cmpu_le_qb, NoItinerary,
 791                                                DSPROpnd>, Defs<[DSPCCond]>;
 792
 793 class CMPGU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.eq.qb",
 794                                                 int_mips_cmpgu_eq_qb,
 795                                                 NoItinerary, GPR32Opnd, DSPROpnd>,
 796                          IsCommutable;
 797
 798 class CMPGU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.lt.qb",
 799                                                 int_mips_cmpgu_lt_qb,
 800                                                 NoItinerary, GPR32Opnd, DSPROpnd>;
 801
 802 class CMPGU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.le.qb",
 803                                                 int_mips_cmpgu_le_qb,
 804                                                 NoItinerary, GPR32Opnd, DSPROpnd>;
 805
 806 class CMP_EQ_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.eq.ph", int_mips_cmp_eq_ph,
 807                                               NoItinerary, DSPROpnd>,
 808                        IsCommutable, Defs<[DSPCCond]>;
 809
 810 class CMP_LT_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.lt.ph", int_mips_cmp_lt_ph,
 811                                               NoItinerary, DSPROpnd>,
 812                        Defs<[DSPCCond]>;
 813
 814 class CMP_LE_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.le.ph", int_mips_cmp_le_ph,
 815                                               NoItinerary, DSPROpnd>,
 816                        Defs<[DSPCCond]>;
 817
 818 // Misc
 819 class BITREV_DESC : ABSQ_S_PH_R2_DESC_BASE<"bitrev", int_mips_bitrev,
 820                                            NoItinerary, GPR32Opnd>;
 821
 822 class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph,
 823                                               NoItinerary, DSPROpnd, DSPROpnd>;
 824
 825 class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, immZExt8,
 826                                     NoItinerary, DSPROpnd>;
 827
 828 class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, immZExt10,
 829                                     NoItinerary, DSPROpnd>;
 830
 831 class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb,
 832                                              NoItinerary, DSPROpnd, GPR32Opnd>;
 833
 834 class REPLV_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.ph", int_mips_repl_ph,
 835                                              NoItinerary, DSPROpnd, GPR32Opnd>;
 836
 837 class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb,
 838                                             NoItinerary, DSPROpnd, DSPROpnd>,
 839                      Uses<[DSPCCond]>;
 840
 841 class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph,
 842                                             NoItinerary, DSPROpnd, DSPROpnd>,
 843                      Uses<[DSPCCond]>;
 844
 845 class LWX_DESC : LX_DESC_BASE<"lwx", int_mips_lwx, NoItinerary>;
 846
 847 class LHX_DESC : LX_DESC_BASE<"lhx", int_mips_lhx, NoItinerary>;
 848
 849 class LBUX_DESC : LX_DESC_BASE<"lbux", int_mips_lbux, NoItinerary>;
 850
 851 class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", NoItinerary>;
 852
 853 // Extr
 854 class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>,
 855                   Uses<[DSPPos]>, Defs<[DSPEFI]>;
 856
 857 class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>,
 858                    Uses<[DSPPos]>, Defs<[DSPEFI]>;
 859
 860 class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>,
 861                     Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
 862
 863 class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", MipsEXTPDP,
 864                                              NoItinerary>,
 865                      Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
 866
 867 class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>,
 868                     Defs<[DSPOutFlag23]>;
 869
 870 class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", MipsEXTR_W,
 871                                              NoItinerary>, Defs<[DSPOutFlag23]>;
 872
 873 class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", MipsEXTR_R_W,
 874                                               NoItinerary>,
 875                       Defs<[DSPOutFlag23]>;
 876
 877 class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", MipsEXTR_R_W,
 878                                                NoItinerary>,
 879                        Defs<[DSPOutFlag23]>;
 880
 881 class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W,
 882                                                NoItinerary>,
 883                        Defs<[DSPOutFlag23]>;
 884
 885 class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W,
 886                                                 NoItinerary>,
 887                         Defs<[DSPOutFlag23]>;
 888
 889 class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", MipsEXTR_S_H,
 890                                               NoItinerary>,
 891                       Defs<[DSPOutFlag23]>;
 892
 893 class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", MipsEXTR_S_H,
 894                                                NoItinerary>,
 895                        Defs<[DSPOutFlag23]>;
 896
 897 class SHILO_DESC : SHILO_R1_DESC_BASE<"shilo", MipsSHILO>;
 898
 899 class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov", MipsSHILO>;
 900
 901 class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip", MipsMTHLIP>, Defs<[DSPPos]>;
 902
 903 class RDDSP_DESC : RDDSP_DESC_BASE<"rddsp", int_mips_rddsp, NoItinerary>;
 904
 905 class WRDSP_DESC : WRDSP_DESC_BASE<"wrdsp", int_mips_wrdsp, NoItinerary>;
 906
 907 class INSV_DESC : INSV_DESC_BASE<"insv", int_mips_insv, NoItinerary>,
 908                   Uses<[DSPPos, DSPSCount]>;
 909
 910 //===----------------------------------------------------------------------===//
 911 // MIPS DSP Rev 2
 912 // Addition/subtraction
 913 class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph, NoItinerary,
 914                                        DSPROpnd, DSPROpnd>, IsCommutable,
 915                      Defs<[DSPOutFlag20]>;
 916
 917 class ADDU_S_PH_DESC : ADDU_QB_DESC_BASE<"addu_s.ph", int_mips_addu_s_ph,
 918                                          NoItinerary, DSPROpnd, DSPROpnd>,
 919                        IsCommutable, Defs<[DSPOutFlag20]>;
 920
 921 class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary,
 922                                        DSPROpnd, DSPROpnd>,
 923                      Defs<[DSPOutFlag20]>;
 924
 925 class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph,
 926                                          NoItinerary, DSPROpnd, DSPROpnd>,
 927                        Defs<[DSPOutFlag20]>;
 928
 929 class ADDUH_QB_DESC : ADDUH_QB_DESC_BASE<"adduh.qb", int_mips_adduh_qb,
 930                                          NoItinerary, DSPROpnd>, IsCommutable;
 931
 932 class ADDUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"adduh_r.qb", int_mips_adduh_r_qb,
 933                                            NoItinerary, DSPROpnd>, IsCommutable;
 934
 935 class SUBUH_QB_DESC : ADDUH_QB_DESC_BASE<"subuh.qb", int_mips_subuh_qb,
 936                                          NoItinerary, DSPROpnd>;
 937
 938 class SUBUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"subuh_r.qb", int_mips_subuh_r_qb,
 939                                            NoItinerary, DSPROpnd>;
 940
 941 class ADDQH_PH_DESC : ADDUH_QB_DESC_BASE<"addqh.ph", int_mips_addqh_ph,
 942                                          NoItinerary, DSPROpnd>, IsCommutable;
 943
 944 class ADDQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"addqh_r.ph", int_mips_addqh_r_ph,
 945                                            NoItinerary, DSPROpnd>, IsCommutable;
 946
 947 class SUBQH_PH_DESC : ADDUH_QB_DESC_BASE<"subqh.ph", int_mips_subqh_ph,
 948                                          NoItinerary, DSPROpnd>;
 949
 950 class SUBQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"subqh_r.ph", int_mips_subqh_r_ph,
 951                                            NoItinerary, DSPROpnd>;
 952
 953 class ADDQH_W_DESC : ADDUH_QB_DESC_BASE<"addqh.w", int_mips_addqh_w,
 954                                         NoItinerary, GPR32Opnd>, IsCommutable;
 955
 956 class ADDQH_R_W_DESC : ADDUH_QB_DESC_BASE<"addqh_r.w", int_mips_addqh_r_w,
 957                                           NoItinerary, GPR32Opnd>, IsCommutable;
 958
 959 class SUBQH_W_DESC : ADDUH_QB_DESC_BASE<"subqh.w", int_mips_subqh_w,
 960                                         NoItinerary, GPR32Opnd>;
 961
 962 class SUBQH_R_W_DESC : ADDUH_QB_DESC_BASE<"subqh_r.w", int_mips_subqh_r_w,
 963                                           NoItinerary, GPR32Opnd>;
 964
 965 // Comparison
 966 class CMPGDU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.eq.qb",
 967                                                  int_mips_cmpgdu_eq_qb,
 968                                                  NoItinerary, GPR32Opnd, DSPROpnd>,
 969                           IsCommutable, Defs<[DSPCCond]>;
 970
 971 class CMPGDU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.lt.qb",
 972                                                  int_mips_cmpgdu_lt_qb,
 973                                                  NoItinerary, GPR32Opnd, DSPROpnd>,
 974                           Defs<[DSPCCond]>;
 975
 976 class CMPGDU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.le.qb",
 977                                                  int_mips_cmpgdu_le_qb,
 978                                                  NoItinerary, GPR32Opnd, DSPROpnd>,
 979                           Defs<[DSPCCond]>;
 980
 981 // Absolute
 982 class ABSQ_S_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.qb", int_mips_absq_s_qb,
 983                                               NoItinerary, DSPROpnd>,
 984                        Defs<[DSPOutFlag20]>;
 985
 986 // Multiplication
 987 class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", null_frag, NoItinerary,
 988                                        DSPROpnd>, IsCommutable,
 989                     Defs<[DSPOutFlag21]>;
 990
 991 class MUL_S_PH_DESC : ADDUH_QB_DESC_BASE<"mul_s.ph", int_mips_mul_s_ph,
 992                                          NoItinerary, DSPROpnd>, IsCommutable,
 993                       Defs<[DSPOutFlag21]>;
 994
 995 class MULQ_S_W_DESC : ADDUH_QB_DESC_BASE<"mulq_s.w", int_mips_mulq_s_w,
 996                                          NoItinerary, GPR32Opnd>, IsCommutable,
 997                       Defs<[DSPOutFlag21]>;
 998
 999 class MULQ_RS_W_DESC : ADDUH_QB_DESC_BASE<"mulq_rs.w", int_mips_mulq_rs_w,
1000                                           NoItinerary, GPR32Opnd>, IsCommutable,
1001                        Defs<[DSPOutFlag21]>;
1002
1003 class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph,
1004                                          NoItinerary, DSPROpnd, DSPROpnd>,
1005                        IsCommutable, Defs<[DSPOutFlag21]>;
1006
1007 // Dot product with accumulate/subtract
1008 class DPA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpa.w.ph", MipsDPA_W_PH>;
1009
1010 class DPS_W_PH_DESC : DPA_W_PH_DESC_BASE<"dps.w.ph", MipsDPS_W_PH>;
1011
1012 class DPAQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_s.w.ph", MipsDPAQX_S_W_PH>,
1013                           Defs<[DSPOutFlag16_19]>;
1014
1015 class DPAQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_sa.w.ph",
1016                                               MipsDPAQX_SA_W_PH>,
1017                            Defs<[DSPOutFlag16_19]>;
1018
1019 class DPAX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpax.w.ph", MipsDPAX_W_PH>;
1020
1021 class DPSX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsx.w.ph", MipsDPSX_W_PH>;
1022
1023 class DPSQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_s.w.ph", MipsDPSQX_S_W_PH>,
1024                           Defs<[DSPOutFlag16_19]>;
1025
1026 class DPSQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_sa.w.ph",
1027                                               MipsDPSQX_SA_W_PH>,
1028                            Defs<[DSPOutFlag16_19]>;
1029
1030 class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph", MipsMULSA_W_PH>;
1031
1032 // Precision reduce/expand
1033 class PRECR_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precr.qb.ph",
1034                                                 int_mips_precr_qb_ph,
1035                                                 NoItinerary, DSPROpnd, DSPROpnd>;
1036
1037 class PRECR_SRA_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra.ph.w",
1038                                                      int_mips_precr_sra_ph_w,
1039                                                      NoItinerary, DSPROpnd,
1040                                                      GPR32Opnd>;
1041
1042 class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w",
1043                                                       int_mips_precr_sra_r_ph_w,
1044                                                        NoItinerary, DSPROpnd,
1045                                                        GPR32Opnd>;
1046
1047 // Shift
1048 class SHRA_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra.qb", null_frag, immZExt3,
1049                                           NoItinerary, DSPROpnd>;
1050
1051 class SHRAV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav.qb", int_mips_shra_qb,
1052                                            NoItinerary, DSPROpnd>;
1053
1054 class SHRA_R_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.qb", int_mips_shra_r_qb,
1055                                             immZExt3, NoItinerary, DSPROpnd>;
1056
1057 class SHRAV_R_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.qb", int_mips_shra_r_qb,
1058                                              NoItinerary, DSPROpnd>;
1059
1060 class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", null_frag, immZExt4,
1061                                           NoItinerary, DSPROpnd>;
1062
1063 class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph,
1064                                            NoItinerary, DSPROpnd>;
1065
1066 // Misc
1067 class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, immZExt5,
1068                                      NoItinerary>;
1069
1070 class BALIGN_DESC : APPEND_DESC_BASE<"balign", int_mips_balign, immZExt2,
1071                                      NoItinerary>;
1072
1073 class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, immZExt5,
1074                                       NoItinerary>;
1075
1076 // Pseudos.
1077 def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32,
1078                                                 NoItinerary>, Uses<[DSPPos]>;
1079
1080 // Instruction defs.
1081 // MIPS DSP Rev 1
1082 def ADDU_QB : DspMMRel, ADDU_QB_ENC, ADDU_QB_DESC;
1083 def ADDU_S_QB : DspMMRel, ADDU_S_QB_ENC, ADDU_S_QB_DESC;
1084 def SUBU_QB : SUBU_QB_ENC, SUBU_QB_DESC;
1085 def SUBU_S_QB : SUBU_S_QB_ENC, SUBU_S_QB_DESC;
1086 def ADDQ_PH : DspMMRel, ADDQ_PH_ENC, ADDQ_PH_DESC;
1087 def ADDQ_S_PH : DspMMRel, ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
1088 def SUBQ_PH : SUBQ_PH_ENC, SUBQ_PH_DESC;
1089 def SUBQ_S_PH : SUBQ_S_PH_ENC, SUBQ_S_PH_DESC;
1090 def ADDQ_S_W : DspMMRel, ADDQ_S_W_ENC, ADDQ_S_W_DESC;
1091 def SUBQ_S_W : SUBQ_S_W_ENC, SUBQ_S_W_DESC;
1092 def ADDSC : DspMMRel, ADDSC_ENC, ADDSC_DESC;
1093 def ADDWC : DspMMRel, ADDWC_ENC, ADDWC_DESC;
1094 def MODSUB : MODSUB_ENC, MODSUB_DESC;
1095 def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC;
1096 def ABSQ_S_PH : DspMMRel, ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
1097 def ABSQ_S_W : DspMMRel, ABSQ_S_W_ENC, ABSQ_S_W_DESC;
1098 def PRECRQ_QB_PH : PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
1099 def PRECRQ_PH_W : PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;
1100 def PRECRQ_RS_PH_W : PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC;
1101 def PRECRQU_S_QB_PH : PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC;
1102 def PRECEQ_W_PHL : PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC;
1103 def PRECEQ_W_PHR : PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC;
1104 def PRECEQU_PH_QBL : PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC;
1105 def PRECEQU_PH_QBR : PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC;
1106 def PRECEQU_PH_QBLA : PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC;
1107 def PRECEQU_PH_QBRA : PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC;
1108 def PRECEU_PH_QBL : PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC;
1109 def PRECEU_PH_QBR : PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC;
1110 def PRECEU_PH_QBLA : PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC;
1111 def PRECEU_PH_QBRA : PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC;
1112 def SHLL_QB : SHLL_QB_ENC, SHLL_QB_DESC;
1113 def SHLLV_QB : SHLLV_QB_ENC, SHLLV_QB_DESC;
1114 def SHRL_QB : SHRL_QB_ENC, SHRL_QB_DESC;
1115 def SHRLV_QB : SHRLV_QB_ENC, SHRLV_QB_DESC;
1116 def SHLL_PH : SHLL_PH_ENC, SHLL_PH_DESC;
1117 def SHLLV_PH : SHLLV_PH_ENC, SHLLV_PH_DESC;
1118 def SHLL_S_PH : SHLL_S_PH_ENC, SHLL_S_PH_DESC;
1119 def SHLLV_S_PH : SHLLV_S_PH_ENC, SHLLV_S_PH_DESC;
1120 def SHRA_PH : SHRA_PH_ENC, SHRA_PH_DESC;
1121 def SHRAV_PH : SHRAV_PH_ENC, SHRAV_PH_DESC;
1122 def SHRA_R_PH : SHRA_R_PH_ENC, SHRA_R_PH_DESC;
1123 def SHRAV_R_PH : SHRAV_R_PH_ENC, SHRAV_R_PH_DESC;
1124 def SHLL_S_W : SHLL_S_W_ENC, SHLL_S_W_DESC;
1125 def SHLLV_S_W : SHLLV_S_W_ENC, SHLLV_S_W_DESC;
1126 def SHRA_R_W : SHRA_R_W_ENC, SHRA_R_W_DESC;
1127 def SHRAV_R_W : SHRAV_R_W_ENC, SHRAV_R_W_DESC;
1128 def MULEU_S_PH_QBL : MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC;
1129 def MULEU_S_PH_QBR : MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC;
1130 def MULEQ_S_W_PHL : MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC;
1131 def MULEQ_S_W_PHR : MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC;
1132 def MULQ_RS_PH : MULQ_RS_PH_ENC, MULQ_RS_PH_DESC;
1133 def MULSAQ_S_W_PH : MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC;
1134 def MAQ_S_W_PHL : MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC;
1135 def MAQ_S_W_PHR : MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC;
1136 def MAQ_SA_W_PHL : MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC;
1137 def MAQ_SA_W_PHR : MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC;
1138 def MFHI_DSP : MFHI_ENC, MFHI_DESC;
1139 def MFLO_DSP : MFLO_ENC, MFLO_DESC;
1140 def MTHI_DSP : MTHI_ENC, MTHI_DESC;
1141 def MTLO_DSP : MTLO_ENC, MTLO_DESC;
1142 def DPAU_H_QBL : DspMMRel, DPAU_H_QBL_ENC, DPAU_H_QBL_DESC;
1143 def DPAU_H_QBR : DspMMRel, DPAU_H_QBR_ENC, DPAU_H_QBR_DESC;
1144 def DPSU_H_QBL : DPSU_H_QBL_ENC, DPSU_H_QBL_DESC;
1145 def DPSU_H_QBR : DPSU_H_QBR_ENC, DPSU_H_QBR_DESC;
1146 def DPAQ_S_W_PH : DspMMRel, DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC;
1147 def DPSQ_S_W_PH : DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC;
1148 def DPAQ_SA_L_W : DspMMRel, DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC;
1149 def DPSQ_SA_L_W : DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC;
1150 def MULT_DSP : DspMMRel, MULT_DSP_ENC, MULT_DSP_DESC;
1151 def MULTU_DSP : DspMMRel, MULTU_DSP_ENC, MULTU_DSP_DESC;
1152 def MADD_DSP : DspMMRel, MADD_DSP_ENC, MADD_DSP_DESC;
1153 def MADDU_DSP : DspMMRel, MADDU_DSP_ENC, MADDU_DSP_DESC;
1154 def MSUB_DSP : DspMMRel, MSUB_DSP_ENC, MSUB_DSP_DESC;
1155 def MSUBU_DSP : DspMMRel, MSUBU_DSP_ENC, MSUBU_DSP_DESC;
1156 def CMPU_EQ_QB : CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC;
1157 def CMPU_LT_QB : CMPU_LT_QB_ENC, CMPU_LT_QB_DESC;
1158 def CMPU_LE_QB : CMPU_LE_QB_ENC, CMPU_LE_QB_DESC;
1159 def CMPGU_EQ_QB : CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC;
1160 def CMPGU_LT_QB : CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC;
1161 def CMPGU_LE_QB : CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC;
1162 def CMP_EQ_PH : CMP_EQ_PH_ENC, CMP_EQ_PH_DESC;
1163 def CMP_LT_PH : CMP_LT_PH_ENC, CMP_LT_PH_DESC;
1164 def CMP_LE_PH : CMP_LE_PH_ENC, CMP_LE_PH_DESC;
1165 def BITREV : BITREV_ENC, BITREV_DESC;
1166 def PACKRL_PH : PACKRL_PH_ENC, PACKRL_PH_DESC;
1167 def REPL_QB : REPL_QB_ENC, REPL_QB_DESC;
1168 def REPL_PH : REPL_PH_ENC, REPL_PH_DESC;
1169 def REPLV_QB : REPLV_QB_ENC, REPLV_QB_DESC;
1170 def REPLV_PH : REPLV_PH_ENC, REPLV_PH_DESC;
1171 def PICK_QB : PICK_QB_ENC, PICK_QB_DESC;
1172 def PICK_PH : PICK_PH_ENC, PICK_PH_DESC;
1173 def LWX : LWX_ENC, LWX_DESC;
1174 def LHX : LHX_ENC, LHX_DESC;
1175 def LBUX : LBUX_ENC, LBUX_DESC;
1176 def BPOSGE32 : BPOSGE32_ENC, BPOSGE32_DESC;
1177 def INSV : DspMMRel, INSV_ENC, INSV_DESC;
1178 def EXTP : EXTP_ENC, EXTP_DESC;
1179 def EXTPV : EXTPV_ENC, EXTPV_DESC;
1180 def EXTPDP : EXTPDP_ENC, EXTPDP_DESC;
1181 def EXTPDPV : EXTPDPV_ENC, EXTPDPV_DESC;
1182 def EXTR_W : EXTR_W_ENC, EXTR_W_DESC;
1183 def EXTRV_W : EXTRV_W_ENC, EXTRV_W_DESC;
1184 def EXTR_R_W : EXTR_R_W_ENC, EXTR_R_W_DESC;
1185 def EXTRV_R_W : EXTRV_R_W_ENC, EXTRV_R_W_DESC;
1186 def EXTR_RS_W : EXTR_RS_W_ENC, EXTR_RS_W_DESC;
1187 def EXTRV_RS_W : EXTRV_RS_W_ENC, EXTRV_RS_W_DESC;
1188 def EXTR_S_H : EXTR_S_H_ENC, EXTR_S_H_DESC;
1189 def EXTRV_S_H : EXTRV_S_H_ENC, EXTRV_S_H_DESC;
1190 def SHILO : SHILO_ENC, SHILO_DESC;
1191 def SHILOV : SHILOV_ENC, SHILOV_DESC;
1192 def MTHLIP : MTHLIP_ENC, MTHLIP_DESC;
1193 def RDDSP : RDDSP_ENC, RDDSP_DESC;
1194 def WRDSP : WRDSP_ENC, WRDSP_DESC;
1195
1196 // MIPS DSP Rev 2
1197 let Predicates = [HasDSPR2] in {
1198
1199 def ADDU_PH : DspMMRel, ADDU_PH_ENC, ADDU_PH_DESC;
1200 def ADDU_S_PH : DspMMRel, ADDU_S_PH_ENC, ADDU_S_PH_DESC;
1201 def SUBU_PH : SUBU_PH_ENC, SUBU_PH_DESC;
1202 def SUBU_S_PH : SUBU_S_PH_ENC, SUBU_S_PH_DESC;
1203 def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC;
1204 def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC;
1205 def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC;
1206 def ABSQ_S_QB : DspMMRel, ABSQ_S_QB_ENC, ABSQ_S_QB_DESC;
1207 def ADDUH_QB : DspMMRel, ADDUH_QB_ENC, ADDUH_QB_DESC;
1208 def ADDUH_R_QB : DspMMRel, ADDUH_R_QB_ENC, ADDUH_R_QB_DESC;
1209 def SUBUH_QB : SUBUH_QB_ENC, SUBUH_QB_DESC;
1210 def SUBUH_R_QB : SUBUH_R_QB_ENC, SUBUH_R_QB_DESC;
1211 def ADDQH_PH : DspMMRel, ADDQH_PH_ENC, ADDQH_PH_DESC;
1212 def ADDQH_R_PH : DspMMRel, ADDQH_R_PH_ENC, ADDQH_R_PH_DESC;
1213 def SUBQH_PH : SUBQH_PH_ENC, SUBQH_PH_DESC;
1214 def SUBQH_R_PH : SUBQH_R_PH_ENC, SUBQH_R_PH_DESC;
1215 def ADDQH_W : DspMMRel, ADDQH_W_ENC, ADDQH_W_DESC;
1216 def ADDQH_R_W : DspMMRel, ADDQH_R_W_ENC, ADDQH_R_W_DESC;
1217 def SUBQH_W : SUBQH_W_ENC, SUBQH_W_DESC;
1218 def SUBQH_R_W : SUBQH_R_W_ENC, SUBQH_R_W_DESC;
1219 def MUL_PH : MUL_PH_ENC, MUL_PH_DESC;
1220 def MUL_S_PH : MUL_S_PH_ENC, MUL_S_PH_DESC;
1221 def MULQ_S_W : MULQ_S_W_ENC, MULQ_S_W_DESC;
1222 def MULQ_RS_W : MULQ_RS_W_ENC, MULQ_RS_W_DESC;
1223 def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC;
1224 def DPA_W_PH : DspMMRel, DPA_W_PH_ENC, DPA_W_PH_DESC;
1225 def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC;
1226 def DPAQX_S_W_PH : DspMMRel, DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC;
1227 def DPAQX_SA_W_PH : DspMMRel, DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC;
1228 def DPAX_W_PH : DspMMRel, DPAX_W_PH_ENC, DPAX_W_PH_DESC;
1229 def DPSX_W_PH : DPSX_W_PH_ENC, DPSX_W_PH_DESC;
1230 def DPSQX_S_W_PH : DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC;
1231 def DPSQX_SA_W_PH : DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC;
1232 def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC;
1233 def PRECR_QB_PH : PRECR_QB_PH_ENC, PRECR_QB_PH_DESC;
1234 def PRECR_SRA_PH_W : PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC;
1235 def PRECR_SRA_R_PH_W : PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC;
1236 def SHRA_QB : SHRA_QB_ENC, SHRA_QB_DESC;
1237 def SHRAV_QB : SHRAV_QB_ENC, SHRAV_QB_DESC;
1238 def SHRA_R_QB : SHRA_R_QB_ENC, SHRA_R_QB_DESC;
1239 def SHRAV_R_QB : SHRAV_R_QB_ENC, SHRAV_R_QB_DESC;
1240 def SHRL_PH : SHRL_PH_ENC, SHRL_PH_DESC;
1241 def SHRLV_PH : SHRLV_PH_ENC, SHRLV_PH_DESC;
1242 def APPEND : APPEND_ENC, APPEND_DESC;
1243 def BALIGN : BALIGN_ENC, BALIGN_DESC;
1244 def PREPEND : PREPEND_ENC, PREPEND_DESC;
1245
1246 }
1247
1248 // Pseudos.
1249 let isPseudo = 1, isCodeGenOnly = 1 in {
1250   // Pseudo instructions for loading and storing accumulator registers.
1251   def LOAD_ACC64DSP  : Load<"", ACC64DSPOpnd>;
1252   def STORE_ACC64DSP : Store<"", ACC64DSPOpnd>;
1253
1254   // Pseudos for loading and storing ccond field of DSP control register.
1255   def LOAD_CCOND_DSP  : Load<"load_ccond_dsp", DSPCC>;
1256   def STORE_CCOND_DSP : Store<"store_ccond_dsp", DSPCC>;
1257 }
1258
1259 // Pseudo CMP and PICK instructions.
1260 class PseudoCMP<Instruction RealInst> :
1261   PseudoDSP<(outs DSPCC:$cmp), (ins DSPROpnd:$rs, DSPROpnd:$rt), []>,
1262   PseudoInstExpansion<(RealInst DSPROpnd:$rs, DSPROpnd:$rt)>, NeverHasSideEffects;
1263
1264 class PseudoPICK<Instruction RealInst> :
1265   PseudoDSP<(outs DSPROpnd:$rd), (ins DSPCC:$cmp, DSPROpnd:$rs, DSPROpnd:$rt), []>,
1266   PseudoInstExpansion<(RealInst DSPROpnd:$rd, DSPROpnd:$rs, DSPROpnd:$rt)>,
1267   NeverHasSideEffects;
1268
1269 def PseudoCMP_EQ_PH : PseudoCMP<CMP_EQ_PH>;
1270 def PseudoCMP_LT_PH : PseudoCMP<CMP_LT_PH>;
1271 def PseudoCMP_LE_PH : PseudoCMP<CMP_LE_PH>;
1272 def PseudoCMPU_EQ_QB : PseudoCMP<CMPU_EQ_QB>;
1273 def PseudoCMPU_LT_QB : PseudoCMP<CMPU_LT_QB>;
1274 def PseudoCMPU_LE_QB : PseudoCMP<CMPU_LE_QB>;
1275
1276 def PseudoPICK_PH : PseudoPICK<PICK_PH>;
1277 def PseudoPICK_QB : PseudoPICK<PICK_QB>;
1278
1279 def PseudoMTLOHI_DSP : PseudoMTLOHI<ACC64DSP, GPR32>;
1280
1281 // Patterns.
1282 class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :
1283   Pat<pattern, result>, Requires<[pred]>;
1284
1285 class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
1286                     RegisterClass SrcRC> :
1287    DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
1288           (COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
1289
1290 def : BitconvertPat<i32, v2i16, GPR32, DSPR>;
1291 def : BitconvertPat<i32, v4i8, GPR32, DSPR>;
1292 def : BitconvertPat<v2i16, i32, DSPR, GPR32>;
1293 def : BitconvertPat<v4i8, i32, DSPR, GPR32>;
1294
1295 def : DSPPat<(v2i16 (load addr:$a)),
1296              (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1297 def : DSPPat<(v4i8 (load addr:$a)),
1298              (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1299 def : DSPPat<(store (v2i16 DSPR:$val), addr:$a),
1300              (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1301 def : DSPPat<(store (v4i8 DSPR:$val), addr:$a),
1302              (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1303
1304 // Binary operations.
1305 class DSPBinPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
1306                 Predicate Pred = HasDSP> :
1307   DSPPat<(Node ValTy:$a, ValTy:$b), (Inst ValTy:$a, ValTy:$b), Pred>;
1308
1309 def : DSPBinPat<ADDQ_PH, v2i16, int_mips_addq_ph>;
1310 def : DSPBinPat<ADDQ_PH, v2i16, add>;
1311 def : DSPBinPat<SUBQ_PH, v2i16, int_mips_subq_ph>;
1312 def : DSPBinPat<SUBQ_PH, v2i16, sub>;
1313 def : DSPBinPat<MUL_PH, v2i16, int_mips_mul_ph, HasDSPR2>;
1314 def : DSPBinPat<MUL_PH, v2i16, mul, HasDSPR2>;
1315 def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>;
1316 def : DSPBinPat<ADDU_QB, v4i8, add>;
1317 def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>;
1318 def : DSPBinPat<SUBU_QB, v4i8, sub>;
1319 def : DSPBinPat<ADDSC, i32, int_mips_addsc>;
1320 def : DSPBinPat<ADDSC, i32, addc>;
1321 def : DSPBinPat<ADDWC, i32, int_mips_addwc>;
1322 def : DSPBinPat<ADDWC, i32, adde>;
1323
1324 // Shift immediate patterns.
1325 class DSPShiftPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
1326                   SDPatternOperator Imm, Predicate Pred = HasDSP> :
1327   DSPPat<(Node ValTy:$a, Imm:$shamt), (Inst ValTy:$a, Imm:$shamt), Pred>;
1328
1329 def : DSPShiftPat<SHLL_PH, v2i16, MipsSHLL_DSP, imm>;
1330 def : DSPShiftPat<SHRA_PH, v2i16, MipsSHRA_DSP, imm>;
1331 def : DSPShiftPat<SHRL_PH, v2i16, MipsSHRL_DSP, imm, HasDSPR2>;
1332 def : DSPShiftPat<SHLL_PH, v2i16, int_mips_shll_ph, immZExt4>;
1333 def : DSPShiftPat<SHRA_PH, v2i16, int_mips_shra_ph, immZExt4>;
1334 def : DSPShiftPat<SHRL_PH, v2i16, int_mips_shrl_ph, immZExt4, HasDSPR2>;
1335 def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, imm>;
1336 def : DSPShiftPat<SHRA_QB, v4i8, MipsSHRA_DSP, imm, HasDSPR2>;
1337 def : DSPShiftPat<SHRL_QB, v4i8, MipsSHRL_DSP, imm>;
1338 def : DSPShiftPat<SHLL_QB, v4i8, int_mips_shll_qb, immZExt3>;
1339 def : DSPShiftPat<SHRA_QB, v4i8, int_mips_shra_qb, immZExt3, HasDSPR2>;
1340 def : DSPShiftPat<SHRL_QB, v4i8, int_mips_shrl_qb, immZExt3>;
1341
1342 // SETCC/SELECT_CC patterns.
1343 class DSPSetCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
1344                   CondCode CC> :
1345   DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
1346          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
1347                       (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR)),
1348                       (ValTy ZERO)))>;
1349
1350 class DSPSetCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
1351                      CondCode CC> :
1352   DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
1353          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
1354                       (ValTy ZERO),
1355                       (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR))))>;
1356
1357 class DSPSelectCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
1358                      CondCode CC> :
1359   DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),
1360          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $c, $d))>;
1361
1362 class DSPSelectCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
1363                         CondCode CC> :
1364   DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),
1365          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $d, $c))>;
1366
1367 def : DSPSetCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1368 def : DSPSetCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1369 def : DSPSetCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
1370 def : DSPSetCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1371 def : DSPSetCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
1372 def : DSPSetCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;
1373 def : DSPSetCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1374 def : DSPSetCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1375 def : DSPSetCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1376 def : DSPSetCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1377 def : DSPSetCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1378 def : DSPSetCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1379
1380 def : DSPSelectCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1381 def : DSPSelectCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1382 def : DSPSelectCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
1383 def : DSPSelectCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1384 def : DSPSelectCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
1385 def : DSPSelectCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;
1386 def : DSPSelectCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1387 def : DSPSelectCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1388 def : DSPSelectCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1389 def : DSPSelectCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1390 def : DSPSelectCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1391 def : DSPSelectCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1392
1393 // Extr patterns.
1394 class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> :
1395   DSPPat<(i32 (OpNode GPR32:$rs, ACC64DSP:$ac)),
1396          (Instr ACC64DSP:$ac, GPR32:$rs)>;
1397
1398 class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> :
1399   DSPPat<(i32 (OpNode immZExt5:$shift, ACC64DSP:$ac)),
1400          (Instr ACC64DSP:$ac, immZExt5:$shift)>;
1401
1402 def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>;
1403 def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>;
1404 def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>;
1405 def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>;
1406 def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>;
1407 def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>;
1408 def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>;
1409 def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>;
1410 def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>;
1411 def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>;
1412 def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>;
1413 def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>;
1414
1415 // Indexed load patterns.
1416 class IndexedLoadPat<SDPatternOperator LoadNode, Instruction Instr> :
1417   DSPPat<(i32 (LoadNode (add i32:$base, i32:$index))),
1418          (Instr i32:$base, i32:$index)>;
1419
1420 let AddedComplexity = 20 in {
1421   def : IndexedLoadPat<zextloadi8, LBUX>;
1422   def : IndexedLoadPat<sextloadi16, LHX>;
1423   def : IndexedLoadPat<load, LWX>;
1424 }