1 //===-- MipsAsmPrinter.cpp - Mips LLVM assembly writer --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-asm-printer"
17 #include "MipsAsmPrinter.h"
18 #include "MipsInstrInfo.h"
19 #include "MipsMachineFunction.h"
20 #include "MipsMCInstLower.h"
21 #include "MipsMCSymbolRefExpr.h"
22 #include "InstPrinter/MipsInstPrinter.h"
23 #include "llvm/ADT/SmallString.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/Analysis/DebugInfo.h"
27 #include "llvm/BasicBlock.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineConstantPool.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineInstr.h"
33 #include "llvm/CodeGen/MachineMemOperand.h"
34 #include "llvm/Instructions.h"
35 #include "llvm/MC/MCStreamer.h"
36 #include "llvm/MC/MCAsmInfo.h"
37 #include "llvm/MC/MCInst.h"
38 #include "llvm/MC/MCSymbol.h"
39 #include "llvm/Support/TargetRegistry.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/Mangler.h"
42 #include "llvm/Target/TargetData.h"
43 #include "llvm/Target/TargetLoweringObjectFile.h"
44 #include "llvm/Target/TargetOptions.h"
48 static bool isUnalignedLoadStore(unsigned Opc) {
49 return Opc == Mips::ULW || Opc == Mips::ULH || Opc == Mips::ULHu ||
50 Opc == Mips::USW || Opc == Mips::USH ||
51 Opc == Mips::ULW_P8 || Opc == Mips::ULH_P8 || Opc == Mips::ULHu_P8 ||
52 Opc == Mips::USW_P8 || Opc == Mips::USH_P8;
55 static bool isDirective(unsigned Opc) {
56 return Opc == Mips::MACRO || Opc == Mips::NOMACRO ||
57 Opc == Mips::REORDER || Opc == Mips::NOREORDER ||
58 Opc == Mips::ATMACRO || Opc == Mips::NOAT;
61 void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
63 raw_svector_ostream OS(Str);
65 if (MI->isDebugValue()) {
66 PrintDebugValueComment(MI, OS);
70 MipsMCInstLower MCInstLowering(Mang, *MF, *this);
71 unsigned Opc = MI->getOpcode();
73 SmallVector<MCInst, 4> MCInsts;
74 MCInstLowering.Lower(MI, TmpInst0);
76 if (!OutStreamer.hasRawTextSupport() && isDirective(Opc))
79 // Enclose unaligned load or store with .macro & .nomacro directives.
80 if (isUnalignedLoadStore(Opc)) {
82 Directive.setOpcode(Mips::MACRO);
83 OutStreamer.EmitInstruction(Directive);
84 OutStreamer.EmitInstruction(TmpInst0);
85 Directive.setOpcode(Mips::NOMACRO);
86 OutStreamer.EmitInstruction(Directive);
90 if (!OutStreamer.hasRawTextSupport()) {
91 // Lower CPLOAD and CPRESTORE
92 if (Opc == Mips::CPLOAD) {
93 MCInstLowering.LowerCPLOAD(MI, MCInsts);
94 for (SmallVector<MCInst, 4>::iterator I = MCInsts.begin();
95 I != MCInsts.end(); ++I)
96 OutStreamer.EmitInstruction(*I);
100 if (Opc == Mips::CPRESTORE) {
101 MCInstLowering.LowerCPRESTORE(MI, TmpInst0);
102 OutStreamer.EmitInstruction(TmpInst0);
107 OutStreamer.EmitInstruction(TmpInst0);
110 //===----------------------------------------------------------------------===//
112 // Mips Asm Directives
114 // -- Frame directive "frame Stackpointer, Stacksize, RARegister"
115 // Describe the stack frame.
117 // -- Mask directives "(f)mask bitmask, offset"
118 // Tells the assembler which registers are saved and where.
119 // bitmask - contain a little endian bitset indicating which registers are
120 // saved on function prologue (e.g. with a 0x80000000 mask, the
121 // assembler knows the register 31 (RA) is saved at prologue.
122 // offset - the position before stack pointer subtraction indicating where
123 // the first saved register on prologue is located. (e.g. with a
125 // Consider the following function prologue:
128 // .mask 0xc0000000,-8
129 // addiu $sp, $sp, -48
133 // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
134 // 30 (FP) are saved at prologue. As the save order on prologue is from
135 // left to right, RA is saved first. A -8 offset means that after the
136 // stack pointer subtration, the first register in the mask (RA) will be
137 // saved at address 48-8=40.
139 //===----------------------------------------------------------------------===//
141 //===----------------------------------------------------------------------===//
143 //===----------------------------------------------------------------------===//
145 // Create a bitmask with all callee saved registers for CPU or Floating Point
146 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
147 void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) {
148 // CPU and FPU Saved Registers Bitmasks
149 unsigned CPUBitmask = 0, FPUBitmask = 0;
150 int CPUTopSavedRegOff, FPUTopSavedRegOff;
152 // Set the CPU and FPU Bitmasks
153 const MachineFrameInfo *MFI = MF->getFrameInfo();
154 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
155 // size of stack area to which FP callee-saved regs are saved.
156 unsigned CPURegSize = Mips::CPURegsRegisterClass->getSize();
157 unsigned FGR32RegSize = Mips::FGR32RegisterClass->getSize();
158 unsigned AFGR64RegSize = Mips::AFGR64RegisterClass->getSize();
159 bool HasAFGR64Reg = false;
160 unsigned CSFPRegsSize = 0;
161 unsigned i, e = CSI.size();
164 for (i = 0; i != e; ++i) {
165 unsigned Reg = CSI[i].getReg();
166 if (Mips::CPURegsRegisterClass->contains(Reg))
169 unsigned RegNum = MipsRegisterInfo::getRegisterNumbering(Reg);
170 if (Mips::AFGR64RegisterClass->contains(Reg)) {
171 FPUBitmask |= (3 << RegNum);
172 CSFPRegsSize += AFGR64RegSize;
177 FPUBitmask |= (1 << RegNum);
178 CSFPRegsSize += FGR32RegSize;
182 for (; i != e; ++i) {
183 unsigned Reg = CSI[i].getReg();
184 unsigned RegNum = MipsRegisterInfo::getRegisterNumbering(Reg);
185 CPUBitmask |= (1 << RegNum);
188 // FP Regs are saved right below where the virtual frame pointer points to.
189 FPUTopSavedRegOff = FPUBitmask ?
190 (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
192 // CPU Regs are saved below FP Regs.
193 CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
196 O << "\t.mask \t"; printHex32(CPUBitmask, O);
197 O << ',' << CPUTopSavedRegOff << '\n';
200 O << "\t.fmask\t"; printHex32(FPUBitmask, O);
201 O << "," << FPUTopSavedRegOff << '\n';
204 // Print a 32 bit hex number with all numbers.
205 void MipsAsmPrinter::printHex32(unsigned Value, raw_ostream &O) {
207 for (int i = 7; i >= 0; i--)
208 O.write_hex((Value & (0xF << (i*4))) >> (i*4));
211 //===----------------------------------------------------------------------===//
212 // Frame and Set directives
213 //===----------------------------------------------------------------------===//
216 void MipsAsmPrinter::emitFrameDirective() {
217 const TargetRegisterInfo &RI = *TM.getRegisterInfo();
219 unsigned stackReg = RI.getFrameRegister(*MF);
220 unsigned returnReg = RI.getRARegister();
221 unsigned stackSize = MF->getFrameInfo()->getStackSize();
223 if (OutStreamer.hasRawTextSupport())
224 OutStreamer.EmitRawText("\t.frame\t$" +
225 StringRef(MipsInstPrinter::getRegisterName(stackReg)).lower() +
226 "," + Twine(stackSize) + ",$" +
227 StringRef(MipsInstPrinter::getRegisterName(returnReg)).lower());
230 /// Emit Set directives.
231 const char *MipsAsmPrinter::getCurrentABIString() const {
232 switch (Subtarget->getTargetABI()) {
233 case MipsSubtarget::O32: return "abi32";
234 case MipsSubtarget::N32: return "abiN32";
235 case MipsSubtarget::N64: return "abi64";
236 case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64
240 llvm_unreachable("Unknown Mips ABI");
244 void MipsAsmPrinter::EmitFunctionEntryLabel() {
245 if (OutStreamer.hasRawTextSupport())
246 OutStreamer.EmitRawText("\t.ent\t" + Twine(CurrentFnSym->getName()));
247 OutStreamer.EmitLabel(CurrentFnSym);
250 /// EmitFunctionBodyStart - Targets can override this to emit stuff before
251 /// the first basic block in the function.
252 void MipsAsmPrinter::EmitFunctionBodyStart() {
253 emitFrameDirective();
255 if (OutStreamer.hasRawTextSupport()) {
256 SmallString<128> Str;
257 raw_svector_ostream OS(Str);
258 printSavedRegsBitmask(OS);
259 OutStreamer.EmitRawText(OS.str());
263 /// EmitFunctionBodyEnd - Targets can override this to emit stuff after
264 /// the last basic block in the function.
265 void MipsAsmPrinter::EmitFunctionBodyEnd() {
266 // There are instruction for this macros, but they must
267 // always be at the function end, and we can't emit and
268 // break with BB logic.
269 if (OutStreamer.hasRawTextSupport()) {
270 OutStreamer.EmitRawText(StringRef("\t.set\tmacro"));
271 OutStreamer.EmitRawText(StringRef("\t.set\treorder"));
272 OutStreamer.EmitRawText("\t.end\t" + Twine(CurrentFnSym->getName()));
276 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
277 /// exactly one predecessor and the control transfer mechanism between
278 /// the predecessor and this block is a fall-through.
279 bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
281 // The predecessor has to be immediately before this block.
282 const MachineBasicBlock *Pred = *MBB->pred_begin();
284 // If the predecessor is a switch statement, assume a jump table
285 // implementation, so it is not a fall through.
286 if (const BasicBlock *bb = Pred->getBasicBlock())
287 if (isa<SwitchInst>(bb->getTerminator()))
290 // If this is a landing pad, it isn't a fall through. If it has no preds,
291 // then nothing falls through to it.
292 if (MBB->isLandingPad() || MBB->pred_empty())
295 // If there isn't exactly one predecessor, it can't be a fall through.
296 MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
299 if (PI2 != MBB->pred_end())
302 // The predecessor has to be immediately before this block.
303 if (!Pred->isLayoutSuccessor(MBB))
306 // If the block is completely empty, then it definitely does fall through.
310 // Otherwise, check the last instruction.
311 // Check if the last terminator is an unconditional branch.
312 MachineBasicBlock::const_iterator I = Pred->end();
313 while (I != Pred->begin() && !(--I)->getDesc().isTerminator()) ;
315 return !I->getDesc().isBarrier();
318 // Print out an operand for an inline asm expression.
319 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
320 unsigned AsmVariant,const char *ExtraCode,
322 // Does this asm operand have a single letter operand modifier?
323 if (ExtraCode && ExtraCode[0])
324 return true; // Unknown modifier.
326 printOperand(MI, OpNo, O);
330 bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
331 unsigned OpNum, unsigned AsmVariant,
332 const char *ExtraCode,
334 if (ExtraCode && ExtraCode[0])
335 return true; // Unknown modifier.
337 const MachineOperand &MO = MI->getOperand(OpNum);
338 assert(MO.isReg() && "unexpected inline asm memory operand");
339 O << "0($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")";
343 void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
345 const MachineOperand &MO = MI->getOperand(opNum);
348 if (MO.getTargetFlags())
351 switch(MO.getTargetFlags()) {
352 case MipsII::MO_GPREL: O << "%gp_rel("; break;
353 case MipsII::MO_GOT_CALL: O << "%call16("; break;
354 case MipsII::MO_GOT: O << "%got("; break;
355 case MipsII::MO_ABS_HI: O << "%hi("; break;
356 case MipsII::MO_ABS_LO: O << "%lo("; break;
357 case MipsII::MO_TLSGD: O << "%tlsgd("; break;
358 case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
359 case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
360 case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
361 case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
362 case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
363 case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
364 case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
365 case MipsII::MO_GOT_OFST: O << "%got_ofst("; break;
368 switch (MO.getType()) {
369 case MachineOperand::MO_Register:
371 << StringRef(MipsInstPrinter::getRegisterName(MO.getReg())).lower();
374 case MachineOperand::MO_Immediate:
378 case MachineOperand::MO_MachineBasicBlock:
379 O << *MO.getMBB()->getSymbol();
382 case MachineOperand::MO_GlobalAddress:
383 O << *Mang->getSymbol(MO.getGlobal());
386 case MachineOperand::MO_BlockAddress: {
387 MCSymbol* BA = GetBlockAddressSymbol(MO.getBlockAddress());
392 case MachineOperand::MO_ExternalSymbol:
393 O << *GetExternalSymbolSymbol(MO.getSymbolName());
396 case MachineOperand::MO_JumpTableIndex:
397 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
398 << '_' << MO.getIndex();
401 case MachineOperand::MO_ConstantPoolIndex:
402 O << MAI->getPrivateGlobalPrefix() << "CPI"
403 << getFunctionNumber() << "_" << MO.getIndex();
405 O << "+" << MO.getOffset();
409 llvm_unreachable("<unknown operand type>");
412 if (closeP) O << ")";
415 void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum,
417 const MachineOperand &MO = MI->getOperand(opNum);
419 O << (unsigned short int)MO.getImm();
421 printOperand(MI, opNum, O);
424 void MipsAsmPrinter::
425 printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
426 // Load/Store memory operands -- imm($reg)
427 // If PIC target the target is loaded as the
428 // pattern lw $25,%call16($28)
429 printOperand(MI, opNum+1, O);
431 printOperand(MI, opNum, O);
435 void MipsAsmPrinter::
436 printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
437 // when using stack locations for not load/store instructions
438 // print the same way as all normal 3 operand instructions.
439 printOperand(MI, opNum, O);
441 printOperand(MI, opNum+1, O);
445 void MipsAsmPrinter::
446 printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
447 const char *Modifier) {
448 const MachineOperand& MO = MI->getOperand(opNum);
449 O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
452 void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
453 // FIXME: Use SwitchSection.
455 // Tell the assembler which ABI we are using
456 if (OutStreamer.hasRawTextSupport())
457 OutStreamer.EmitRawText("\t.section .mdebug." + Twine(getCurrentABIString()));
459 // TODO: handle O64 ABI
460 if (OutStreamer.hasRawTextSupport()) {
461 if (Subtarget->isABI_EABI()) {
462 if (Subtarget->isGP32bit())
463 OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long32"));
465 OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long64"));
469 // return to previous section
470 if (OutStreamer.hasRawTextSupport())
471 OutStreamer.EmitRawText(StringRef("\t.previous"));
475 MipsAsmPrinter::getDebugValueLocation(const MachineInstr *MI) const {
476 // Handles frame addresses emitted in MipsInstrInfo::emitFrameIndexDebugValue.
477 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
478 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm() &&
479 "Unexpected MachineOperand types");
480 return MachineLocation(MI->getOperand(0).getReg(),
481 MI->getOperand(1).getImm());
484 void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
489 // Force static initialization.
490 extern "C" void LLVMInitializeMipsAsmPrinter() {
491 RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
492 RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);
493 RegisterAsmPrinter<MipsAsmPrinter> A(TheMips64Target);
494 RegisterAsmPrinter<MipsAsmPrinter> B(TheMips64elTarget);