1 //===-- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-asm-printer"
16 #include "InstPrinter/MipsInstPrinter.h"
17 #include "MCTargetDesc/MipsBaseInfo.h"
19 #include "MipsAsmPrinter.h"
20 #include "MipsInstrInfo.h"
21 #include "MipsMCInstLower.h"
22 #include "MipsTargetStreamer.h"
23 #include "llvm/ADT/SmallString.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineInstr.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/IR/BasicBlock.h"
32 #include "llvm/IR/DataLayout.h"
33 #include "llvm/IR/InlineAsm.h"
34 #include "llvm/IR/Instructions.h"
35 #include "llvm/IR/Mangler.h"
36 #include "llvm/MC/MCAsmInfo.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCELFStreamer.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCSectionELF.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/Support/ELF.h"
43 #include "llvm/Support/TargetRegistry.h"
44 #include "llvm/Support/raw_ostream.h"
45 #include "llvm/Target/TargetLoweringObjectFile.h"
46 #include "llvm/Target/TargetOptions.h"
50 MipsTargetStreamer &MipsAsmPrinter::getTargetStreamer() {
51 return static_cast<MipsTargetStreamer &>(*OutStreamer.getTargetStreamer());
54 bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
55 // Initialize TargetLoweringObjectFile.
56 if (Subtarget->allowMixed16_32())
57 const_cast<TargetLoweringObjectFile&>(getObjFileLowering())
58 .Initialize(OutContext, TM);
59 MipsFI = MF.getInfo<MipsFunctionInfo>();
60 MCP = MF.getConstantPool();
61 AsmPrinter::runOnMachineFunction(MF);
65 bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) {
66 MCOp = MCInstLowering.LowerOperand(MO);
67 return MCOp.isValid();
70 #include "MipsGenMCPseudoLowering.inc"
72 void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
73 if (MI->isDebugValue()) {
75 raw_svector_ostream OS(Str);
77 PrintDebugValueComment(MI, OS);
81 // If we just ended a constant pool, mark it as such.
82 if (InConstantPool && MI->getOpcode() != Mips::CONSTPOOL_ENTRY) {
83 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
84 InConstantPool = false;
86 if (MI->getOpcode() == Mips::CONSTPOOL_ENTRY) {
87 // CONSTPOOL_ENTRY - This instruction represents a floating
88 //constant pool in the function. The first operand is the ID#
89 // for this instruction, the second is the index into the
90 // MachineConstantPool that this is, the third is the size in
91 // bytes of this constant pool entry.
92 // The required alignment is specified on the basic block holding this MI.
94 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
95 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
97 // If this is the first entry of the pool, mark it.
98 if (!InConstantPool) {
99 OutStreamer.EmitDataRegion(MCDR_DataRegion);
100 InConstantPool = true;
103 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
105 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
106 if (MCPE.isMachineConstantPoolEntry())
107 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
109 EmitGlobalConstant(MCPE.Val.ConstVal);
114 MachineBasicBlock::const_instr_iterator I = MI;
115 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
118 // Do any auto-generated pseudo lowerings.
119 if (emitPseudoExpansionLowering(OutStreamer, &*I))
122 // The inMips16Mode() test is not permanent.
123 // Some instructions are marked as pseudo right now which
124 // would make the test fail for the wrong reason but
125 // that will be fixed soon. We need this here because we are
126 // removing another test for this situation downstream in the
129 if (I->isPseudo() && !Subtarget->inMips16Mode())
130 llvm_unreachable("Pseudo opcode found in EmitInstruction()");
133 MCInstLowering.Lower(I, TmpInst0);
134 OutStreamer.EmitInstruction(TmpInst0);
135 } while ((++I != E) && I->isInsideBundle()); // Delay slot check
138 //===----------------------------------------------------------------------===//
140 // Mips Asm Directives
142 // -- Frame directive "frame Stackpointer, Stacksize, RARegister"
143 // Describe the stack frame.
145 // -- Mask directives "(f)mask bitmask, offset"
146 // Tells the assembler which registers are saved and where.
147 // bitmask - contain a little endian bitset indicating which registers are
148 // saved on function prologue (e.g. with a 0x80000000 mask, the
149 // assembler knows the register 31 (RA) is saved at prologue.
150 // offset - the position before stack pointer subtraction indicating where
151 // the first saved register on prologue is located. (e.g. with a
153 // Consider the following function prologue:
156 // .mask 0xc0000000,-8
157 // addiu $sp, $sp, -48
161 // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
162 // 30 (FP) are saved at prologue. As the save order on prologue is from
163 // left to right, RA is saved first. A -8 offset means that after the
164 // stack pointer subtration, the first register in the mask (RA) will be
165 // saved at address 48-8=40.
167 //===----------------------------------------------------------------------===//
169 //===----------------------------------------------------------------------===//
171 //===----------------------------------------------------------------------===//
173 // Create a bitmask with all callee saved registers for CPU or Floating Point
174 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
175 void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) {
176 // CPU and FPU Saved Registers Bitmasks
177 unsigned CPUBitmask = 0, FPUBitmask = 0;
178 int CPUTopSavedRegOff, FPUTopSavedRegOff;
180 // Set the CPU and FPU Bitmasks
181 const MachineFrameInfo *MFI = MF->getFrameInfo();
182 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
183 // size of stack area to which FP callee-saved regs are saved.
184 unsigned CPURegSize = Mips::GPR32RegClass.getSize();
185 unsigned FGR32RegSize = Mips::FGR32RegClass.getSize();
186 unsigned AFGR64RegSize = Mips::AFGR64RegClass.getSize();
187 bool HasAFGR64Reg = false;
188 unsigned CSFPRegsSize = 0;
189 unsigned i, e = CSI.size();
192 for (i = 0; i != e; ++i) {
193 unsigned Reg = CSI[i].getReg();
194 if (Mips::GPR32RegClass.contains(Reg))
197 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg);
198 if (Mips::AFGR64RegClass.contains(Reg)) {
199 FPUBitmask |= (3 << RegNum);
200 CSFPRegsSize += AFGR64RegSize;
205 FPUBitmask |= (1 << RegNum);
206 CSFPRegsSize += FGR32RegSize;
210 for (; i != e; ++i) {
211 unsigned Reg = CSI[i].getReg();
212 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg);
213 CPUBitmask |= (1 << RegNum);
216 // FP Regs are saved right below where the virtual frame pointer points to.
217 FPUTopSavedRegOff = FPUBitmask ?
218 (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
220 // CPU Regs are saved below FP Regs.
221 CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
224 O << "\t.mask \t"; printHex32(CPUBitmask, O);
225 O << ',' << CPUTopSavedRegOff << '\n';
228 O << "\t.fmask\t"; printHex32(FPUBitmask, O);
229 O << "," << FPUTopSavedRegOff << '\n';
232 // Print a 32 bit hex number with all numbers.
233 void MipsAsmPrinter::printHex32(unsigned Value, raw_ostream &O) {
235 for (int i = 7; i >= 0; i--)
236 O.write_hex((Value & (0xF << (i*4))) >> (i*4));
239 //===----------------------------------------------------------------------===//
240 // Frame and Set directives
241 //===----------------------------------------------------------------------===//
244 void MipsAsmPrinter::emitFrameDirective() {
245 const TargetRegisterInfo &RI = *TM.getRegisterInfo();
247 unsigned stackReg = RI.getFrameRegister(*MF);
248 unsigned returnReg = RI.getRARegister();
249 unsigned stackSize = MF->getFrameInfo()->getStackSize();
251 if (OutStreamer.hasRawTextSupport())
252 OutStreamer.EmitRawText("\t.frame\t$" +
253 StringRef(MipsInstPrinter::getRegisterName(stackReg)).lower() +
254 "," + Twine(stackSize) + ",$" +
255 StringRef(MipsInstPrinter::getRegisterName(returnReg)).lower());
258 /// Emit Set directives.
259 const char *MipsAsmPrinter::getCurrentABIString() const {
260 switch (Subtarget->getTargetABI()) {
261 case MipsSubtarget::O32: return "abi32";
262 case MipsSubtarget::N32: return "abiN32";
263 case MipsSubtarget::N64: return "abi64";
264 case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64
265 default: llvm_unreachable("Unknown Mips ABI");
269 void MipsAsmPrinter::EmitFunctionEntryLabel() {
270 MipsTargetStreamer &TS = getTargetStreamer();
271 if (Subtarget->inMicroMipsMode())
272 TS.emitDirectiveSetMicroMips();
273 // leave out until FSF available gas has micromips changes
275 // TS.emitDirectiveSetNoMicroMips();
277 if (Subtarget->inMips16Mode())
278 TS.emitDirectiveSetMips16();
280 TS.emitDirectiveSetNoMips16();
282 TS.emitDirectiveEnt(*CurrentFnSym);
283 OutStreamer.EmitLabel(CurrentFnSym);
286 /// EmitFunctionBodyStart - Targets can override this to emit stuff before
287 /// the first basic block in the function.
288 void MipsAsmPrinter::EmitFunctionBodyStart() {
289 MipsTargetStreamer &TS = getTargetStreamer();
291 MCInstLowering.Initialize(&MF->getContext());
293 bool IsNakedFunction =
295 getAttributes().hasAttribute(AttributeSet::FunctionIndex,
297 if (!IsNakedFunction)
298 emitFrameDirective();
300 if (OutStreamer.hasRawTextSupport()) {
301 SmallString<128> Str;
302 raw_svector_ostream OS(Str);
303 if (!IsNakedFunction)
304 printSavedRegsBitmask(OS);
305 OutStreamer.EmitRawText(OS.str());
307 if (!Subtarget->inMips16Mode()) {
308 TS.emitDirectiveSetNoReorder();
309 TS.emitDirectiveSetNoMacro();
310 TS.emitDirectiveSetNoAt();
314 /// EmitFunctionBodyEnd - Targets can override this to emit stuff after
315 /// the last basic block in the function.
316 void MipsAsmPrinter::EmitFunctionBodyEnd() {
317 MipsTargetStreamer &TS = getTargetStreamer();
319 // There are instruction for this macros, but they must
320 // always be at the function end, and we can't emit and
321 // break with BB logic.
322 if (!Subtarget->inMips16Mode()) {
323 TS.emitDirectiveSetAt();
324 TS.emitDirectiveSetMacro();
325 TS.emitDirectiveSetReorder();
327 TS.emitDirectiveEnd(CurrentFnSym->getName());
328 // Make sure to terminate any constant pools that were at the end
332 InConstantPool = false;
333 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
336 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
337 /// exactly one predecessor and the control transfer mechanism between
338 /// the predecessor and this block is a fall-through.
339 bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
341 // The predecessor has to be immediately before this block.
342 const MachineBasicBlock *Pred = *MBB->pred_begin();
344 // If the predecessor is a switch statement, assume a jump table
345 // implementation, so it is not a fall through.
346 if (const BasicBlock *bb = Pred->getBasicBlock())
347 if (isa<SwitchInst>(bb->getTerminator()))
350 // If this is a landing pad, it isn't a fall through. If it has no preds,
351 // then nothing falls through to it.
352 if (MBB->isLandingPad() || MBB->pred_empty())
355 // If there isn't exactly one predecessor, it can't be a fall through.
356 MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
359 if (PI2 != MBB->pred_end())
362 // The predecessor has to be immediately before this block.
363 if (!Pred->isLayoutSuccessor(MBB))
366 // If the block is completely empty, then it definitely does fall through.
370 // Otherwise, check the last instruction.
371 // Check if the last terminator is an unconditional branch.
372 MachineBasicBlock::const_iterator I = Pred->end();
373 while (I != Pred->begin() && !(--I)->isTerminator()) ;
375 return !I->isBarrier();
378 // Print out an operand for an inline asm expression.
379 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
380 unsigned AsmVariant,const char *ExtraCode,
382 // Does this asm operand have a single letter operand modifier?
383 if (ExtraCode && ExtraCode[0]) {
384 if (ExtraCode[1] != 0) return true; // Unknown modifier.
386 const MachineOperand &MO = MI->getOperand(OpNum);
387 switch (ExtraCode[0]) {
389 // See if this is a generic print operand
390 return AsmPrinter::PrintAsmOperand(MI,OpNum,AsmVariant,ExtraCode,O);
391 case 'X': // hex const int
392 if ((MO.getType()) != MachineOperand::MO_Immediate)
394 O << "0x" << StringRef(utohexstr(MO.getImm())).lower();
396 case 'x': // hex const int (low 16 bits)
397 if ((MO.getType()) != MachineOperand::MO_Immediate)
399 O << "0x" << StringRef(utohexstr(MO.getImm() & 0xffff)).lower();
401 case 'd': // decimal const int
402 if ((MO.getType()) != MachineOperand::MO_Immediate)
406 case 'm': // decimal const int minus 1
407 if ((MO.getType()) != MachineOperand::MO_Immediate)
409 O << MO.getImm() - 1;
412 // $0 if zero, regular printing otherwise
413 if (MO.getType() != MachineOperand::MO_Immediate)
415 int64_t Val = MO.getImm();
422 case 'D': // Second part of a double word register operand
423 case 'L': // Low order register of a double word register operand
424 case 'M': // High order register of a double word register operand
428 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
429 if (!FlagsOP.isImm())
431 unsigned Flags = FlagsOP.getImm();
432 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
433 // Number of registers represented by this operand. We are looking
434 // for 2 for 32 bit mode and 1 for 64 bit mode.
436 if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) {
437 unsigned Reg = MO.getReg();
438 O << '$' << MipsInstPrinter::getRegisterName(Reg);
444 unsigned RegOp = OpNum;
445 if (!Subtarget->isGP64bit()){
446 // Endianess reverses which register holds the high or low value
448 switch(ExtraCode[0]) {
450 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
453 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1;
455 case 'D': // Always the second part
458 if (RegOp >= MI->getNumOperands())
460 const MachineOperand &MO = MI->getOperand(RegOp);
463 unsigned Reg = MO.getReg();
464 O << '$' << MipsInstPrinter::getRegisterName(Reg);
469 // Print MSA registers for the 'f' constraint
470 // In LLVM, the 'w' modifier doesn't need to do anything.
471 // We can just call printOperand as normal.
476 printOperand(MI, OpNum, O);
480 bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
481 unsigned OpNum, unsigned AsmVariant,
482 const char *ExtraCode,
485 // Currently we are expecting either no ExtraCode or 'D'
487 if (ExtraCode[0] == 'D')
490 return true; // Unknown modifier.
493 const MachineOperand &MO = MI->getOperand(OpNum);
494 assert(MO.isReg() && "unexpected inline asm memory operand");
495 O << Offset << "($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")";
500 void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
502 const DataLayout *DL = TM.getDataLayout();
503 const MachineOperand &MO = MI->getOperand(opNum);
506 if (MO.getTargetFlags())
509 switch(MO.getTargetFlags()) {
510 case MipsII::MO_GPREL: O << "%gp_rel("; break;
511 case MipsII::MO_GOT_CALL: O << "%call16("; break;
512 case MipsII::MO_GOT: O << "%got("; break;
513 case MipsII::MO_ABS_HI: O << "%hi("; break;
514 case MipsII::MO_ABS_LO: O << "%lo("; break;
515 case MipsII::MO_TLSGD: O << "%tlsgd("; break;
516 case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
517 case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
518 case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
519 case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
520 case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
521 case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
522 case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
523 case MipsII::MO_GOT_OFST: O << "%got_ofst("; break;
526 switch (MO.getType()) {
527 case MachineOperand::MO_Register:
529 << StringRef(MipsInstPrinter::getRegisterName(MO.getReg())).lower();
532 case MachineOperand::MO_Immediate:
536 case MachineOperand::MO_MachineBasicBlock:
537 O << *MO.getMBB()->getSymbol();
540 case MachineOperand::MO_GlobalAddress:
541 O << *getSymbol(MO.getGlobal());
544 case MachineOperand::MO_BlockAddress: {
545 MCSymbol *BA = GetBlockAddressSymbol(MO.getBlockAddress());
550 case MachineOperand::MO_ConstantPoolIndex:
551 O << DL->getPrivateGlobalPrefix() << "CPI"
552 << getFunctionNumber() << "_" << MO.getIndex();
554 O << "+" << MO.getOffset();
558 llvm_unreachable("<unknown operand type>");
561 if (closeP) O << ")";
564 void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum,
566 const MachineOperand &MO = MI->getOperand(opNum);
568 O << (unsigned short int)MO.getImm();
570 printOperand(MI, opNum, O);
573 void MipsAsmPrinter::printUnsignedImm8(const MachineInstr *MI, int opNum,
575 const MachineOperand &MO = MI->getOperand(opNum);
577 O << (unsigned short int)(unsigned char)MO.getImm();
579 printOperand(MI, opNum, O);
582 void MipsAsmPrinter::
583 printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
584 // Load/Store memory operands -- imm($reg)
585 // If PIC target the target is loaded as the
586 // pattern lw $25,%call16($28)
587 printOperand(MI, opNum+1, O);
589 printOperand(MI, opNum, O);
593 void MipsAsmPrinter::
594 printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
595 // when using stack locations for not load/store instructions
596 // print the same way as all normal 3 operand instructions.
597 printOperand(MI, opNum, O);
599 printOperand(MI, opNum+1, O);
603 void MipsAsmPrinter::
604 printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
605 const char *Modifier) {
606 const MachineOperand &MO = MI->getOperand(opNum);
607 O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
610 void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
611 // TODO: Need to add -mabicalls and -mno-abicalls flags.
612 // Currently we assume that -mabicalls is the default.
613 getTargetStreamer().emitDirectiveAbiCalls();
614 Reloc::Model RM = Subtarget->getRelocationModel();
615 if (RM == Reloc::Static && !Subtarget->hasMips64())
616 getTargetStreamer().emitDirectiveOptionPic0();
618 // Tell the assembler which ABI we are using
619 std::string SectionName = std::string(".mdebug.") + getCurrentABIString();
620 OutStreamer.SwitchSection(OutContext.getELFSection(
621 SectionName, ELF::SHT_PROGBITS, 0, SectionKind::getDataRel()));
623 // TODO: handle O64 ABI
625 if (Subtarget->isABI_EABI()) {
626 if (Subtarget->isGP32bit())
627 OutStreamer.SwitchSection(
628 OutContext.getELFSection(".gcc_compiled_long32", ELF::SHT_PROGBITS, 0,
629 SectionKind::getDataRel()));
631 OutStreamer.SwitchSection(
632 OutContext.getELFSection(".gcc_compiled_long64", ELF::SHT_PROGBITS, 0,
633 SectionKind::getDataRel()));
636 // return to the text section
637 OutStreamer.SwitchSection(OutContext.getObjectFileInfo()->getTextSection());
640 void MipsAsmPrinter::EmitEndOfAsmFile(Module &M) {
641 // Emit Mips ELF register info
642 Subtarget->getMReginfo().emitMipsReginfoSectionCG(
643 OutStreamer, getObjFileLowering(), *Subtarget);
646 void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
651 // Force static initialization.
652 extern "C" void LLVMInitializeMipsAsmPrinter() {
653 RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
654 RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);
655 RegisterAsmPrinter<MipsAsmPrinter> A(TheMips64Target);
656 RegisterAsmPrinter<MipsAsmPrinter> B(TheMips64elTarget);