1 //===-- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-asm-printer"
16 #include "InstPrinter/MipsInstPrinter.h"
17 #include "MCTargetDesc/MipsBaseInfo.h"
19 #include "MipsAsmPrinter.h"
20 #include "MipsInstrInfo.h"
21 #include "MipsMCInstLower.h"
22 #include "MipsTargetStreamer.h"
23 #include "llvm/ADT/SmallString.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineInstr.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/IR/BasicBlock.h"
32 #include "llvm/IR/DataLayout.h"
33 #include "llvm/IR/InlineAsm.h"
34 #include "llvm/IR/Instructions.h"
35 #include "llvm/IR/Mangler.h"
36 #include "llvm/MC/MCAsmInfo.h"
37 #include "llvm/MC/MCELFStreamer.h"
38 #include "llvm/MC/MCInst.h"
39 #include "llvm/MC/MCSymbol.h"
40 #include "llvm/Support/ELF.h"
41 #include "llvm/Support/TargetRegistry.h"
42 #include "llvm/Support/raw_ostream.h"
43 #include "llvm/Target/TargetLoweringObjectFile.h"
44 #include "llvm/Target/TargetOptions.h"
48 MipsTargetStreamer &MipsAsmPrinter::getTargetStreamer() {
49 return static_cast<MipsTargetStreamer &>(*OutStreamer.getTargetStreamer());
52 bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
53 // Initialize TargetLoweringObjectFile.
54 if (Subtarget->allowMixed16_32())
55 const_cast<TargetLoweringObjectFile&>(getObjFileLowering())
56 .Initialize(OutContext, TM);
57 MipsFI = MF.getInfo<MipsFunctionInfo>();
58 MCP = MF.getConstantPool();
59 AsmPrinter::runOnMachineFunction(MF);
63 bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) {
64 MCOp = MCInstLowering.LowerOperand(MO);
65 return MCOp.isValid();
68 #include "MipsGenMCPseudoLowering.inc"
70 void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
71 if (MI->isDebugValue()) {
73 raw_svector_ostream OS(Str);
75 PrintDebugValueComment(MI, OS);
79 // If we just ended a constant pool, mark it as such.
80 if (InConstantPool && MI->getOpcode() != Mips::CONSTPOOL_ENTRY) {
81 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
82 InConstantPool = false;
84 if (MI->getOpcode() == Mips::CONSTPOOL_ENTRY) {
85 // CONSTPOOL_ENTRY - This instruction represents a floating
86 //constant pool in the function. The first operand is the ID#
87 // for this instruction, the second is the index into the
88 // MachineConstantPool that this is, the third is the size in
89 // bytes of this constant pool entry.
90 // The required alignment is specified on the basic block holding this MI.
92 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
93 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
95 // If this is the first entry of the pool, mark it.
96 if (!InConstantPool) {
97 OutStreamer.EmitDataRegion(MCDR_DataRegion);
98 InConstantPool = true;
101 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
103 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
104 if (MCPE.isMachineConstantPoolEntry())
105 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
107 EmitGlobalConstant(MCPE.Val.ConstVal);
111 MachineBasicBlock::const_instr_iterator I = MI;
112 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
115 // Do any auto-generated pseudo lowerings.
116 if (emitPseudoExpansionLowering(OutStreamer, &*I))
119 // The inMips16Mode() test is not permanent.
120 // Some instructions are marked as pseudo right now which
121 // would make the test fail for the wrong reason but
122 // that will be fixed soon. We need this here because we are
123 // removing another test for this situation downstream in the
126 if (I->isPseudo() && !Subtarget->inMips16Mode())
127 llvm_unreachable("Pseudo opcode found in EmitInstruction()");
130 MCInstLowering.Lower(I, TmpInst0);
131 OutStreamer.EmitInstruction(TmpInst0);
132 } while ((++I != E) && I->isInsideBundle()); // Delay slot check
135 //===----------------------------------------------------------------------===//
137 // Mips Asm Directives
139 // -- Frame directive "frame Stackpointer, Stacksize, RARegister"
140 // Describe the stack frame.
142 // -- Mask directives "(f)mask bitmask, offset"
143 // Tells the assembler which registers are saved and where.
144 // bitmask - contain a little endian bitset indicating which registers are
145 // saved on function prologue (e.g. with a 0x80000000 mask, the
146 // assembler knows the register 31 (RA) is saved at prologue.
147 // offset - the position before stack pointer subtraction indicating where
148 // the first saved register on prologue is located. (e.g. with a
150 // Consider the following function prologue:
153 // .mask 0xc0000000,-8
154 // addiu $sp, $sp, -48
158 // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
159 // 30 (FP) are saved at prologue. As the save order on prologue is from
160 // left to right, RA is saved first. A -8 offset means that after the
161 // stack pointer subtration, the first register in the mask (RA) will be
162 // saved at address 48-8=40.
164 //===----------------------------------------------------------------------===//
166 //===----------------------------------------------------------------------===//
168 //===----------------------------------------------------------------------===//
170 // Create a bitmask with all callee saved registers for CPU or Floating Point
171 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
172 void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) {
173 // CPU and FPU Saved Registers Bitmasks
174 unsigned CPUBitmask = 0, FPUBitmask = 0;
175 int CPUTopSavedRegOff, FPUTopSavedRegOff;
177 // Set the CPU and FPU Bitmasks
178 const MachineFrameInfo *MFI = MF->getFrameInfo();
179 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
180 // size of stack area to which FP callee-saved regs are saved.
181 unsigned CPURegSize = Mips::GPR32RegClass.getSize();
182 unsigned FGR32RegSize = Mips::FGR32RegClass.getSize();
183 unsigned AFGR64RegSize = Mips::AFGR64RegClass.getSize();
184 bool HasAFGR64Reg = false;
185 unsigned CSFPRegsSize = 0;
186 unsigned i, e = CSI.size();
189 for (i = 0; i != e; ++i) {
190 unsigned Reg = CSI[i].getReg();
191 if (Mips::GPR32RegClass.contains(Reg))
194 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg);
195 if (Mips::AFGR64RegClass.contains(Reg)) {
196 FPUBitmask |= (3 << RegNum);
197 CSFPRegsSize += AFGR64RegSize;
202 FPUBitmask |= (1 << RegNum);
203 CSFPRegsSize += FGR32RegSize;
207 for (; i != e; ++i) {
208 unsigned Reg = CSI[i].getReg();
209 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg);
210 CPUBitmask |= (1 << RegNum);
213 // FP Regs are saved right below where the virtual frame pointer points to.
214 FPUTopSavedRegOff = FPUBitmask ?
215 (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
217 // CPU Regs are saved below FP Regs.
218 CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
221 O << "\t.mask \t"; printHex32(CPUBitmask, O);
222 O << ',' << CPUTopSavedRegOff << '\n';
225 O << "\t.fmask\t"; printHex32(FPUBitmask, O);
226 O << "," << FPUTopSavedRegOff << '\n';
229 // Print a 32 bit hex number with all numbers.
230 void MipsAsmPrinter::printHex32(unsigned Value, raw_ostream &O) {
232 for (int i = 7; i >= 0; i--)
233 O.write_hex((Value & (0xF << (i*4))) >> (i*4));
236 //===----------------------------------------------------------------------===//
237 // Frame and Set directives
238 //===----------------------------------------------------------------------===//
241 void MipsAsmPrinter::emitFrameDirective() {
242 const TargetRegisterInfo &RI = *TM.getRegisterInfo();
244 unsigned stackReg = RI.getFrameRegister(*MF);
245 unsigned returnReg = RI.getRARegister();
246 unsigned stackSize = MF->getFrameInfo()->getStackSize();
248 if (OutStreamer.hasRawTextSupport())
249 OutStreamer.EmitRawText("\t.frame\t$" +
250 StringRef(MipsInstPrinter::getRegisterName(stackReg)).lower() +
251 "," + Twine(stackSize) + ",$" +
252 StringRef(MipsInstPrinter::getRegisterName(returnReg)).lower());
255 /// Emit Set directives.
256 const char *MipsAsmPrinter::getCurrentABIString() const {
257 switch (Subtarget->getTargetABI()) {
258 case MipsSubtarget::O32: return "abi32";
259 case MipsSubtarget::N32: return "abiN32";
260 case MipsSubtarget::N64: return "abi64";
261 case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64
262 default: llvm_unreachable("Unknown Mips ABI");
266 void MipsAsmPrinter::EmitFunctionEntryLabel() {
267 MipsTargetStreamer &TS = getTargetStreamer();
268 if (Subtarget->inMicroMipsMode())
269 TS.emitDirectiveSetMicroMips();
270 // leave out until FSF available gas has micromips changes
272 // TS.emitDirectiveSetNoMicroMips();
274 if (Subtarget->inMips16Mode())
275 TS.emitDirectiveSetMips16();
277 TS.emitDirectiveSetNoMips16();
279 TS.emitDirectiveEnt(*CurrentFnSym);
280 OutStreamer.EmitLabel(CurrentFnSym);
283 /// EmitFunctionBodyStart - Targets can override this to emit stuff before
284 /// the first basic block in the function.
285 void MipsAsmPrinter::EmitFunctionBodyStart() {
286 MCInstLowering.Initialize(&MF->getContext());
288 bool IsNakedFunction =
290 getAttributes().hasAttribute(AttributeSet::FunctionIndex,
292 if (!IsNakedFunction)
293 emitFrameDirective();
295 if (OutStreamer.hasRawTextSupport()) {
296 SmallString<128> Str;
297 raw_svector_ostream OS(Str);
298 if (!IsNakedFunction)
299 printSavedRegsBitmask(OS);
300 OutStreamer.EmitRawText(OS.str());
301 if (!Subtarget->inMips16Mode()) {
302 OutStreamer.EmitRawText(StringRef("\t.set\tnoreorder"));
303 OutStreamer.EmitRawText(StringRef("\t.set\tnomacro"));
304 OutStreamer.EmitRawText(StringRef("\t.set\tnoat"));
309 /// EmitFunctionBodyEnd - Targets can override this to emit stuff after
310 /// the last basic block in the function.
311 void MipsAsmPrinter::EmitFunctionBodyEnd() {
312 // There are instruction for this macros, but they must
313 // always be at the function end, and we can't emit and
314 // break with BB logic.
315 if (OutStreamer.hasRawTextSupport()) {
316 if (!Subtarget->inMips16Mode()) {
317 OutStreamer.EmitRawText(StringRef("\t.set\tat"));
318 OutStreamer.EmitRawText(StringRef("\t.set\tmacro"));
319 OutStreamer.EmitRawText(StringRef("\t.set\treorder"));
321 OutStreamer.EmitRawText("\t.end\t" + Twine(CurrentFnSym->getName()));
323 // Make sure to terminate any constant pools that were at the end
327 InConstantPool = false;
328 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
331 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
332 /// exactly one predecessor and the control transfer mechanism between
333 /// the predecessor and this block is a fall-through.
334 bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
336 // The predecessor has to be immediately before this block.
337 const MachineBasicBlock *Pred = *MBB->pred_begin();
339 // If the predecessor is a switch statement, assume a jump table
340 // implementation, so it is not a fall through.
341 if (const BasicBlock *bb = Pred->getBasicBlock())
342 if (isa<SwitchInst>(bb->getTerminator()))
345 // If this is a landing pad, it isn't a fall through. If it has no preds,
346 // then nothing falls through to it.
347 if (MBB->isLandingPad() || MBB->pred_empty())
350 // If there isn't exactly one predecessor, it can't be a fall through.
351 MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
354 if (PI2 != MBB->pred_end())
357 // The predecessor has to be immediately before this block.
358 if (!Pred->isLayoutSuccessor(MBB))
361 // If the block is completely empty, then it definitely does fall through.
365 // Otherwise, check the last instruction.
366 // Check if the last terminator is an unconditional branch.
367 MachineBasicBlock::const_iterator I = Pred->end();
368 while (I != Pred->begin() && !(--I)->isTerminator()) ;
370 return !I->isBarrier();
373 // Print out an operand for an inline asm expression.
374 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
375 unsigned AsmVariant,const char *ExtraCode,
377 // Does this asm operand have a single letter operand modifier?
378 if (ExtraCode && ExtraCode[0]) {
379 if (ExtraCode[1] != 0) return true; // Unknown modifier.
381 const MachineOperand &MO = MI->getOperand(OpNum);
382 switch (ExtraCode[0]) {
384 // See if this is a generic print operand
385 return AsmPrinter::PrintAsmOperand(MI,OpNum,AsmVariant,ExtraCode,O);
386 case 'X': // hex const int
387 if ((MO.getType()) != MachineOperand::MO_Immediate)
389 O << "0x" << StringRef(utohexstr(MO.getImm())).lower();
391 case 'x': // hex const int (low 16 bits)
392 if ((MO.getType()) != MachineOperand::MO_Immediate)
394 O << "0x" << StringRef(utohexstr(MO.getImm() & 0xffff)).lower();
396 case 'd': // decimal const int
397 if ((MO.getType()) != MachineOperand::MO_Immediate)
401 case 'm': // decimal const int minus 1
402 if ((MO.getType()) != MachineOperand::MO_Immediate)
404 O << MO.getImm() - 1;
407 // $0 if zero, regular printing otherwise
408 if (MO.getType() != MachineOperand::MO_Immediate)
410 int64_t Val = MO.getImm();
417 case 'D': // Second part of a double word register operand
418 case 'L': // Low order register of a double word register operand
419 case 'M': // High order register of a double word register operand
423 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
424 if (!FlagsOP.isImm())
426 unsigned Flags = FlagsOP.getImm();
427 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
428 // Number of registers represented by this operand. We are looking
429 // for 2 for 32 bit mode and 1 for 64 bit mode.
431 if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) {
432 unsigned Reg = MO.getReg();
433 O << '$' << MipsInstPrinter::getRegisterName(Reg);
439 unsigned RegOp = OpNum;
440 if (!Subtarget->isGP64bit()){
441 // Endianess reverses which register holds the high or low value
443 switch(ExtraCode[0]) {
445 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
448 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1;
450 case 'D': // Always the second part
453 if (RegOp >= MI->getNumOperands())
455 const MachineOperand &MO = MI->getOperand(RegOp);
458 unsigned Reg = MO.getReg();
459 O << '$' << MipsInstPrinter::getRegisterName(Reg);
464 // Print MSA registers for the 'f' constraint
465 // In LLVM, the 'w' modifier doesn't need to do anything.
466 // We can just call printOperand as normal.
471 printOperand(MI, OpNum, O);
475 bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
476 unsigned OpNum, unsigned AsmVariant,
477 const char *ExtraCode,
480 // Currently we are expecting either no ExtraCode or 'D'
482 if (ExtraCode[0] == 'D')
485 return true; // Unknown modifier.
488 const MachineOperand &MO = MI->getOperand(OpNum);
489 assert(MO.isReg() && "unexpected inline asm memory operand");
490 O << Offset << "($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")";
495 void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
497 const DataLayout *DL = TM.getDataLayout();
498 const MachineOperand &MO = MI->getOperand(opNum);
501 if (MO.getTargetFlags())
504 switch(MO.getTargetFlags()) {
505 case MipsII::MO_GPREL: O << "%gp_rel("; break;
506 case MipsII::MO_GOT_CALL: O << "%call16("; break;
507 case MipsII::MO_GOT: O << "%got("; break;
508 case MipsII::MO_ABS_HI: O << "%hi("; break;
509 case MipsII::MO_ABS_LO: O << "%lo("; break;
510 case MipsII::MO_TLSGD: O << "%tlsgd("; break;
511 case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
512 case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
513 case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
514 case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
515 case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
516 case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
517 case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
518 case MipsII::MO_GOT_OFST: O << "%got_ofst("; break;
521 switch (MO.getType()) {
522 case MachineOperand::MO_Register:
524 << StringRef(MipsInstPrinter::getRegisterName(MO.getReg())).lower();
527 case MachineOperand::MO_Immediate:
531 case MachineOperand::MO_MachineBasicBlock:
532 O << *MO.getMBB()->getSymbol();
535 case MachineOperand::MO_GlobalAddress:
536 O << *getSymbol(MO.getGlobal());
539 case MachineOperand::MO_BlockAddress: {
540 MCSymbol *BA = GetBlockAddressSymbol(MO.getBlockAddress());
545 case MachineOperand::MO_ConstantPoolIndex:
546 O << DL->getPrivateGlobalPrefix() << "CPI"
547 << getFunctionNumber() << "_" << MO.getIndex();
549 O << "+" << MO.getOffset();
553 llvm_unreachable("<unknown operand type>");
556 if (closeP) O << ")";
559 void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum,
561 const MachineOperand &MO = MI->getOperand(opNum);
563 O << (unsigned short int)MO.getImm();
565 printOperand(MI, opNum, O);
568 void MipsAsmPrinter::printUnsignedImm8(const MachineInstr *MI, int opNum,
570 const MachineOperand &MO = MI->getOperand(opNum);
572 O << (unsigned short int)(unsigned char)MO.getImm();
574 printOperand(MI, opNum, O);
577 void MipsAsmPrinter::
578 printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
579 // Load/Store memory operands -- imm($reg)
580 // If PIC target the target is loaded as the
581 // pattern lw $25,%call16($28)
582 printOperand(MI, opNum+1, O);
584 printOperand(MI, opNum, O);
588 void MipsAsmPrinter::
589 printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
590 // when using stack locations for not load/store instructions
591 // print the same way as all normal 3 operand instructions.
592 printOperand(MI, opNum, O);
594 printOperand(MI, opNum+1, O);
598 void MipsAsmPrinter::
599 printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
600 const char *Modifier) {
601 const MachineOperand &MO = MI->getOperand(opNum);
602 O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
605 void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
606 // FIXME: Use SwitchSection.
608 // TODO: Need to add -mabicalls and -mno-abicalls flags.
609 // Currently we assume that -mabicalls is the default.
610 getTargetStreamer().emitDirectiveAbiCalls();
611 Reloc::Model RM = Subtarget->getRelocationModel();
612 if (RM == Reloc::Static && !Subtarget->hasMips64())
613 getTargetStreamer().emitDirectiveOptionPic0();
615 // Tell the assembler which ABI we are using
616 if (OutStreamer.hasRawTextSupport())
617 OutStreamer.EmitRawText("\t.section .mdebug." +
618 Twine(getCurrentABIString()));
620 // TODO: handle O64 ABI
621 if (OutStreamer.hasRawTextSupport()) {
622 if (Subtarget->isABI_EABI()) {
623 if (Subtarget->isGP32bit())
624 OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long32"));
626 OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long64"));
630 // return to previous section
631 if (OutStreamer.hasRawTextSupport())
632 OutStreamer.EmitRawText(StringRef("\t.previous"));
636 void MipsAsmPrinter::processInitialEFlags() {
637 // Not having this check would work too, but would have us chew through
638 // code that it doesn't use for RawText.
639 if (OutStreamer.hasRawTextSupport())
642 // Update e_header flags
645 // TODO: Need to add -mabicalls and -mno-abicalls flags.
646 // Currently we assume that -mabicalls is the default.
647 EFlags |= ELF::EF_MIPS_CPIC;
649 if (Subtarget->inMips16Mode())
650 EFlags |= ELF::EF_MIPS_ARCH_ASE_M16;
652 EFlags |= ELF::EF_MIPS_NOREORDER;
655 if (Subtarget->hasMips64r2())
656 EFlags |= ELF::EF_MIPS_ARCH_64R2;
657 else if (Subtarget->hasMips64())
658 EFlags |= ELF::EF_MIPS_ARCH_64;
659 else if (Subtarget->hasMips32r2())
660 EFlags |= ELF::EF_MIPS_ARCH_32R2;
662 EFlags |= ELF::EF_MIPS_ARCH_32;
664 if (Subtarget->inMicroMipsMode())
665 EFlags |= ELF::EF_MIPS_MICROMIPS;
668 if (Subtarget->isABI_O32())
669 EFlags |= ELF::EF_MIPS_ABI_O32;
672 Reloc::Model RM = Subtarget->getRelocationModel();
673 if (RM == Reloc::PIC_ || RM == Reloc::Default)
674 EFlags |= ELF::EF_MIPS_PIC;
675 else if (RM == Reloc::Static)
676 ; // Do nothing for Reloc::Static
678 llvm_unreachable("Unsupported relocation model for e_flags");
680 getTargetStreamer().emitMipsELFFlags(EFlags);
683 void MipsAsmPrinter::EmitEndOfAsmFile(Module &M) {
684 // Emit Mips ELF register info
685 Subtarget->getMReginfo().emitMipsReginfoSectionCG(
686 OutStreamer, getObjFileLowering(), *Subtarget);
689 void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
694 // Force static initialization.
695 extern "C" void LLVMInitializeMipsAsmPrinter() {
696 RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
697 RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);
698 RegisterAsmPrinter<MipsAsmPrinter> A(TheMips64Target);
699 RegisterAsmPrinter<MipsAsmPrinter> B(TheMips64elTarget);