1 //===-- MipsAsmPrinter.cpp - Mips LLVM assembly writer --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-asm-printer"
17 #include "MipsSubtarget.h"
18 #include "MipsInstrInfo.h"
19 #include "MipsTargetMachine.h"
20 #include "MipsMachineFunction.h"
21 #include "llvm/BasicBlock.h"
22 #include "llvm/Instructions.h"
23 #include "llvm/CodeGen/AsmPrinter.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstr.h"
28 #include "llvm/MC/MCStreamer.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/MC/MCSymbol.h"
31 #include "llvm/Target/Mangler.h"
32 #include "llvm/Target/TargetData.h"
33 #include "llvm/Target/TargetLoweringObjectFile.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/Target/TargetRegistry.h"
37 #include "llvm/ADT/SmallString.h"
38 #include "llvm/ADT/StringExtras.h"
39 #include "llvm/ADT/Twine.h"
40 #include "llvm/Support/raw_ostream.h"
44 class MipsAsmPrinter : public AsmPrinter {
45 const MipsSubtarget *Subtarget;
47 explicit MipsAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
48 : AsmPrinter(TM, Streamer) {
49 Subtarget = &TM.getSubtarget<MipsSubtarget>();
52 virtual const char *getPassName() const {
53 return "Mips Assembly Printer";
56 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
57 unsigned AsmVariant, const char *ExtraCode,
59 void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
60 void printUnsignedImm(const MachineInstr *MI, int opNum, raw_ostream &O);
61 void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
62 const char *Modifier = 0);
63 void printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
64 const char *Modifier = 0);
65 void printSavedRegsBitmask(raw_ostream &O);
66 void printHex32(unsigned int Value, raw_ostream &O);
68 const char *getCurrentABIString() const;
69 void emitFrameDirective();
71 void printInstruction(const MachineInstr *MI, raw_ostream &O); // autogen'd.
72 void EmitInstruction(const MachineInstr *MI) {
74 raw_svector_ostream OS(Str);
75 printInstruction(MI, OS);
76 OutStreamer.EmitRawText(OS.str());
78 virtual void EmitFunctionBodyStart();
79 virtual void EmitFunctionBodyEnd();
80 virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
82 static const char *getRegisterName(unsigned RegNo);
84 virtual void EmitFunctionEntryLabel();
85 void EmitStartOfAsmFile(Module &M);
87 } // end of anonymous namespace
89 #include "MipsGenAsmWriter.inc"
91 //===----------------------------------------------------------------------===//
93 // Mips Asm Directives
95 // -- Frame directive "frame Stackpointer, Stacksize, RARegister"
96 // Describe the stack frame.
98 // -- Mask directives "(f)mask bitmask, offset"
99 // Tells the assembler which registers are saved and where.
100 // bitmask - contain a little endian bitset indicating which registers are
101 // saved on function prologue (e.g. with a 0x80000000 mask, the
102 // assembler knows the register 31 (RA) is saved at prologue.
103 // offset - the position before stack pointer subtraction indicating where
104 // the first saved register on prologue is located. (e.g. with a
106 // Consider the following function prologue:
109 // .mask 0xc0000000,-8
110 // addiu $sp, $sp, -48
114 // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
115 // 30 (FP) are saved at prologue. As the save order on prologue is from
116 // left to right, RA is saved first. A -8 offset means that after the
117 // stack pointer subtration, the first register in the mask (RA) will be
118 // saved at address 48-8=40.
120 //===----------------------------------------------------------------------===//
122 //===----------------------------------------------------------------------===//
124 //===----------------------------------------------------------------------===//
126 // Create a bitmask with all callee saved registers for CPU or Floating Point
127 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
128 void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) {
129 const TargetFrameLowering *TFI = TM.getFrameLowering();
130 const TargetRegisterInfo *RI = TM.getRegisterInfo();
131 const MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>();
133 // CPU and FPU Saved Registers Bitmasks
134 unsigned int CPUBitmask = 0;
135 unsigned int FPUBitmask = 0;
137 // Set the CPU and FPU Bitmasks
138 const MachineFrameInfo *MFI = MF->getFrameInfo();
139 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
140 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
141 unsigned Reg = CSI[i].getReg();
142 unsigned RegNum = MipsRegisterInfo::getRegisterNumbering(Reg);
143 if (Mips::CPURegsRegisterClass->contains(Reg))
144 CPUBitmask |= (1 << RegNum);
146 FPUBitmask |= (1 << RegNum);
149 // Return Address and Frame registers must also be set in CPUBitmask.
150 // FIXME: Do we really need hasFP() call here? When no FP is present SP is
151 // just returned -- will it be ok?
153 CPUBitmask |= (1 << MipsRegisterInfo::
154 getRegisterNumbering(RI->getFrameRegister(*MF)));
156 if (MFI->adjustsStack())
157 CPUBitmask |= (1 << MipsRegisterInfo::
158 getRegisterNumbering(RI->getRARegister()));
161 O << "\t.mask \t"; printHex32(CPUBitmask, O);
162 O << ',' << MipsFI->getCPUTopSavedRegOff() << '\n';
165 O << "\t.fmask\t"; printHex32(FPUBitmask, O); O << ","
166 << MipsFI->getFPUTopSavedRegOff() << '\n';
169 // Print a 32 bit hex number with all numbers.
170 void MipsAsmPrinter::printHex32(unsigned Value, raw_ostream &O) {
172 for (int i = 7; i >= 0; i--)
173 O << utohexstr((Value & (0xF << (i*4))) >> (i*4));
176 //===----------------------------------------------------------------------===//
177 // Frame and Set directives
178 //===----------------------------------------------------------------------===//
181 void MipsAsmPrinter::emitFrameDirective() {
182 const TargetRegisterInfo &RI = *TM.getRegisterInfo();
184 unsigned stackReg = RI.getFrameRegister(*MF);
185 unsigned returnReg = RI.getRARegister();
186 unsigned stackSize = MF->getFrameInfo()->getStackSize();
188 OutStreamer.EmitRawText("\t.frame\t$" +
189 Twine(LowercaseString(getRegisterName(stackReg))) +
190 "," + Twine(stackSize) + ",$" +
191 Twine(LowercaseString(getRegisterName(returnReg))));
194 /// Emit Set directives.
195 const char *MipsAsmPrinter::getCurrentABIString() const {
196 switch (Subtarget->getTargetABI()) {
197 case MipsSubtarget::O32: return "abi32";
198 case MipsSubtarget::O64: return "abiO64";
199 case MipsSubtarget::N32: return "abiN32";
200 case MipsSubtarget::N64: return "abi64";
201 case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64
205 llvm_unreachable("Unknown Mips ABI");
209 void MipsAsmPrinter::EmitFunctionEntryLabel() {
210 OutStreamer.EmitRawText("\t.ent\t" + Twine(CurrentFnSym->getName()));
211 OutStreamer.EmitLabel(CurrentFnSym);
214 /// EmitFunctionBodyStart - Targets can override this to emit stuff before
215 /// the first basic block in the function.
216 void MipsAsmPrinter::EmitFunctionBodyStart() {
217 emitFrameDirective();
219 SmallString<128> Str;
220 raw_svector_ostream OS(Str);
221 printSavedRegsBitmask(OS);
222 OutStreamer.EmitRawText(OS.str());
225 /// EmitFunctionBodyEnd - Targets can override this to emit stuff after
226 /// the last basic block in the function.
227 void MipsAsmPrinter::EmitFunctionBodyEnd() {
228 // There are instruction for this macros, but they must
229 // always be at the function end, and we can't emit and
230 // break with BB logic.
231 OutStreamer.EmitRawText(StringRef("\t.set\tmacro"));
232 OutStreamer.EmitRawText(StringRef("\t.set\treorder"));
233 OutStreamer.EmitRawText("\t.end\t" + Twine(CurrentFnSym->getName()));
237 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
238 /// exactly one predecessor and the control transfer mechanism between
239 /// the predecessor and this block is a fall-through.
240 bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
242 // The predecessor has to be immediately before this block.
243 const MachineBasicBlock *Pred = *MBB->pred_begin();
245 // If the predecessor is a switch statement, assume a jump table
246 // implementation, so it is not a fall through.
247 if (const BasicBlock *bb = Pred->getBasicBlock())
248 if (isa<SwitchInst>(bb->getTerminator()))
251 // If this is a landing pad, it isn't a fall through. If it has no preds,
252 // then nothing falls through to it.
253 if (MBB->isLandingPad() || MBB->pred_empty())
256 // If there isn't exactly one predecessor, it can't be a fall through.
257 MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
260 if (PI2 != MBB->pred_end())
263 // The predecessor has to be immediately before this block.
264 if (!Pred->isLayoutSuccessor(MBB))
267 // If the block is completely empty, then it definitely does fall through.
271 // Otherwise, check the last instruction.
272 // Check if the last terminator is an unconditional branch.
273 MachineBasicBlock::const_iterator I = Pred->end();
274 while (I != Pred->begin() && !(--I)->getDesc().isTerminator()) ;
276 return !I->getDesc().isBarrier();
279 // Print out an operand for an inline asm expression.
280 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
281 unsigned AsmVariant,const char *ExtraCode,
283 // Does this asm operand have a single letter operand modifier?
284 if (ExtraCode && ExtraCode[0])
285 return true; // Unknown modifier.
287 printOperand(MI, OpNo, O);
291 void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
293 const MachineOperand &MO = MI->getOperand(opNum);
296 if (MO.getTargetFlags())
299 switch(MO.getTargetFlags()) {
300 case MipsII::MO_GPREL: O << "%gp_rel("; break;
301 case MipsII::MO_GOT_CALL: O << "%call16("; break;
302 case MipsII::MO_GOT: O << "%got("; break;
303 case MipsII::MO_ABS_HI: O << "%hi("; break;
304 case MipsII::MO_ABS_LO: O << "%lo("; break;
307 switch (MO.getType()) {
308 case MachineOperand::MO_Register:
309 O << '$' << LowercaseString(getRegisterName(MO.getReg()));
312 case MachineOperand::MO_Immediate:
313 O << (short int)MO.getImm();
316 case MachineOperand::MO_MachineBasicBlock:
317 O << *MO.getMBB()->getSymbol();
320 case MachineOperand::MO_GlobalAddress:
321 O << *Mang->getSymbol(MO.getGlobal());
324 case MachineOperand::MO_BlockAddress: {
325 MCSymbol* BA = GetBlockAddressSymbol(MO.getBlockAddress());
330 case MachineOperand::MO_ExternalSymbol:
331 O << *GetExternalSymbolSymbol(MO.getSymbolName());
334 case MachineOperand::MO_JumpTableIndex:
335 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
336 << '_' << MO.getIndex();
339 case MachineOperand::MO_ConstantPoolIndex:
340 O << MAI->getPrivateGlobalPrefix() << "CPI"
341 << getFunctionNumber() << "_" << MO.getIndex();
343 O << "+" << MO.getOffset();
347 llvm_unreachable("<unknown operand type>");
350 if (closeP) O << ")";
353 void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum,
355 const MachineOperand &MO = MI->getOperand(opNum);
357 O << (unsigned short int)MO.getImm();
359 printOperand(MI, opNum, O);
362 void MipsAsmPrinter::
363 printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
364 const char *Modifier) {
365 // when using stack locations for not load/store instructions
366 // print the same way as all normal 3 operand instructions.
367 if (Modifier && !strcmp(Modifier, "stackloc")) {
368 printOperand(MI, opNum+1, O);
370 printOperand(MI, opNum, O);
374 // Load/Store memory operands -- imm($reg)
375 // If PIC target the target is loaded as the
376 // pattern lw $25,%call16($28)
377 printOperand(MI, opNum, O);
379 printOperand(MI, opNum+1, O);
383 void MipsAsmPrinter::
384 printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
385 const char *Modifier) {
386 const MachineOperand& MO = MI->getOperand(opNum);
387 O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
390 void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
391 // FIXME: Use SwitchSection.
393 // Tell the assembler which ABI we are using
394 OutStreamer.EmitRawText("\t.section .mdebug." + Twine(getCurrentABIString()));
396 // TODO: handle O64 ABI
397 if (Subtarget->isABI_EABI()) {
398 if (Subtarget->isGP32bit())
399 OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long32"));
401 OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long64"));
404 // return to previous section
405 OutStreamer.EmitRawText(StringRef("\t.previous"));
408 // Force static initialization.
409 extern "C" void LLVMInitializeMipsAsmPrinter() {
410 RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
411 RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);