1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips32r6 instructions.
12 //===----------------------------------------------------------------------===//
14 include "Mips32r6InstrFormats.td"
16 // Notes about removals/changes from MIPS32r6:
18 // Reencoded: cache, pref
19 // Reencoded: clo, clz
20 // Reencoded: jr -> jalr
21 // Reencoded: jr.hb -> jalr.hb
28 // Removed: /.ps$/, cvt.ps.s, cvt.ps.pw
30 // Removed: bc1any2, bc1any4
32 // Removed: bc2f, bc2t
35 // Removed: c.cond.fmt, bc1[ft]
40 // Removed: lwl, lwr, lwle, lwre, swl, swr, swle, swre
42 // Removed: madd.[ds], nmadd.[ds], nmsub.[ds], sub.[ds]
43 // Removed: mfhi, mflo, mthi, mtlo, madd, maddu, msub, msubu, mul
44 // Removed: movf, movt
45 // Removed: movf.fmt, movt.fmt, movn.fmt, movz.fmt
46 // Removed: movn, movz
47 // Removed: mult, multu
52 // Removed: teqi, tgei, tgeiu, tlti, tltiu, tnei
53 // Rencoded: [ls][wd]c2
55 //===----------------------------------------------------------------------===//
57 // Instruction Encodings
59 //===----------------------------------------------------------------------===//
61 class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>;
62 class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>;
63 class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
64 class AUI_ENC : AUI_FM;
65 class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;
66 class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>;
67 class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
68 class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
69 class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;
70 class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>;
71 class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>;
72 class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>;
73 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
74 class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>;
76 class MADDF_S_ENC : COP1_3R_FM<0b011000, FIELD_FMT_S>;
77 class MADDF_D_ENC : COP1_3R_FM<0b011000, FIELD_FMT_D>;
78 class MSUBF_S_ENC : COP1_3R_FM<0b011001, FIELD_FMT_S>;
79 class MSUBF_D_ENC : COP1_3R_FM<0b011001, FIELD_FMT_D>;
81 class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>;
82 class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>;
84 class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
85 class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
86 class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>;
87 class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>;
89 class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>;
90 class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>;
91 class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>;
92 class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>;
94 class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>;
95 class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>;
96 class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>;
97 class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>;
99 class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>;
100 class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>;
101 class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>;
102 class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>;
104 //===----------------------------------------------------------------------===//
106 // Instruction Descriptions
108 //===----------------------------------------------------------------------===//
110 class ADDIUPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
111 dag OutOperandList = (outs GPROpnd:$rs);
112 dag InOperandList = (ins simm19_lsl2:$imm);
113 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
114 list<dag> Pattern = [];
117 class ADDIUPC_DESC : ADDIUPC_DESC_BASE<"addiupc", GPR32Opnd>;
119 class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
121 dag OutOperandList = (outs GPROpnd:$rd);
122 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
123 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
124 list<dag> Pattern = [];
127 class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2>;
129 class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
130 dag OutOperandList = (outs GPROpnd:$rs);
131 dag InOperandList = (ins simm16:$imm);
132 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
133 list<dag> Pattern = [];
136 class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>;
137 class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>;
139 class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
140 dag OutOperandList = (outs GPROpnd:$rs);
141 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
142 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
143 list<dag> Pattern = [];
146 class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
148 class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
149 dag OutOperandList = (outs GPROpnd:$rd);
150 dag InOperandList = (ins GPROpnd:$rt);
151 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
152 list<dag> Pattern = [];
155 class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>;
157 class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
158 dag OutOperandList = (outs GPROpnd:$rd);
159 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
160 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
161 list<dag> Pattern = [];
164 class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd>;
165 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd>;
166 class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd>;
167 class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd>;
169 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
170 dag OutOperandList = (outs GPROpnd:$rd);
171 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
172 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
173 list<dag> Pattern = [];
176 class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd>;
177 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd>;
178 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd>;
179 class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
181 class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
182 dag OutOperandList = (outs FGROpnd:$fd);
183 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
184 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
185 list<dag> Pattern = [];
186 string Constraints = "$fd_in = $fd";
189 class SEL_D_DESC : COP1_4R_DESC_BASE<"sel.d", FGR64Opnd>;
190 class SEL_S_DESC : COP1_4R_DESC_BASE<"sel.s", FGR32Opnd>;
192 class MADDF_S_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>;
193 class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>;
194 class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>;
195 class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>;
197 class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
198 dag OutOperandList = (outs FGROpnd:$fd);
199 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
200 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
201 list<dag> Pattern = [];
204 class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>;
205 class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>;
206 class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>;
207 class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>;
209 class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>;
210 class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>;
211 class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>;
212 class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>;
214 class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
215 dag OutOperandList = (outs FGROpnd:$fd);
216 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
217 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
218 list<dag> Pattern = [];
221 class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
222 class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
223 class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
224 class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
226 class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
227 dag OutOperandList = (outs FGROpnd:$fd);
228 dag InOperandList = (ins FGROpnd:$fs);
229 string AsmString = !strconcat(instr_asm, "\t$fd, $fs");
230 list<dag> Pattern = [];
233 class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>;
234 class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>;
235 class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>;
236 class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>;
238 //===----------------------------------------------------------------------===//
240 // Instruction Definitions
242 //===----------------------------------------------------------------------===//
244 def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
245 def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
246 def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
247 def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
248 def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
258 def BGEC; // Also aliased to blec with operands swapped
259 def BGEUC; // Also aliased to bleuc with operands swapped
264 def BITSWAP : BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
267 def BLTC; // Also aliased to bgtc with operands swapped
268 def BLTUC; // Also aliased to bgtuc with operands swapped
276 def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6;
277 def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6;
280 def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;
281 def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
284 // def LSA; // See MSA
287 def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6;
288 def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6;
289 def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6;
290 def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6;
291 def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6;
292 def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6;
293 def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6;
294 def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6;
295 def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6;
296 def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6;
297 def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6;
298 def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6;
299 def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6;
300 def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6;
301 def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6;
302 def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
303 def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
304 def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6;
305 def NAL; // BAL with rd=0
306 def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6;
307 def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6;
309 def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6;
310 def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6;
312 def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6;
313 def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6;
314 def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6;
315 def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6;