1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips32r6 instructions.
12 //===----------------------------------------------------------------------===//
14 include "Mips32r6InstrFormats.td"
16 // Notes about removals/changes from MIPS32r6:
18 // Reencoded: cache, pref
19 // Reencoded: clo, clz
20 // Reencoded: jr -> jalr
21 // Reencoded: jr.hb -> jalr.hb
28 // Removed: bc1any2, bc1any4
30 // Removed: bc2f, bc2t
33 // Removed: c.cond.fmt, bc1[ft]
38 // Removed: lwl, lwr, lwle, lwre, swl, swr, swle, swre
40 // Removed: madd.[ds], nmadd.[ds], nmsub.[ds], sub.[ds]
41 // Removed: mfhi, mflo, mthi, mtlo, madd, maddu, msub, msubu, mul
42 // Removed: movf, movt
43 // Removed: movf.fmt, movt.fmt, movn.fmt, movz.fmt
44 // Removed: movn, movz
45 // Removed: mult, multu
50 // Removed: teqi, tgei, tgeiu, tlti, tltiu, tnei
51 // Rencoded: [ls][wd]c2
53 def brtarget21 : Operand<OtherVT> {
54 let EncoderMethod = "getBranchTarget21OpValue";
55 let OperandType = "OPERAND_PCREL";
56 let DecoderMethod = "DecodeBranchTarget21";
57 let ParserMatchClass = MipsJumpTargetAsmOperand;
60 def brtarget26 : Operand<OtherVT> {
61 let EncoderMethod = "getBranchTarget26OpValue";
62 let OperandType = "OPERAND_PCREL";
63 let DecoderMethod = "DecodeBranchTarget26";
64 let ParserMatchClass = MipsJumpTargetAsmOperand;
67 def jmpoffset16 : Operand<OtherVT> {
68 let EncoderMethod = "getJumpOffset16OpValue";
69 let ParserMatchClass = MipsJumpTargetAsmOperand;
72 def calloffset16 : Operand<iPTR> {
73 let EncoderMethod = "getJumpOffset16OpValue";
74 let ParserMatchClass = MipsJumpTargetAsmOperand;
77 //===----------------------------------------------------------------------===//
79 // Instruction Encodings
81 //===----------------------------------------------------------------------===//
83 class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>;
84 class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>;
85 class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
86 class AUI_ENC : AUI_FM;
87 class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;
89 class BALC_ENC : BRANCH_OFF26_FM<0b111010>;
90 class BC_ENC : BRANCH_OFF26_FM<0b110010>;
91 class BEQC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
92 DecodeDisambiguates<"AddiGroupBranch">;
93 class BEQZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_ADDI>,
94 DecodeDisambiguatedBy<"DaddiGroupBranch">;
95 class BNEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
96 DecodeDisambiguates<"DaddiGroupBranch">;
97 class BNEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_DADDI>,
98 DecodeDisambiguatedBy<"DaddiGroupBranch">;
100 class BLTZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZL>,
101 DecodeDisambiguates<"BgtzlGroupBranch">;
102 class BGEZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZL>,
103 DecodeDisambiguates<"BlezlGroupBranch">;
104 class BGTZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZ>,
105 DecodeDisambiguatedBy<"BgtzGroupBranch">;
107 class BLEZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZL>,
108 DecodeDisambiguatedBy<"BlezlGroupBranch">;
109 class BLTZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZ>,
110 DecodeDisambiguates<"BgtzGroupBranch">;
111 class BGTZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZL>,
112 DecodeDisambiguatedBy<"BgtzlGroupBranch">;
114 class BEQZC_ENC : CMP_BRANCH_OFF21_FM<0b110110>;
115 class BGEZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZ>;
116 class BNEZC_ENC : CMP_BRANCH_OFF21_FM<0b111110>;
118 class BC1EQZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1EQZ>;
119 class BC1NEZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1NEZ>;
120 class BC2EQZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2EQZ>;
121 class BC2NEZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2NEZ>;
123 class JIALC_ENC : JMP_IDX_COMPACT_FM<0b111110>;
124 class JIC_ENC : JMP_IDX_COMPACT_FM<0b110110>;
126 class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>;
127 class BLEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZ>;
128 class BNVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
129 DecodeDisambiguatedBy<"DaddiGroupBranch">;
130 class BOVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
131 DecodeDisambiguatedBy<"AddiGroupBranch">;
132 class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
133 class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
134 class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;
135 class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>;
136 class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>;
137 class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>;
138 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
139 class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>;
141 class MADDF_S_ENC : COP1_3R_FM<0b011000, FIELD_FMT_S>;
142 class MADDF_D_ENC : COP1_3R_FM<0b011000, FIELD_FMT_D>;
143 class MSUBF_S_ENC : COP1_3R_FM<0b011001, FIELD_FMT_S>;
144 class MSUBF_D_ENC : COP1_3R_FM<0b011001, FIELD_FMT_D>;
146 class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>;
147 class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>;
149 class SELEQZ_ENC : SPECIAL_3R_FM<0b00000, 0b110101>;
150 class SELNEZ_ENC : SPECIAL_3R_FM<0b00000, 0b110111>;
152 class LWPC_ENC : PCREL19_FM<OPCODE2_LWPC>;
153 class LWUPC_ENC : PCREL19_FM<OPCODE2_LWUPC>;
155 class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
156 class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
157 class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>;
158 class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>;
160 class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>;
161 class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>;
162 class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>;
163 class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>;
165 class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>;
166 class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>;
167 class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>;
168 class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>;
170 class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>;
171 class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>;
172 class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>;
173 class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>;
175 class CMP_CONDN_DESC_BASE<string CondStr, string Typestr, RegisterOperand FGROpnd> {
176 dag OutOperandList = (outs FGROpnd:$fd);
177 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
178 string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft");
179 list<dag> Pattern = [];
182 //===----------------------------------------------------------------------===//
184 // Instruction Multiclasses
186 //===----------------------------------------------------------------------===//
188 multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
189 RegisterOperand FGROpnd>{
190 def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_F>,
191 CMP_CONDN_DESC_BASE<"f", Typestr, FGROpnd>,
193 def CMP_UN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
194 CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>,
196 def CMP_EQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,
197 CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>,
199 def CMP_UEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UEQ>,
200 CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>,
202 def CMP_OLT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLT>,
203 CMP_CONDN_DESC_BASE<"olt", Typestr, FGROpnd>,
205 def CMP_ULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULT>,
206 CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>,
208 def CMP_OLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLE>,
209 CMP_CONDN_DESC_BASE<"ole", Typestr, FGROpnd>,
211 def CMP_ULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULE>,
212 CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>,
214 def CMP_SF_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SF>,
215 CMP_CONDN_DESC_BASE<"sf", Typestr, FGROpnd>,
217 def CMP_NGLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGLE>,
218 CMP_CONDN_DESC_BASE<"ngle", Typestr, FGROpnd>,
220 def CMP_SEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SEQ>,
221 CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>,
223 def CMP_NGL_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGL>,
224 CMP_CONDN_DESC_BASE<"ngl", Typestr, FGROpnd>,
226 def CMP_LT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
227 CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>,
229 def CMP_NGE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGE>,
230 CMP_CONDN_DESC_BASE<"nge", Typestr, FGROpnd>,
232 def CMP_LE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
233 CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>,
235 def CMP_NGT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGT>,
236 CMP_CONDN_DESC_BASE<"ngt", Typestr, FGROpnd>,
240 //===----------------------------------------------------------------------===//
242 // Instruction Descriptions
244 //===----------------------------------------------------------------------===//
246 class PCREL19_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
247 dag OutOperandList = (outs GPROpnd:$rs);
248 dag InOperandList = (ins simm19_lsl2:$imm);
249 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
250 list<dag> Pattern = [];
253 class ADDIUPC_DESC : PCREL19_DESC_BASE<"addiupc", GPR32Opnd>;
254 class LWPC_DESC: PCREL19_DESC_BASE<"lwpc", GPR32Opnd>;
255 class LWUPC_DESC: PCREL19_DESC_BASE<"lwupc", GPR32Opnd>;
257 class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
259 dag OutOperandList = (outs GPROpnd:$rd);
260 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
261 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
262 list<dag> Pattern = [];
265 class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2>;
267 class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
268 dag OutOperandList = (outs GPROpnd:$rs);
269 dag InOperandList = (ins simm16:$imm);
270 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
271 list<dag> Pattern = [];
274 class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>;
275 class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>;
277 class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
278 dag OutOperandList = (outs GPROpnd:$rs);
279 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
280 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
281 list<dag> Pattern = [];
284 class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
286 class BRANCH_DESC_BASE {
288 bit isTerminator = 1;
289 bit hasDelaySlot = 0;
292 class BC_DESC_BASE<string instr_asm, DAGOperand opnd> : BRANCH_DESC_BASE {
293 dag InOperandList = (ins opnd:$offset);
294 dag OutOperandList = (outs);
295 string AsmString = !strconcat(instr_asm, "\t$offset");
299 class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd,
300 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
301 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
302 dag OutOperandList = (outs);
303 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
304 list<Register> Defs = [AT];
307 class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
308 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
309 dag InOperandList = (ins GPROpnd:$rs, opnd:$offset);
310 dag OutOperandList = (outs);
311 string AsmString = !strconcat(instr_asm, "\t$rs, $offset");
312 list<Register> Defs = [AT];
315 class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
316 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
317 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
318 dag OutOperandList = (outs);
319 string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
320 list<Register> Defs = [AT];
323 class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> {
325 list<Register> Defs = [RA];
328 class BC_DESC : BC_DESC_BASE<"bc", brtarget26>;
329 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
330 class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
332 class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd>;
333 class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd>;
335 class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;
336 class BGTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR32Opnd>;
338 class BEQZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>;
339 class BNEZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>;
341 class COP1_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
342 dag InOperandList = (ins FGR64Opnd:$ft, brtarget:$offset);
343 dag OutOperandList = (outs);
344 string AsmString = instr_asm;
345 bit hasDelaySlot = 1;
348 class BC1EQZ_DESC : COP1_BCCZ_DESC_BASE<"bc1eqz $ft, $offset">;
349 class BC1NEZ_DESC : COP1_BCCZ_DESC_BASE<"bc1nez $ft, $offset">;
351 class COP2_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
352 dag InOperandList = (ins COP2Opnd:$ct, brtarget:$offset);
353 dag OutOperandList = (outs);
354 string AsmString = instr_asm;
355 bit hasDelaySlot = 1;
358 class BC2EQZ_DESC : COP2_BCCZ_DESC_BASE<"bc2eqz $ct, $offset">;
359 class BC2NEZ_DESC : COP2_BCCZ_DESC_BASE<"bc2nez $ct, $offset">;
361 class BOVC_DESC : CMP_BC_DESC_BASE<"bovc", brtarget, GPR32Opnd>;
362 class BNVC_DESC : CMP_BC_DESC_BASE<"bnvc", brtarget, GPR32Opnd>;
364 class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
365 RegisterOperand GPROpnd> {
366 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
367 string AsmString = !strconcat(opstr, "\t$rt, $offset");
368 list<dag> Pattern = [];
369 bit isTerminator = 1;
370 bit hasDelaySlot = 0;
371 string DecoderMethod = "DecodeSimm16";
374 class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
377 list<Register> Defs = [RA];
380 class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR32Opnd> {
382 list<Register> Defs = [AT];
385 class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
386 dag OutOperandList = (outs GPROpnd:$rd);
387 dag InOperandList = (ins GPROpnd:$rt);
388 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
389 list<dag> Pattern = [];
392 class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>;
394 class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
395 dag OutOperandList = (outs GPROpnd:$rd);
396 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
397 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
398 list<dag> Pattern = [];
401 class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd>;
402 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd>;
403 class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd>;
404 class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd>;
406 class BEQZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> {
407 list<Register> Defs = [RA];
410 class BGEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezalc", brtarget, GPR32Opnd> {
411 list<Register> Defs = [RA];
414 class BGTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzalc", brtarget, GPR32Opnd> {
415 list<Register> Defs = [RA];
418 class BLEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezalc", brtarget, GPR32Opnd> {
419 list<Register> Defs = [RA];
422 class BLTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzalc", brtarget, GPR32Opnd> {
423 list<Register> Defs = [RA];
426 class BNEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bnezalc", brtarget, GPR32Opnd> {
427 list<Register> Defs = [RA];
429 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
430 dag OutOperandList = (outs GPROpnd:$rd);
431 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
432 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
433 list<dag> Pattern = [];
436 class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd>;
437 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd>;
438 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd>;
439 class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
441 class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
442 dag OutOperandList = (outs FGROpnd:$fd);
443 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
444 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
445 list<dag> Pattern = [];
446 string Constraints = "$fd_in = $fd";
449 class SEL_D_DESC : COP1_4R_DESC_BASE<"sel.d", FGR64Opnd>;
450 class SEL_S_DESC : COP1_4R_DESC_BASE<"sel.s", FGR32Opnd>;
452 class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
453 dag OutOperandList = (outs GPROpnd:$rd);
454 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
455 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
456 list<dag> Pattern = [];
459 class SELEQZ_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR32Opnd>;
460 class SELNEZ_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR32Opnd>;
462 class MADDF_S_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>;
463 class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>;
464 class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>;
465 class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>;
467 class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
468 dag OutOperandList = (outs FGROpnd:$fd);
469 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
470 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
471 list<dag> Pattern = [];
474 class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>;
475 class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>;
476 class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>;
477 class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>;
479 class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>;
480 class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>;
481 class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>;
482 class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>;
484 class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
485 dag OutOperandList = (outs FGROpnd:$fd);
486 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
487 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
488 list<dag> Pattern = [];
491 class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
492 class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
493 class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
494 class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
496 class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
497 dag OutOperandList = (outs FGROpnd:$fd);
498 dag InOperandList = (ins FGROpnd:$fs);
499 string AsmString = !strconcat(instr_asm, "\t$fd, $fs");
500 list<dag> Pattern = [];
503 class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>;
504 class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>;
505 class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>;
506 class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>;
508 //===----------------------------------------------------------------------===//
510 // Instruction Definitions
512 //===----------------------------------------------------------------------===//
514 def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
515 def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
516 def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
517 def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
518 def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
519 def BALC : BALC_ENC, BALC_DESC, ISA_MIPS32R6;
520 def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6;
521 def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6;
522 def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6;
523 def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6;
524 def BC : BC_ENC, BC_DESC, ISA_MIPS32R6;
525 def BEQC : BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;
526 def BEQZALC : BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6;
527 def BEQZC : BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6;
528 def BGEC; // Also aliased to blec with operands swapped
529 def BGEUC; // Also aliased to bleuc with operands swapped
530 def BGEZALC : BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6;
531 def BGEZC : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6;
532 def BGTZALC : BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6;
533 def BGTZC : BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6;
534 def BITSWAP : BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
535 def BLEZALC : BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6;
536 def BLEZC : BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6;
537 def BLTC; // Also aliased to bgtc with operands swapped
538 def BLTUC; // Also aliased to bgtuc with operands swapped
539 def BLTZALC : BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6;
540 def BLTZC : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6;
541 def BNEC : BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;
542 def BNEZALC : BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6;
543 def BNEZC : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
544 def BNVC : BNVC_ENC, BNVC_DESC, ISA_MIPS32R6;
545 def BOVC : BOVC_ENC, BOVC_DESC, ISA_MIPS32R6;
546 def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6;
547 def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6;
548 defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;
549 defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>;
550 def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;
551 def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
552 def JIALC : JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
553 def JIC : JIC_ENC, JIC_DESC, ISA_MIPS32R6;
554 // def LSA; // See MSA
555 def LWPC : LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
556 def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
557 def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6;
558 def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6;
559 def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6;
560 def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6;
561 def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6;
562 def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6;
563 def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6;
564 def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6;
565 def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6;
566 def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6;
567 def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6;
568 def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6;
569 def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6;
570 def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6;
571 def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6;
572 def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
573 def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
574 def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6;
575 def NAL; // BAL with rd=0
576 def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6;
577 def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6;
578 def SELEQZ : SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6;
579 def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6;
580 def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6;
581 def SELNEZ : SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6;
582 def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6;
583 def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6;
584 def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6;
585 def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6;