lib/Target/Mips/Mips32r6InstrInfo.td

   1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes Mips32r6 instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 include "Mips32r6InstrFormats.td"
  15
  16 // Notes about removals/changes from MIPS32r6:
  17 // Unclear: ssnop
  18 // Reencoded: cache, pref
  19 // Reencoded: clo, clz
  20 // Reencoded: jr -> jalr
  21 // Reencoded: jr.hb -> jalr.hb
  22 // Reencoded: ldc2
  23 // Reencoded: ll, sc
  24 // Reencoded: lwc2
  25 // Reencoded: sdbbp
  26 // Reencoded: sdc2
  27 // Reencoded: swc2
  28 // Removed: /.ps$/, cvt.ps.s, cvt.ps.pw
  29 // Removed: addi
  30 // Removed: bc1any2, bc1any4
  31 // Removed: bc2[ft]
  32 // Removed: bc2f, bc2t
  33 // Removed: bc[12][ft]l, bgezl, bgtzl, bgtzl, blezl, bltzall, bltzl, bnel, bgezall,
  34 // Removed: beql
  35 // Removed: bgezal
  36 // Removed: bltzal
  37 // Removed: c.cond.fmt, bc1[ft]
  38 // Removed: div, divu
  39 // Removed: jalx
  40 // Removed: ldxc1
  41 // Removed: luxc1
  42 // Removed: lwl, lwr, lwle, lwre, swl, swr, swle, swre
  43 // Removed: lwxc1
  44 // Removed: madd.[ds], nmadd.[ds], nmsub.[ds], sub.[ds]
  45 // Removed: mfhi, mflo, mthi, mtlo, madd, maddu, msub, msubu, mul
  46 // Removed: movf, movt
  47 // Removed: movf.fmt, movt.fmt, movn.fmt, movz.fmt
  48 // Removed: movn, movz
  49 // Removed: mult, multu
  50 // Removed: prefx
  51 // Removed: sdxc1
  52 // Removed: suxc1
  53 // Removed: swxc1
  54 // Removed: teqi, tgei, tgeiu, tlti, tltiu, tnei
  55 // Rencoded: [ls][wd]c2
  56
  57 //===----------------------------------------------------------------------===//
  58 //
  59 // Instruction Encodings
  60 //
  61 //===----------------------------------------------------------------------===//
  62
  63 class MUH_ENC    : SPECIAL_3R_FM<0b00011, 0b011000>;
  64 class MUHU_ENC   : SPECIAL_3R_FM<0b00011, 0b011001>;
  65 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
  66 class MULU_ENC   : SPECIAL_3R_FM<0b00010, 0b011001>;
  67
  68 //===----------------------------------------------------------------------===//
  69 //
  70 // Instruction Descriptions
  71 //
  72 //===----------------------------------------------------------------------===//
  73
  74 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
  75   dag OutOperandList = (outs GPROpnd:$rd);
  76   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
  77   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
  78   list<dag> Pattern = [];
  79 }
  80
  81 class MUH_DESC    : MUL_R6_DESC_BASE<"muh", GPR32Opnd>;
  82 class MUHU_DESC   : MUL_R6_DESC_BASE<"muhu", GPR32Opnd>;
  83 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd>;
  84 class MULU_DESC   : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
  85
  86 //===----------------------------------------------------------------------===//
  87 //
  88 // Instruction Definitions
  89 //
  90 //===----------------------------------------------------------------------===//
  91
  92 def ADDIUPC;
  93 def ALIGN; // Known as as BALIGN in DSP ASE
  94 def ALUIPC;
  95 def AUI;
  96 def AUIPC;
  97 def BALC;
  98 def BC1EQZ;
  99 def BC1NEZ;
 100 def BC2EQZ;
 101 def BC2NEZ;
 102 def BC;
 103 def BEQC;
 104 def BEQZALC;
 105 def BEQZC;
 106 def BGEC;  // Also aliased to blec with operands swapped
 107 def BGEUC; // Also aliased to bleuc with operands swapped
 108 def BGEZALC;
 109 def BGEZC;
 110 def BGTZALC;
 111 def BGTZC;
 112 def BITSWAP; // Known as BITREV in DSP ASE
 113 def BLEZALC;
 114 def BLEZC;
 115 def BLTC; // Also aliased to bgtc with operands swapped
 116 def BLTUC; // Also aliased to bgtuc with operands swapped
 117 def BLTZALC;
 118 def BLTZC;
 119 def BNEC;
 120 def BNEZALC;
 121 def BNEZC;
 122 def BNVC;
 123 def BOVC;
 124 def CLASS_D;
 125 def CLASS_S;
 126 def CMP_CC_D;
 127 def CMP_CC_S;
 128 def DIV;   // Not to be confused with the old div
 129 def DIVU;  // Not to be confused with the old div
 130 def JIALC;
 131 def JIC;
 132 // def LSA; // See MSA
 133 def LWPC;
 134 def LWUPC;
 135 def MADDF;
 136 def MAXA_D;
 137 def MAXA_S;
 138 def MAX_D;
 139 def MAX_S;
 140 def MINA_D;
 141 def MINA_S;
 142 def MIN_D;
 143 def MOD;
 144 def MODU;
 145 def MSUBF;
 146 def MUH    : MUH_ENC, MUH_DESC, ISA_MIPS32R6;
 147 def MUHU   : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
 148 def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
 149 def MULU   : MULU_ENC, MULU_DESC, ISA_MIPS32R6;
 150 def NAL; // BAL with rd=0
 151 def RINT_D;
 152 def RINT_S;
 153 def SELEQZ;
 154 def SELEQZ_D;
 155 def SELEQZ_S;
 156 def SELNEZ;
 157 def SELNEZ_D;
 158 def SELNEZ_S;
 159 def SEL_D;
 160 def SEL_S;