1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips32r6 instructions.
12 //===----------------------------------------------------------------------===//
14 include "Mips32r6InstrFormats.td"
16 // Notes about removals/changes from MIPS32r6:
18 // Reencoded: cache, pref
19 // Reencoded: clo, clz
20 // Reencoded: jr -> jalr
21 // Reencoded: jr.hb -> jalr.hb
28 // Removed: /.ps$/, cvt.ps.s, cvt.ps.pw
30 // Removed: bc1any2, bc1any4
32 // Removed: bc2f, bc2t
35 // Removed: c.cond.fmt, bc1[ft]
40 // Removed: lwl, lwr, lwle, lwre, swl, swr, swle, swre
42 // Removed: madd.[ds], nmadd.[ds], nmsub.[ds], sub.[ds]
43 // Removed: mfhi, mflo, mthi, mtlo, madd, maddu, msub, msubu, mul
44 // Removed: movf, movt
45 // Removed: movf.fmt, movt.fmt, movn.fmt, movz.fmt
46 // Removed: movn, movz
47 // Removed: mult, multu
52 // Removed: teqi, tgei, tgeiu, tlti, tltiu, tnei
53 // Rencoded: [ls][wd]c2
55 //===----------------------------------------------------------------------===//
57 // Instruction Encodings
59 //===----------------------------------------------------------------------===//
61 class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>;
62 class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>;
63 class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
64 class AUI_ENC : AUI_FM;
65 class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;
66 class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>;
67 class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
68 class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
69 class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;
70 class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>;
71 class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>;
72 class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>;
73 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
74 class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>;
75 class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>;
76 class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>;
78 class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
79 class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
80 class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>;
81 class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>;
83 class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>;
84 class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>;
85 class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>;
86 class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>;
88 class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>;
89 class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>;
90 class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>;
91 class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>;
93 //===----------------------------------------------------------------------===//
95 // Instruction Descriptions
97 //===----------------------------------------------------------------------===//
99 class ADDIUPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
100 dag OutOperandList = (outs GPROpnd:$rs);
101 dag InOperandList = (ins simm19_lsl2:$imm);
102 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
103 list<dag> Pattern = [];
106 class ADDIUPC_DESC : ADDIUPC_DESC_BASE<"addiupc", GPR32Opnd>;
108 class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
110 dag OutOperandList = (outs GPROpnd:$rd);
111 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
112 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
113 list<dag> Pattern = [];
116 class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2>;
118 class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
119 dag OutOperandList = (outs GPROpnd:$rs);
120 dag InOperandList = (ins simm16:$imm);
121 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
122 list<dag> Pattern = [];
125 class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>;
126 class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>;
128 class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
129 dag OutOperandList = (outs GPROpnd:$rs);
130 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
131 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
132 list<dag> Pattern = [];
135 class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
137 class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
138 dag OutOperandList = (outs GPROpnd:$rd);
139 dag InOperandList = (ins GPROpnd:$rt);
140 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
141 list<dag> Pattern = [];
144 class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>;
146 class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
147 dag OutOperandList = (outs GPROpnd:$rd);
148 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
149 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
150 list<dag> Pattern = [];
153 class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd>;
154 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd>;
155 class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd>;
156 class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd>;
158 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
159 dag OutOperandList = (outs GPROpnd:$rd);
160 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
161 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
162 list<dag> Pattern = [];
165 class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd>;
166 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd>;
167 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd>;
168 class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
170 class SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
171 dag OutOperandList = (outs FGROpnd:$fd);
172 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
173 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
174 list<dag> Pattern = [];
175 string Constraints = "$fd_in = $fd";
178 class SEL_D_DESC : SEL_DESC_BASE<"sel.d", FGR64Opnd>;
179 class SEL_S_DESC : SEL_DESC_BASE<"sel.s", FGR32Opnd>;
181 class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
182 dag OutOperandList = (outs FGROpnd:$fd);
183 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
184 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
185 list<dag> Pattern = [];
188 class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>;
189 class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>;
190 class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>;
191 class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>;
193 class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>;
194 class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>;
195 class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>;
196 class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>;
198 class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
199 dag OutOperandList = (outs FGROpnd:$fd);
200 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
201 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
202 list<dag> Pattern = [];
205 class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
206 class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
207 class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
208 class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
210 //===----------------------------------------------------------------------===//
212 // Instruction Definitions
214 //===----------------------------------------------------------------------===//
216 def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
217 def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
218 def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
219 def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
220 def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
230 def BGEC; // Also aliased to blec with operands swapped
231 def BGEUC; // Also aliased to bleuc with operands swapped
236 def BITSWAP : BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
239 def BLTC; // Also aliased to bgtc with operands swapped
240 def BLTUC; // Also aliased to bgtuc with operands swapped
252 def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;
253 def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
256 // def LSA; // See MSA
260 def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6;
261 def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6;
262 def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6;
263 def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6;
264 def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6;
265 def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6;
266 def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6;
267 def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6;
268 def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6;
269 def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6;
271 def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6;
272 def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
273 def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
274 def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6;
275 def NAL; // BAL with rd=0
279 def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6;
280 def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6;
282 def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6;
283 def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6;
284 def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6;
285 def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6;