1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips32r6 instructions.
12 //===----------------------------------------------------------------------===//
14 include "Mips32r6InstrFormats.td"
16 // Notes about removals/changes from MIPS32r6:
18 // Reencoded: cache, pref
19 // Reencoded: clo, clz
20 // Reencoded: jr -> jalr
21 // Reencoded: jr.hb -> jalr.hb
28 // Removed: /.ps$/, cvt.ps.s, cvt.ps.pw
30 // Removed: bc1any2, bc1any4
32 // Removed: bc2f, bc2t
35 // Removed: c.cond.fmt, bc1[ft]
40 // Removed: lwl, lwr, lwle, lwre, swl, swr, swle, swre
42 // Removed: madd.[ds], nmadd.[ds], nmsub.[ds], sub.[ds]
43 // Removed: mfhi, mflo, mthi, mtlo, madd, maddu, msub, msubu, mul
44 // Removed: movf, movt
45 // Removed: movf.fmt, movt.fmt, movn.fmt, movz.fmt
46 // Removed: movn, movz
47 // Removed: mult, multu
52 // Removed: teqi, tgei, tgeiu, tlti, tltiu, tnei
53 // Rencoded: [ls][wd]c2
55 def brtarget21 : Operand<OtherVT> {
56 let EncoderMethod = "getBranchTarget21OpValue";
57 let OperandType = "OPERAND_PCREL";
58 let DecoderMethod = "DecodeBranchTarget21";
59 let ParserMatchClass = MipsJumpTargetAsmOperand;
62 def brtarget26 : Operand<OtherVT> {
63 let EncoderMethod = "getBranchTarget26OpValue";
64 let OperandType = "OPERAND_PCREL";
65 let DecoderMethod = "DecodeBranchTarget26";
66 let ParserMatchClass = MipsJumpTargetAsmOperand;
69 def jmpoffset16 : Operand<OtherVT> {
70 let EncoderMethod = "getJumpOffset16OpValue";
71 let ParserMatchClass = MipsJumpTargetAsmOperand;
74 def calloffset16 : Operand<iPTR> {
75 let EncoderMethod = "getJumpOffset16OpValue";
76 let ParserMatchClass = MipsJumpTargetAsmOperand;
79 //===----------------------------------------------------------------------===//
81 // Instruction Encodings
83 //===----------------------------------------------------------------------===//
85 class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>;
86 class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>;
87 class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
88 class AUI_ENC : AUI_FM;
89 class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;
91 class BALC_ENC : BRANCH_OFF26_FM<0b111010>;
92 class BC_ENC : BRANCH_OFF26_FM<0b110010>;
93 class BEQC_ENC : CMP_BRANCH_OFF16_FM<0b001000>;
94 class BEQZALC_ENC : CMP_BRANCH_RT_OFF16_FM<0b001000>;
95 class BNEC_ENC : CMP_BRANCH_OFF16_FM<0b011000>;
96 class BNEZALC_ENC : CMP_BRANCH_RT_OFF16_FM<0b011000>;
98 class BLTZC_ENC : CMP_BRANCH_OFF16_FM<0b010111>;
99 class BGEZC_ENC : CMP_BRANCH_OFF16_FM<0b010110>;
100 class BGTZALC_ENC : CMP_BRANCH_RT_OFF16_FM<0b000111>;
102 class BLEZC_ENC : CMP_BRANCH_RT_OFF16_FM<0b010110>;
103 class BLTZALC_ENC : CMP_BRANCH_OFF16_FM<0b000111>;
104 class BGTZC_ENC : CMP_BRANCH_RT_OFF16_FM<0b010111>;
106 class BEQZC_ENC : CMP_BRANCH_OFF21_FM<0b110110>;
107 class BGEZALC_ENC : CMP_BRANCH_OFF16_FM<0b000110>;
108 class BNEZC_ENC : CMP_BRANCH_OFF21_FM<0b111110>;
110 class JIALC_ENC : JMP_IDX_COMPACT_FM<0b111110>;
111 class JIC_ENC : JMP_IDX_COMPACT_FM<0b110110>;
113 class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>;
114 class BLEZALC_ENC : CMP_BRANCH_RT_OFF16_FM<0b000110>;
115 class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
116 class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
117 class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;
118 class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>;
119 class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>;
120 class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>;
121 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
122 class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>;
124 class MADDF_S_ENC : COP1_3R_FM<0b011000, FIELD_FMT_S>;
125 class MADDF_D_ENC : COP1_3R_FM<0b011000, FIELD_FMT_D>;
126 class MSUBF_S_ENC : COP1_3R_FM<0b011001, FIELD_FMT_S>;
127 class MSUBF_D_ENC : COP1_3R_FM<0b011001, FIELD_FMT_D>;
129 class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>;
130 class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>;
132 class LWPC_ENC : PCREL19_FM<OPCODE2_LWPC>;
133 class LWUPC_ENC : PCREL19_FM<OPCODE2_LWUPC>;
135 class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
136 class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
137 class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>;
138 class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>;
140 class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>;
141 class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>;
142 class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>;
143 class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>;
145 class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>;
146 class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>;
147 class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>;
148 class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>;
150 class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>;
151 class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>;
152 class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>;
153 class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>;
155 class CMP_CONDN_DESC_BASE<string CondStr, string Typestr, RegisterOperand FGROpnd> {
156 dag OutOperandList = (outs FGROpnd:$fd);
157 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
158 string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft");
159 list<dag> Pattern = [];
162 //===----------------------------------------------------------------------===//
164 // Instruction Multiclasses
166 //===----------------------------------------------------------------------===//
168 multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
169 RegisterOperand FGROpnd>{
170 def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_F>,
171 CMP_CONDN_DESC_BASE<"f", Typestr, FGROpnd>,
173 def CMP_UN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
174 CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>,
176 def CMP_EQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,
177 CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>,
179 def CMP_UEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UEQ>,
180 CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>,
182 def CMP_OLT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLT>,
183 CMP_CONDN_DESC_BASE<"olt", Typestr, FGROpnd>,
185 def CMP_ULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULT>,
186 CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>,
188 def CMP_OLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLE>,
189 CMP_CONDN_DESC_BASE<"ole", Typestr, FGROpnd>,
191 def CMP_ULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULE>,
192 CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>,
194 def CMP_SF_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SF>,
195 CMP_CONDN_DESC_BASE<"sf", Typestr, FGROpnd>,
197 def CMP_NGLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGLE>,
198 CMP_CONDN_DESC_BASE<"ngle", Typestr, FGROpnd>,
200 def CMP_SEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SEQ>,
201 CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>,
203 def CMP_NGL_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGL>,
204 CMP_CONDN_DESC_BASE<"ngl", Typestr, FGROpnd>,
206 def CMP_LT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
207 CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>,
209 def CMP_NGE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGE>,
210 CMP_CONDN_DESC_BASE<"nge", Typestr, FGROpnd>,
212 def CMP_LE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
213 CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>,
215 def CMP_NGT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGT>,
216 CMP_CONDN_DESC_BASE<"ngt", Typestr, FGROpnd>,
220 //===----------------------------------------------------------------------===//
222 // Instruction Descriptions
224 //===----------------------------------------------------------------------===//
226 class PCREL19_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
227 dag OutOperandList = (outs GPROpnd:$rs);
228 dag InOperandList = (ins simm19_lsl2:$imm);
229 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
230 list<dag> Pattern = [];
233 class ADDIUPC_DESC : PCREL19_DESC_BASE<"addiupc", GPR32Opnd>;
234 class LWPC_DESC: PCREL19_DESC_BASE<"lwpc", GPR32Opnd>;
235 class LWUPC_DESC: PCREL19_DESC_BASE<"lwupc", GPR32Opnd>;
237 class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
239 dag OutOperandList = (outs GPROpnd:$rd);
240 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
241 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
242 list<dag> Pattern = [];
245 class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2>;
247 class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
248 dag OutOperandList = (outs GPROpnd:$rs);
249 dag InOperandList = (ins simm16:$imm);
250 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
251 list<dag> Pattern = [];
254 class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>;
255 class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>;
257 class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
258 dag OutOperandList = (outs GPROpnd:$rs);
259 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
260 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
261 list<dag> Pattern = [];
264 class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
266 class BRANCH_DESC_BASE {
268 bit isTerminator = 1;
269 bit hasDelaySlot = 0;
272 class BC_DESC_BASE<string instr_asm, DAGOperand opnd> : BRANCH_DESC_BASE {
273 dag InOperandList = (ins opnd:$offset);
274 dag OutOperandList = (outs);
275 string AsmString = !strconcat(instr_asm, "\t$offset");
279 class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd,
280 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
281 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
282 dag OutOperandList = (outs);
283 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
284 list<Register> Defs = [AT];
287 class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
288 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
289 dag InOperandList = (ins GPROpnd:$rs, opnd:$offset);
290 dag OutOperandList = (outs);
291 string AsmString = !strconcat(instr_asm, "\t$rs, $offset");
292 list<Register> Defs = [AT];
295 class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
296 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
297 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
298 dag OutOperandList = (outs);
299 string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
300 list<Register> Defs = [AT];
303 class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> {
305 list<Register> Defs = [RA];
308 class BC_DESC : BC_DESC_BASE<"bc", brtarget26>;
309 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
310 class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
312 class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd> {
313 string Constraints = "$rs = $rt";
316 class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd> {
317 string Constraints = "$rs = $rt";
320 class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;
321 class BGTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR32Opnd>;
323 class BEQZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>;
324 class BNEZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>;
326 class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
327 RegisterOperand GPROpnd> {
328 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
329 string AsmString = !strconcat(opstr, "\t$rt, $offset");
330 list<dag> Pattern = [];
331 bit isTerminator = 1;
332 bit hasDelaySlot = 0;
333 string DecoderMethod = "DecodeSimm16";
336 class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
339 list<Register> Defs = [RA];
342 class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR32Opnd> {
344 list<Register> Defs = [AT];
347 class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
348 dag OutOperandList = (outs GPROpnd:$rd);
349 dag InOperandList = (ins GPROpnd:$rt);
350 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
351 list<dag> Pattern = [];
354 class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>;
356 class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
357 dag OutOperandList = (outs GPROpnd:$rd);
358 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
359 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
360 list<dag> Pattern = [];
363 class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd>;
364 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd>;
365 class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd>;
366 class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd>;
368 class BEQZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> {
369 list<Register> Defs = [RA];
372 class BGEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezalc", brtarget, GPR32Opnd> {
373 string Constraints = "$rs = $rt";
374 list<Register> Defs = [RA];
377 class BGTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzalc", brtarget, GPR32Opnd> {
378 list<Register> Defs = [RA];
381 class BLEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezalc", brtarget, GPR32Opnd> {
382 list<Register> Defs = [RA];
385 class BLTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzalc", brtarget, GPR32Opnd> {
386 string Constraints = "$rs = $rt";
387 list<Register> Defs = [RA];
390 class BNEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bnezalc", brtarget, GPR32Opnd> {
391 list<Register> Defs = [RA];
393 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
394 dag OutOperandList = (outs GPROpnd:$rd);
395 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
396 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
397 list<dag> Pattern = [];
400 class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd>;
401 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd>;
402 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd>;
403 class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
405 class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
406 dag OutOperandList = (outs FGROpnd:$fd);
407 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
408 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
409 list<dag> Pattern = [];
410 string Constraints = "$fd_in = $fd";
413 class SEL_D_DESC : COP1_4R_DESC_BASE<"sel.d", FGR64Opnd>;
414 class SEL_S_DESC : COP1_4R_DESC_BASE<"sel.s", FGR32Opnd>;
416 class MADDF_S_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>;
417 class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>;
418 class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>;
419 class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>;
421 class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
422 dag OutOperandList = (outs FGROpnd:$fd);
423 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
424 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
425 list<dag> Pattern = [];
428 class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>;
429 class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>;
430 class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>;
431 class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>;
433 class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>;
434 class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>;
435 class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>;
436 class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>;
438 class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
439 dag OutOperandList = (outs FGROpnd:$fd);
440 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
441 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
442 list<dag> Pattern = [];
445 class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
446 class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
447 class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
448 class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
450 class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
451 dag OutOperandList = (outs FGROpnd:$fd);
452 dag InOperandList = (ins FGROpnd:$fs);
453 string AsmString = !strconcat(instr_asm, "\t$fd, $fs");
454 list<dag> Pattern = [];
457 class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>;
458 class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>;
459 class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>;
460 class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>;
462 //===----------------------------------------------------------------------===//
464 // Instruction Definitions
466 //===----------------------------------------------------------------------===//
468 def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
469 def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
470 def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
471 def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
472 def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
473 def BALC : BALC_ENC, BALC_DESC, ISA_MIPS32R6;
478 def BC : BC_ENC, BC_DESC, ISA_MIPS32R6;
479 def BEQC : BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;
480 def BEQZALC : BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6;
481 def BEQZC : BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6;
482 def BGEC; // Also aliased to blec with operands swapped
483 def BGEUC; // Also aliased to bleuc with operands swapped
484 def BGEZALC : BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6;
485 def BGEZC : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6;
486 def BGTZALC : BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6;
487 def BGTZC : BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6;
488 def BITSWAP : BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
489 def BLEZALC : BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6;
490 def BLEZC : BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6;
491 def BLTC; // Also aliased to bgtc with operands swapped
492 def BLTUC; // Also aliased to bgtuc with operands swapped
493 def BLTZALC : BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6;
494 def BLTZC : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6;
495 def BNEC : BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;
496 def BNEZALC : BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6;
497 def BNEZC : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
500 def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6;
501 def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6;
502 defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;
503 defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>;
504 def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;
505 def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
506 def JIALC : JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
507 def JIC : JIC_ENC, JIC_DESC, ISA_MIPS32R6;
508 // def LSA; // See MSA
509 def LWPC : LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
510 def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
511 def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6;
512 def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6;
513 def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6;
514 def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6;
515 def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6;
516 def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6;
517 def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6;
518 def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6;
519 def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6;
520 def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6;
521 def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6;
522 def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6;
523 def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6;
524 def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6;
525 def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6;
526 def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
527 def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
528 def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6;
529 def NAL; // BAL with rd=0
530 def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6;
531 def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6;
533 def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6;
534 def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6;
536 def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6;
537 def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6;
538 def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6;
539 def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6;