1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips32r6 instructions.
12 //===----------------------------------------------------------------------===//
14 include "Mips32r6InstrFormats.td"
16 // Notes about removals/changes from MIPS32r6:
18 // Reencoded: cache, pref
19 // Reencoded: clo, clz
20 // Reencoded: jr -> jalr
21 // Reencoded: jr.hb -> jalr.hb
28 // Removed: /.ps$/, cvt.ps.s, cvt.ps.pw
30 // Removed: bc1any2, bc1any4
32 // Removed: bc2f, bc2t
35 // Removed: c.cond.fmt, bc1[ft]
40 // Removed: lwl, lwr, lwle, lwre, swl, swr, swle, swre
42 // Removed: madd.[ds], nmadd.[ds], nmsub.[ds], sub.[ds]
43 // Removed: mfhi, mflo, mthi, mtlo, madd, maddu, msub, msubu, mul
44 // Removed: movf, movt
45 // Removed: movf.fmt, movt.fmt, movn.fmt, movz.fmt
46 // Removed: movn, movz
47 // Removed: mult, multu
52 // Removed: teqi, tgei, tgeiu, tlti, tltiu, tnei
53 // Rencoded: [ls][wd]c2
55 def brtarget21 : Operand<OtherVT> {
56 let EncoderMethod = "getBranchTarget21OpValue";
57 let OperandType = "OPERAND_PCREL";
58 let DecoderMethod = "DecodeBranchTarget21";
59 let ParserMatchClass = MipsJumpTargetAsmOperand;
62 def brtarget26 : Operand<OtherVT> {
63 let EncoderMethod = "getBranchTarget26OpValue";
64 let OperandType = "OPERAND_PCREL";
65 let DecoderMethod = "DecodeBranchTarget26";
66 let ParserMatchClass = MipsJumpTargetAsmOperand;
69 //===----------------------------------------------------------------------===//
71 // Instruction Encodings
73 //===----------------------------------------------------------------------===//
75 class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>;
76 class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>;
77 class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
78 class AUI_ENC : AUI_FM;
79 class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;
81 class BALC_ENC : BRANCH_OFF26_FM<0b111010>;
82 class BC_ENC : BRANCH_OFF26_FM<0b110010>;
83 class BEQC_ENC : CMP_BRANCH_OFF16_FM<0b001000>;
84 class BNEC_ENC : CMP_BRANCH_OFF16_FM<0b011000>;
86 class BLTZC_ENC : CMP_BRANCH_OFF16_FM<0b010111>;
87 class BGEZC_ENC : CMP_BRANCH_OFF16_FM<0b010110>;
89 class BLEZC_ENC : CMP_BRANCH_RT_OFF16_FM<0b010110>;
90 class BGTZC_ENC : CMP_BRANCH_RT_OFF16_FM<0b010111>;
92 class BEQZC_ENC : CMP_BRANCH_OFF21_FM<0b110110>;
93 class BNEZC_ENC : CMP_BRANCH_OFF21_FM<0b111110>;
95 class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>;
96 class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
97 class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
98 class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;
99 class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>;
100 class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>;
101 class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>;
102 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
103 class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>;
105 class MADDF_S_ENC : COP1_3R_FM<0b011000, FIELD_FMT_S>;
106 class MADDF_D_ENC : COP1_3R_FM<0b011000, FIELD_FMT_D>;
107 class MSUBF_S_ENC : COP1_3R_FM<0b011001, FIELD_FMT_S>;
108 class MSUBF_D_ENC : COP1_3R_FM<0b011001, FIELD_FMT_D>;
110 class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>;
111 class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>;
113 class LWPC_ENC : PCREL19_FM<OPCODE2_LWPC>;
114 class LWUPC_ENC : PCREL19_FM<OPCODE2_LWUPC>;
116 class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
117 class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
118 class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>;
119 class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>;
121 class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>;
122 class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>;
123 class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>;
124 class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>;
126 class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>;
127 class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>;
128 class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>;
129 class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>;
131 class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>;
132 class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>;
133 class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>;
134 class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>;
136 class CMP_CONDN_DESC_BASE<string CondStr, string Typestr, RegisterOperand FGROpnd> {
137 dag OutOperandList = (outs FGROpnd:$fd);
138 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
139 string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft");
140 list<dag> Pattern = [];
143 //===----------------------------------------------------------------------===//
145 // Instruction Multiclasses
147 //===----------------------------------------------------------------------===//
149 multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
150 RegisterOperand FGROpnd>{
151 def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_F>,
152 CMP_CONDN_DESC_BASE<"f", Typestr, FGROpnd>,
154 def CMP_UN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
155 CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>,
157 def CMP_EQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,
158 CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>,
160 def CMP_UEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UEQ>,
161 CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>,
163 def CMP_OLT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLT>,
164 CMP_CONDN_DESC_BASE<"olt", Typestr, FGROpnd>,
166 def CMP_ULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULT>,
167 CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>,
169 def CMP_OLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLE>,
170 CMP_CONDN_DESC_BASE<"ole", Typestr, FGROpnd>,
172 def CMP_ULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULE>,
173 CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>,
175 def CMP_SF_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SF>,
176 CMP_CONDN_DESC_BASE<"sf", Typestr, FGROpnd>,
178 def CMP_NGLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGLE>,
179 CMP_CONDN_DESC_BASE<"ngle", Typestr, FGROpnd>,
181 def CMP_SEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SEQ>,
182 CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>,
184 def CMP_NGL_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGL>,
185 CMP_CONDN_DESC_BASE<"ngl", Typestr, FGROpnd>,
187 def CMP_LT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
188 CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>,
190 def CMP_NGE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGE>,
191 CMP_CONDN_DESC_BASE<"nge", Typestr, FGROpnd>,
193 def CMP_LE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
194 CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>,
196 def CMP_NGT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGT>,
197 CMP_CONDN_DESC_BASE<"ngt", Typestr, FGROpnd>,
201 //===----------------------------------------------------------------------===//
203 // Instruction Descriptions
205 //===----------------------------------------------------------------------===//
207 class PCREL19_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
208 dag OutOperandList = (outs GPROpnd:$rs);
209 dag InOperandList = (ins simm19_lsl2:$imm);
210 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
211 list<dag> Pattern = [];
214 class ADDIUPC_DESC : PCREL19_DESC_BASE<"addiupc", GPR32Opnd>;
215 class LWPC_DESC: PCREL19_DESC_BASE<"lwpc", GPR32Opnd>;
216 class LWUPC_DESC: PCREL19_DESC_BASE<"lwupc", GPR32Opnd>;
218 class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
220 dag OutOperandList = (outs GPROpnd:$rd);
221 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
222 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
223 list<dag> Pattern = [];
226 class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2>;
228 class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
229 dag OutOperandList = (outs GPROpnd:$rs);
230 dag InOperandList = (ins simm16:$imm);
231 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
232 list<dag> Pattern = [];
235 class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>;
236 class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>;
238 class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
239 dag OutOperandList = (outs GPROpnd:$rs);
240 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
241 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
242 list<dag> Pattern = [];
245 class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
247 class BRANCH_DESC_BASE {
249 bit isTerminator = 1;
250 bit hasDelaySlot = 0;
253 class BC_DESC_BASE<string instr_asm, DAGOperand opnd> : BRANCH_DESC_BASE {
254 dag InOperandList = (ins opnd:$offset);
255 dag OutOperandList = (outs);
256 string AsmString = !strconcat(instr_asm, "\t$offset");
260 class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd,
261 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
262 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
263 dag OutOperandList = (outs);
264 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
265 list<Register> Defs = [AT];
268 class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
269 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
270 dag InOperandList = (ins GPROpnd:$rs, opnd:$offset);
271 dag OutOperandList = (outs);
272 string AsmString = !strconcat(instr_asm, "\t$rs, $offset");
273 list<Register> Defs = [AT];
276 class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
277 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
278 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
279 dag OutOperandList = (outs);
280 string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
281 list<Register> Defs = [AT];
284 class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> {
286 list<Register> Defs = [RA];
289 class BC_DESC : BC_DESC_BASE<"bc", brtarget26>;
290 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
291 class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
293 class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd> {
294 string Constraints = "$rs = $rt";
297 class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd> {
298 string Constraints = "$rs = $rt";
301 class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;
302 class BGTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR32Opnd>;
304 class BEQZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>;
305 class BNEZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>;
307 class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
308 dag OutOperandList = (outs GPROpnd:$rd);
309 dag InOperandList = (ins GPROpnd:$rt);
310 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
311 list<dag> Pattern = [];
314 class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>;
316 class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
317 dag OutOperandList = (outs GPROpnd:$rd);
318 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
319 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
320 list<dag> Pattern = [];
323 class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd>;
324 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd>;
325 class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd>;
326 class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd>;
328 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
329 dag OutOperandList = (outs GPROpnd:$rd);
330 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
331 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
332 list<dag> Pattern = [];
335 class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd>;
336 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd>;
337 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd>;
338 class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
340 class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
341 dag OutOperandList = (outs FGROpnd:$fd);
342 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
343 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
344 list<dag> Pattern = [];
345 string Constraints = "$fd_in = $fd";
348 class SEL_D_DESC : COP1_4R_DESC_BASE<"sel.d", FGR64Opnd>;
349 class SEL_S_DESC : COP1_4R_DESC_BASE<"sel.s", FGR32Opnd>;
351 class MADDF_S_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>;
352 class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>;
353 class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>;
354 class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>;
356 class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
357 dag OutOperandList = (outs FGROpnd:$fd);
358 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
359 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
360 list<dag> Pattern = [];
363 class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>;
364 class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>;
365 class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>;
366 class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>;
368 class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>;
369 class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>;
370 class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>;
371 class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>;
373 class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
374 dag OutOperandList = (outs FGROpnd:$fd);
375 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
376 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
377 list<dag> Pattern = [];
380 class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
381 class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
382 class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
383 class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
385 class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
386 dag OutOperandList = (outs FGROpnd:$fd);
387 dag InOperandList = (ins FGROpnd:$fs);
388 string AsmString = !strconcat(instr_asm, "\t$fd, $fs");
389 list<dag> Pattern = [];
392 class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>;
393 class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>;
394 class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>;
395 class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>;
397 //===----------------------------------------------------------------------===//
399 // Instruction Definitions
401 //===----------------------------------------------------------------------===//
403 def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
404 def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
405 def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
406 def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
407 def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
408 def BALC : BALC_ENC, BALC_DESC, ISA_MIPS32R6;
413 def BC : BC_ENC, BC_DESC, ISA_MIPS32R6;
414 def BEQC : BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;
416 def BEQZC : BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6;
417 def BGEC; // Also aliased to blec with operands swapped
418 def BGEUC; // Also aliased to bleuc with operands swapped
420 def BGEZC : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6;
422 def BGTZC : BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6;
423 def BITSWAP : BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
425 def BLEZC : BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6;
426 def BLTC; // Also aliased to bgtc with operands swapped
427 def BLTUC; // Also aliased to bgtuc with operands swapped
429 def BLTZC : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6;
430 def BNEC : BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;
432 def BNEZC : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
435 def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6;
436 def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6;
437 defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;
438 defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>;
439 def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;
440 def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
443 // def LSA; // See MSA
444 def LWPC : LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
445 def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
446 def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6;
447 def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6;
448 def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6;
449 def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6;
450 def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6;
451 def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6;
452 def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6;
453 def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6;
454 def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6;
455 def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6;
456 def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6;
457 def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6;
458 def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6;
459 def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6;
460 def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6;
461 def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
462 def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
463 def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6;
464 def NAL; // BAL with rd=0
465 def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6;
466 def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6;
468 def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6;
469 def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6;
471 def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6;
472 def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6;
473 def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6;
474 def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6;