1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips32r6 instructions.
12 //===----------------------------------------------------------------------===//
14 include "Mips32r6InstrFormats.td"
16 // Notes about removals/changes from MIPS32r6:
17 // Reencoded: jr -> jalr
18 // Reencoded: jr.hb -> jalr.hb
21 def brtarget21 : Operand<OtherVT> {
22 let EncoderMethod = "getBranchTarget21OpValue";
23 let OperandType = "OPERAND_PCREL";
24 let DecoderMethod = "DecodeBranchTarget21";
25 let ParserMatchClass = MipsJumpTargetAsmOperand;
28 def brtarget26 : Operand<OtherVT> {
29 let EncoderMethod = "getBranchTarget26OpValue";
30 let OperandType = "OPERAND_PCREL";
31 let DecoderMethod = "DecodeBranchTarget26";
32 let ParserMatchClass = MipsJumpTargetAsmOperand;
35 def jmpoffset16 : Operand<OtherVT> {
36 let EncoderMethod = "getJumpOffset16OpValue";
37 let ParserMatchClass = MipsJumpTargetAsmOperand;
40 def calloffset16 : Operand<iPTR> {
41 let EncoderMethod = "getJumpOffset16OpValue";
42 let ParserMatchClass = MipsJumpTargetAsmOperand;
45 //===----------------------------------------------------------------------===//
47 // Instruction Encodings
49 //===----------------------------------------------------------------------===//
51 class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>;
52 class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>;
53 class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
54 class AUI_ENC : AUI_FM;
55 class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;
57 class BAL_ENC : BAL_FM;
58 class BALC_ENC : BRANCH_OFF26_FM<0b111010>;
59 class BC_ENC : BRANCH_OFF26_FM<0b110010>;
60 class BEQC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
61 DecodeDisambiguates<"AddiGroupBranch">;
62 class BEQZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_ADDI>,
63 DecodeDisambiguatedBy<"DaddiGroupBranch">;
64 class BNEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
65 DecodeDisambiguates<"DaddiGroupBranch">;
66 class BNEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_DADDI>,
67 DecodeDisambiguatedBy<"DaddiGroupBranch">;
69 class BLTZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZL>,
70 DecodeDisambiguates<"BgtzlGroupBranch">;
71 class BGEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZL>,
72 DecodeDisambiguatedBy<"BlezlGroupBranch">;
73 class BGEUC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZ>,
74 DecodeDisambiguatedBy<"BlezGroupBranch">;
75 class BGEZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZL>,
76 DecodeDisambiguates<"BlezlGroupBranch">;
77 class BGTZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZ>,
78 DecodeDisambiguatedBy<"BgtzGroupBranch">;
80 class BLTC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BGTZL>,
81 DecodeDisambiguatedBy<"BgtzlGroupBranch">;
82 class BLTUC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BGTZ>,
83 DecodeDisambiguatedBy<"BgtzGroupBranch">;
85 class BLEZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZL>,
86 DecodeDisambiguatedBy<"BlezlGroupBranch">;
87 class BLTZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZ>,
88 DecodeDisambiguates<"BgtzGroupBranch">;
89 class BGTZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZL>,
90 DecodeDisambiguatedBy<"BgtzlGroupBranch">;
92 class BEQZC_ENC : CMP_BRANCH_OFF21_FM<0b110110>;
93 class BGEZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZ>,
94 DecodeDisambiguates<"BlezGroupBranch">;
95 class BNEZC_ENC : CMP_BRANCH_OFF21_FM<0b111110>;
97 class BC1EQZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1EQZ>;
98 class BC1NEZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1NEZ>;
99 class BC2EQZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2EQZ>;
100 class BC2NEZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2NEZ>;
102 class JIALC_ENC : JMP_IDX_COMPACT_FM<0b111110>;
103 class JIC_ENC : JMP_IDX_COMPACT_FM<0b110110>;
104 class JR_HB_R6_ENC : JR_HB_R6_FM<OPCODE6_JALR>;
105 class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>;
106 class BLEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZ>,
107 DecodeDisambiguatedBy<"BlezGroupBranch">;
108 class BNVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
109 DecodeDisambiguatedBy<"DaddiGroupBranch">;
110 class BOVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
111 DecodeDisambiguatedBy<"AddiGroupBranch">;
112 class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
113 class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
114 class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;
115 class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>;
116 class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>;
117 class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>;
118 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
119 class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>;
121 class MADDF_S_ENC : COP1_3R_FM<0b011000, FIELD_FMT_S>;
122 class MADDF_D_ENC : COP1_3R_FM<0b011000, FIELD_FMT_D>;
123 class MSUBF_S_ENC : COP1_3R_FM<0b011001, FIELD_FMT_S>;
124 class MSUBF_D_ENC : COP1_3R_FM<0b011001, FIELD_FMT_D>;
126 class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>;
127 class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>;
129 class SELEQZ_ENC : SPECIAL_3R_FM<0b00000, 0b110101>;
130 class SELNEZ_ENC : SPECIAL_3R_FM<0b00000, 0b110111>;
132 class LWPC_ENC : PCREL19_FM<OPCODE2_LWPC>;
133 class LWUPC_ENC : PCREL19_FM<OPCODE2_LWUPC>;
135 class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
136 class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
137 class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>;
138 class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>;
140 class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>;
141 class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>;
142 class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>;
143 class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>;
145 class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>;
146 class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>;
147 class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>;
148 class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>;
150 class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>;
151 class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>;
152 class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>;
153 class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>;
155 class CACHE_ENC : SPECIAL3_MEM_FM<OPCODE6_CACHE>;
156 class PREF_ENC : SPECIAL3_MEM_FM<OPCODE6_PREF>;
158 class LDC2_R6_ENC : COP2LDST_FM<OPCODE5_LDC2>;
159 class LWC2_R6_ENC : COP2LDST_FM<OPCODE5_LWC2>;
160 class SDC2_R6_ENC : COP2LDST_FM<OPCODE5_SDC2>;
161 class SWC2_R6_ENC : COP2LDST_FM<OPCODE5_SWC2>;
163 class LSA_R6_ENC : SPECIAL_LSA_FM<OPCODE6_LSA>;
165 class LL_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LL>;
166 class SC_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SC>;
168 class CLO_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLO>;
169 class CLZ_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLZ>;
171 class CMP_CONDN_DESC_BASE<string CondStr, string Typestr,
172 RegisterOperand FGROpnd,
173 SDPatternOperator Op = null_frag> {
174 dag OutOperandList = (outs FGRCCOpnd:$fd);
175 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
176 string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft");
177 list<dag> Pattern = [(set FGRCCOpnd:$fd, (Op FGROpnd:$fs, FGROpnd:$ft))];
180 //===----------------------------------------------------------------------===//
182 // Instruction Multiclasses
184 //===----------------------------------------------------------------------===//
186 multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
187 RegisterOperand FGROpnd>{
188 def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_F>,
189 CMP_CONDN_DESC_BASE<"f", Typestr, FGROpnd>,
191 def CMP_UN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
192 CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, setuo>,
194 def CMP_EQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,
195 CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, setoeq>,
197 def CMP_UEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UEQ>,
198 CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, setueq>,
200 def CMP_OLT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLT>,
201 CMP_CONDN_DESC_BASE<"olt", Typestr, FGROpnd, setolt>,
203 def CMP_ULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULT>,
204 CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, setult>,
206 def CMP_OLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLE>,
207 CMP_CONDN_DESC_BASE<"ole", Typestr, FGROpnd, setole>,
209 def CMP_ULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULE>,
210 CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, setule>,
212 def CMP_SF_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SF>,
213 CMP_CONDN_DESC_BASE<"sf", Typestr, FGROpnd>,
215 def CMP_NGLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGLE>,
216 CMP_CONDN_DESC_BASE<"ngle", Typestr, FGROpnd>,
218 def CMP_SEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SEQ>,
219 CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>,
221 def CMP_NGL_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGL>,
222 CMP_CONDN_DESC_BASE<"ngl", Typestr, FGROpnd>,
224 def CMP_LT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
225 CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>,
227 def CMP_NGE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGE>,
228 CMP_CONDN_DESC_BASE<"nge", Typestr, FGROpnd>,
230 def CMP_LE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
231 CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>,
233 def CMP_NGT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGT>,
234 CMP_CONDN_DESC_BASE<"ngt", Typestr, FGROpnd>,
238 //===----------------------------------------------------------------------===//
240 // Instruction Descriptions
242 //===----------------------------------------------------------------------===//
244 class PCREL_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
246 dag OutOperandList = (outs GPROpnd:$rs);
247 dag InOperandList = (ins ImmOpnd:$imm);
248 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
249 list<dag> Pattern = [];
252 class ADDIUPC_DESC : PCREL_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
253 class LWPC_DESC: PCREL_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
254 class LWUPC_DESC: PCREL_DESC_BASE<"lwupc", GPR32Opnd, simm19_lsl2>;
256 class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
258 dag OutOperandList = (outs GPROpnd:$rd);
259 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
260 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
261 list<dag> Pattern = [];
264 class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2>;
266 class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
267 dag OutOperandList = (outs GPROpnd:$rs);
268 dag InOperandList = (ins simm16:$imm);
269 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
270 list<dag> Pattern = [];
273 class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>;
274 class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>;
276 class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
277 dag OutOperandList = (outs GPROpnd:$rs);
278 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
279 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
280 list<dag> Pattern = [];
283 class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
285 class BRANCH_DESC_BASE {
287 bit isTerminator = 1;
288 bit hasDelaySlot = 0;
291 class BC_DESC_BASE<string instr_asm, DAGOperand opnd> : BRANCH_DESC_BASE {
292 dag InOperandList = (ins opnd:$offset);
293 dag OutOperandList = (outs);
294 string AsmString = !strconcat(instr_asm, "\t$offset");
298 class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd,
299 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
300 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
301 dag OutOperandList = (outs);
302 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
303 list<Register> Defs = [AT];
306 class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
307 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
308 dag InOperandList = (ins GPROpnd:$rs, opnd:$offset);
309 dag OutOperandList = (outs);
310 string AsmString = !strconcat(instr_asm, "\t$rs, $offset");
311 list<Register> Defs = [AT];
314 class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
315 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
316 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
317 dag OutOperandList = (outs);
318 string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
319 list<Register> Defs = [AT];
322 class BAL_DESC : BC_DESC_BASE<"bal", brtarget> {
324 bit hasDelaySlot = 1;
325 list<Register> Defs = [RA];
328 class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> {
330 list<Register> Defs = [RA];
333 class BC_DESC : BC_DESC_BASE<"bc", brtarget26>;
334 class BGEC_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR32Opnd>;
335 class BGEUC_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR32Opnd>;
336 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
337 class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
339 class BLTC_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR32Opnd>;
340 class BLTUC_DESC : CMP_BC_DESC_BASE<"bltuc", brtarget, GPR32Opnd>;
342 class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd>;
343 class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd>;
345 class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;
346 class BGTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR32Opnd>;
348 class BEQZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>;
349 class BNEZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>;
351 class COP1_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
352 dag InOperandList = (ins FGR64Opnd:$ft, brtarget:$offset);
353 dag OutOperandList = (outs);
354 string AsmString = instr_asm;
355 bit hasDelaySlot = 1;
358 class BC1EQZ_DESC : COP1_BCCZ_DESC_BASE<"bc1eqz $ft, $offset">;
359 class BC1NEZ_DESC : COP1_BCCZ_DESC_BASE<"bc1nez $ft, $offset">;
361 class COP2_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
362 dag InOperandList = (ins COP2Opnd:$ct, brtarget:$offset);
363 dag OutOperandList = (outs);
364 string AsmString = instr_asm;
365 bit hasDelaySlot = 1;
368 class BC2EQZ_DESC : COP2_BCCZ_DESC_BASE<"bc2eqz $ct, $offset">;
369 class BC2NEZ_DESC : COP2_BCCZ_DESC_BASE<"bc2nez $ct, $offset">;
371 class BOVC_DESC : CMP_BC_DESC_BASE<"bovc", brtarget, GPR32Opnd>;
372 class BNVC_DESC : CMP_BC_DESC_BASE<"bnvc", brtarget, GPR32Opnd>;
374 class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
375 RegisterOperand GPROpnd> {
376 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
377 string AsmString = !strconcat(opstr, "\t$rt, $offset");
378 list<dag> Pattern = [];
379 bit isTerminator = 1;
380 bit hasDelaySlot = 0;
381 string DecoderMethod = "DecodeSimm16";
384 class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
387 list<Register> Defs = [RA];
390 class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR32Opnd> {
392 list<Register> Defs = [AT];
395 class JR_HB_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
397 bit isIndirectBranch = 1;
398 bit hasDelaySlot = 1;
403 class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
404 dag OutOperandList = (outs GPROpnd:$rd);
405 dag InOperandList = (ins GPROpnd:$rt);
406 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
407 list<dag> Pattern = [];
410 class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>;
412 class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
413 SDPatternOperator Op=null_frag> {
414 dag OutOperandList = (outs GPROpnd:$rd);
415 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
416 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
417 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
419 // This instruction doesn't trap division by zero itself. We must insert
420 // teq instructions as well.
421 bit usesCustomInserter = 1;
424 class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd, sdiv>;
425 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd, udiv>;
426 class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd, srem>;
427 class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd, urem>;
429 class BEQZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> {
430 list<Register> Defs = [RA];
433 class BGEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezalc", brtarget, GPR32Opnd> {
434 list<Register> Defs = [RA];
437 class BGTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzalc", brtarget, GPR32Opnd> {
438 list<Register> Defs = [RA];
441 class BLEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezalc", brtarget, GPR32Opnd> {
442 list<Register> Defs = [RA];
445 class BLTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzalc", brtarget, GPR32Opnd> {
446 list<Register> Defs = [RA];
449 class BNEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bnezalc", brtarget, GPR32Opnd> {
450 list<Register> Defs = [RA];
453 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
454 SDPatternOperator Op=null_frag> {
455 dag OutOperandList = (outs GPROpnd:$rd);
456 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
457 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
458 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
461 class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd, mulhs>;
462 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd, mulhu>;
463 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd, mul>;
464 class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
466 class COP1_SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
467 dag OutOperandList = (outs FGROpnd:$fd);
468 dag InOperandList = (ins FGRCCOpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
469 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
470 list<dag> Pattern = [(set FGROpnd:$fd, (select FGRCCOpnd:$fd_in,
473 string Constraints = "$fd_in = $fd";
476 class SEL_D_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd> {
477 // We must insert a SUBREG_TO_REG around $fd_in
478 bit usesCustomInserter = 1;
480 class SEL_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd>;
482 class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
483 dag OutOperandList = (outs GPROpnd:$rd);
484 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
485 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
486 list<dag> Pattern = [];
489 class SELEQZ_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR32Opnd>;
490 class SELNEZ_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR32Opnd>;
492 class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
493 dag OutOperandList = (outs FGROpnd:$fd);
494 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
495 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
496 list<dag> Pattern = [];
497 string Constraints = "$fd_in = $fd";
500 class MADDF_S_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>;
501 class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>;
502 class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>;
503 class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>;
505 class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
506 dag OutOperandList = (outs FGROpnd:$fd);
507 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
508 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
509 list<dag> Pattern = [];
512 class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>;
513 class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>;
514 class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>;
515 class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>;
517 class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>;
518 class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>;
519 class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>;
520 class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>;
522 class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
523 dag OutOperandList = (outs FGROpnd:$fd);
524 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
525 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
526 list<dag> Pattern = [];
529 class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
530 class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
531 class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
532 class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
534 class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
535 dag OutOperandList = (outs FGROpnd:$fd);
536 dag InOperandList = (ins FGROpnd:$fs);
537 string AsmString = !strconcat(instr_asm, "\t$fd, $fs");
538 list<dag> Pattern = [];
541 class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>;
542 class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>;
543 class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>;
544 class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>;
546 class CACHE_HINT_DESC<string instr_asm, Operand MemOpnd,
547 RegisterOperand GPROpnd> {
548 dag OutOperandList = (outs);
549 dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
550 string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
551 list<dag> Pattern = [];
554 class CACHE_DESC : CACHE_HINT_DESC<"cache", mem_simm9, GPR32Opnd>;
555 class PREF_DESC : CACHE_HINT_DESC<"pref", mem_simm9, GPR32Opnd>;
557 class COP2LD_DESC_BASE<string instr_asm, RegisterOperand COPOpnd> {
558 dag OutOperandList = (outs COPOpnd:$rt);
559 dag InOperandList = (ins mem_simm11:$addr);
560 string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
561 list<dag> Pattern = [];
565 class LDC2_R6_DESC : COP2LD_DESC_BASE<"ldc2", COP2Opnd>;
566 class LWC2_R6_DESC : COP2LD_DESC_BASE<"lwc2", COP2Opnd>;
568 class COP2ST_DESC_BASE<string instr_asm, RegisterOperand COPOpnd> {
569 dag OutOperandList = (outs);
570 dag InOperandList = (ins COPOpnd:$rt, mem_simm11:$addr);
571 string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
572 list<dag> Pattern = [];
576 class SDC2_R6_DESC : COP2ST_DESC_BASE<"sdc2", COP2Opnd>;
577 class SWC2_R6_DESC : COP2ST_DESC_BASE<"swc2", COP2Opnd>;
579 class LSA_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
581 dag OutOperandList = (outs GPROpnd:$rd);
582 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
583 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $imm2");
584 list<dag> Pattern = [];
587 class LSA_R6_DESC : LSA_R6_DESC_BASE<"lsa", GPR32Opnd, uimm2>;
589 class LL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
590 dag OutOperandList = (outs GPROpnd:$rt);
591 dag InOperandList = (ins mem_simm9:$addr);
592 string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
593 list<dag> Pattern = [];
597 class LL_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd>;
599 class SC_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
600 dag OutOperandList = (outs GPROpnd:$dst);
601 dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr);
602 string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
603 list<dag> Pattern = [];
605 string Constraints = "$rt = $dst";
608 class SC_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd>;
610 class CLO_CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
611 dag OutOperandList = (outs GPROpnd:$rd);
612 dag InOperandList = (ins GPROpnd:$rs);
613 string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
616 class CLO_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> :
617 CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd> {
618 list<dag> Pattern = [(set GPROpnd:$rd, (ctlz (not GPROpnd:$rs)))];
621 class CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> :
622 CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd> {
623 list<dag> Pattern = [(set GPROpnd:$rd, (ctlz GPROpnd:$rs))];
626 class CLO_R6_DESC : CLO_R6_DESC_BASE<"clo", GPR32Opnd>;
627 class CLZ_R6_DESC : CLZ_R6_DESC_BASE<"clz", GPR32Opnd>;
629 //===----------------------------------------------------------------------===//
631 // Instruction Definitions
633 //===----------------------------------------------------------------------===//
635 def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
636 def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
637 def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
638 def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
639 def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
640 def BAL : BAL_ENC, BAL_DESC, ISA_MIPS32R6;
641 def BALC : BALC_ENC, BALC_DESC, ISA_MIPS32R6;
642 def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6;
643 def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6;
644 def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6;
645 def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6;
646 def BC : BC_ENC, BC_DESC, ISA_MIPS32R6;
647 def BEQC : BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;
648 def BEQZALC : BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6;
649 def BEQZC : BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6;
650 def BGEC : BGEC_ENC, BGEC_DESC, ISA_MIPS32R6;
651 def BGEUC : BGEUC_ENC, BGEUC_DESC, ISA_MIPS32R6;
652 def BGEZALC : BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6;
653 def BGEZC : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6;
654 def BGTZALC : BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6;
655 def BGTZC : BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6;
656 def BITSWAP : BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
657 def BLEZALC : BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6;
658 def BLEZC : BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6;
659 def BLTC : BLTC_ENC, BLTC_DESC, ISA_MIPS32R6;
660 def BLTUC : BLTUC_ENC, BLTUC_DESC, ISA_MIPS32R6;
661 def BLTZALC : BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6;
662 def BLTZC : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6;
663 def BNEC : BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;
664 def BNEZALC : BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6;
665 def BNEZC : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
666 def BNVC : BNVC_ENC, BNVC_DESC, ISA_MIPS32R6;
667 def BOVC : BOVC_ENC, BOVC_DESC, ISA_MIPS32R6;
668 def CACHE_R6 : CACHE_ENC, CACHE_DESC, ISA_MIPS32R6;
669 def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6;
670 def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6;
671 def CLO_R6 : CLO_R6_ENC, CLO_R6_DESC, ISA_MIPS32R6;
672 def CLZ_R6 : CLZ_R6_ENC, CLZ_R6_DESC, ISA_MIPS32R6;
673 defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;
674 defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>;
675 def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;
676 def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
677 def JIALC : JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
678 def JIC : JIC_ENC, JIC_DESC, ISA_MIPS32R6;
679 def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6;
680 def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6;
681 def LL_R6 : LL_R6_ENC, LL_R6_DESC, ISA_MIPS32R6;
682 def LSA_R6 : LSA_R6_ENC, LSA_R6_DESC, ISA_MIPS32R6;
683 def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6;
684 def LWPC : LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
685 def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
686 def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6;
687 def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6;
688 def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6;
689 def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6;
690 def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6;
691 def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6;
692 def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6;
693 def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6;
694 def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6;
695 def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6;
696 def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6;
697 def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6;
698 def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6;
699 def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6;
700 def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6;
701 def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
702 def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
703 def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6;
704 def NAL; // BAL with rd=0
705 def PREF_R6 : PREF_ENC, PREF_DESC, ISA_MIPS32R6;
706 def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6;
707 def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6;
708 def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6;
709 def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;
710 def SELEQZ : SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32;
711 def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6;
712 def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6;
713 def SELNEZ : SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32;
714 def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6;
715 def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6;
716 def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6;
717 def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6;
718 def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6;
720 //===----------------------------------------------------------------------===//
722 // Patterns and Pseudo Instructions
724 //===----------------------------------------------------------------------===//
726 // f32 comparisons supported via another comparison
727 def : MipsPat<(setone f32:$lhs, f32:$rhs),
728 (NOR (CMP_UEQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
729 def : MipsPat<(seto f32:$lhs, f32:$rhs),
730 (NOR (CMP_UN_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
731 def : MipsPat<(setune f32:$lhs, f32:$rhs),
732 (NOR (CMP_EQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
733 def : MipsPat<(seteq f32:$lhs, f32:$rhs), (CMP_EQ_S f32:$lhs, f32:$rhs)>,
735 def : MipsPat<(setgt f32:$lhs, f32:$rhs), (CMP_LE_S f32:$rhs, f32:$lhs)>,
737 def : MipsPat<(setge f32:$lhs, f32:$rhs), (CMP_LT_S f32:$rhs, f32:$lhs)>,
739 def : MipsPat<(setlt f32:$lhs, f32:$rhs), (CMP_OLT_S f32:$lhs, f32:$rhs)>,
741 def : MipsPat<(setlt f32:$lhs, f32:$rhs), (CMP_OLE_S f32:$lhs, f32:$rhs)>,
743 def : MipsPat<(setne f32:$lhs, f32:$rhs),
744 (NOR (CMP_EQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
746 // f64 comparisons supported via another comparison
747 def : MipsPat<(setone f64:$lhs, f64:$rhs),
748 (NOR (CMP_UEQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
749 def : MipsPat<(seto f64:$lhs, f64:$rhs),
750 (NOR (CMP_UN_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
751 def : MipsPat<(setune f64:$lhs, f64:$rhs),
752 (NOR (CMP_EQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
753 def : MipsPat<(seteq f64:$lhs, f64:$rhs), (CMP_EQ_D f64:$lhs, f64:$rhs)>,
755 def : MipsPat<(setgt f64:$lhs, f64:$rhs), (CMP_LE_D f64:$rhs, f64:$lhs)>,
757 def : MipsPat<(setge f64:$lhs, f64:$rhs), (CMP_LT_D f64:$rhs, f64:$lhs)>,
759 def : MipsPat<(setlt f64:$lhs, f64:$rhs), (CMP_OLT_D f64:$lhs, f64:$rhs)>,
761 def : MipsPat<(setlt f64:$lhs, f64:$rhs), (CMP_OLE_D f64:$lhs, f64:$rhs)>,
763 def : MipsPat<(setne f64:$lhs, f64:$rhs),
764 (NOR (CMP_EQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
767 def : MipsPat<(select i32:$cond, i32:$t, i32:$f),
768 (OR (SELNEZ i32:$t, i32:$cond), (SELEQZ i32:$f, i32:$cond))>,
770 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i32:$t, i32:$f),
771 (OR (SELNEZ i32:$t, i32:$cond), (SELEQZ i32:$f, i32:$cond))>,
773 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i32:$t, i32:$f),
774 (OR (SELNEZ i32:$f, i32:$cond), (SELEQZ i32:$t, i32:$cond))>,
776 def : MipsPat<(select (i32 (seteq i32:$cond, immZExt16:$imm)), i32:$t, i32:$f),
777 (OR (SELNEZ i32:$t, (XORi i32:$cond, immZExt16:$imm)),
778 (SELEQZ i32:$f, (XORi i32:$cond, immZExt16:$imm)))>,
780 def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i32:$t, i32:$f),
781 (OR (SELNEZ i32:$f, (XORi i32:$cond, immZExt16:$imm)),
782 (SELEQZ i32:$t, (XORi i32:$cond, immZExt16:$imm)))>,
784 def : MipsPat<(select (i32 (setgt i32:$cond, immSExt16Plus1:$imm)), i32:$t,
786 (OR (SELNEZ i32:$t, (SLTi i32:$cond, (Plus1 imm:$imm))),
787 (SELEQZ i32:$f, (SLTi i32:$cond, (Plus1 imm:$imm))))>,
789 def : MipsPat<(select (i32 (setugt i32:$cond, immSExt16Plus1:$imm)),
791 (OR (SELNEZ i32:$t, (SLTiu i32:$cond, (Plus1 imm:$imm))),
792 (SELEQZ i32:$f, (SLTiu i32:$cond, (Plus1 imm:$imm))))>,
795 def : MipsPat<(select i32:$cond, i32:$t, immz),
796 (SELNEZ i32:$t, i32:$cond)>, ISA_MIPS32R6;
797 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i32:$t, immz),
798 (SELNEZ i32:$t, i32:$cond)>, ISA_MIPS32R6;
799 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i32:$t, immz),
800 (SELEQZ i32:$t, i32:$cond)>, ISA_MIPS32R6;
801 def : MipsPat<(select i32:$cond, immz, i32:$f),
802 (SELEQZ i32:$f, i32:$cond)>, ISA_MIPS32R6;
803 def : MipsPat<(select (i32 (setne i32:$cond, immz)), immz, i32:$f),
804 (SELEQZ i32:$f, i32:$cond)>, ISA_MIPS32R6;
805 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), immz, i32:$f),
806 (SELNEZ i32:$f, i32:$cond)>, ISA_MIPS32R6;