1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips32r6 instructions.
12 //===----------------------------------------------------------------------===//
14 include "Mips32r6InstrFormats.td"
16 // Notes about removals/changes from MIPS32r6:
18 // Reencoded: cache, pref
19 // Reencoded: clo, clz
20 // Reencoded: jr -> jalr
21 // Reencoded: jr.hb -> jalr.hb
28 // Removed: /.ps$/, cvt.ps.s, cvt.ps.pw
30 // Removed: bc1any2, bc1any4
32 // Removed: bc2f, bc2t
35 // Removed: c.cond.fmt, bc1[ft]
40 // Removed: lwl, lwr, lwle, lwre, swl, swr, swle, swre
42 // Removed: madd.[ds], nmadd.[ds], nmsub.[ds], sub.[ds]
43 // Removed: mfhi, mflo, mthi, mtlo, madd, maddu, msub, msubu, mul
44 // Removed: movf, movt
45 // Removed: movf.fmt, movt.fmt, movn.fmt, movz.fmt
46 // Removed: movn, movz
47 // Removed: mult, multu
52 // Removed: teqi, tgei, tgeiu, tlti, tltiu, tnei
53 // Rencoded: [ls][wd]c2
55 //===----------------------------------------------------------------------===//
57 // Instruction Encodings
59 //===----------------------------------------------------------------------===//
61 class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>;
62 class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>;
63 class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
64 class AUI_ENC : AUI_FM;
65 class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;
66 class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
67 class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
68 class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;
69 class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>;
70 class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>;
71 class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>;
72 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
73 class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>;
74 class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>;
75 class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>;
77 //===----------------------------------------------------------------------===//
79 // Instruction Descriptions
81 //===----------------------------------------------------------------------===//
83 class ADDIUPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
84 dag OutOperandList = (outs GPROpnd:$rs);
85 dag InOperandList = (ins simm19_lsl2:$imm);
86 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
87 list<dag> Pattern = [];
90 class ADDIUPC_DESC : ADDIUPC_DESC_BASE<"addiupc", GPR32Opnd>;
92 class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
94 dag OutOperandList = (outs GPROpnd:$rd);
95 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
96 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
97 list<dag> Pattern = [];
100 class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2>;
102 class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
103 dag OutOperandList = (outs GPROpnd:$rs);
104 dag InOperandList = (ins simm16:$imm);
105 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
106 list<dag> Pattern = [];
109 class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>;
110 class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>;
112 class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
113 dag OutOperandList = (outs GPROpnd:$rs);
114 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
115 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
116 list<dag> Pattern = [];
119 class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
121 class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
122 dag OutOperandList = (outs GPROpnd:$rd);
123 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
124 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
125 list<dag> Pattern = [];
128 class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd>;
129 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd>;
130 class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd>;
131 class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd>;
133 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
134 dag OutOperandList = (outs GPROpnd:$rd);
135 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
136 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
137 list<dag> Pattern = [];
140 class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd>;
141 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd>;
142 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd>;
143 class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
145 class SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
146 dag OutOperandList = (outs FGROpnd:$fd);
147 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
148 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
149 list<dag> Pattern = [];
150 string Constraints = "$fd_in = $fd";
153 class SEL_D_DESC : SEL_DESC_BASE<"sel.d", FGR64Opnd>;
154 class SEL_S_DESC : SEL_DESC_BASE<"sel.s", FGR32Opnd>;
156 //===----------------------------------------------------------------------===//
158 // Instruction Definitions
160 //===----------------------------------------------------------------------===//
162 def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
163 def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
164 def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
165 def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
166 def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
176 def BGEC; // Also aliased to blec with operands swapped
177 def BGEUC; // Also aliased to bleuc with operands swapped
182 def BITSWAP; // Known as BITREV in DSP ASE
185 def BLTC; // Also aliased to bgtc with operands swapped
186 def BLTUC; // Also aliased to bgtuc with operands swapped
198 def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;
199 def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
202 // def LSA; // See MSA
213 def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6;
214 def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6;
216 def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6;
217 def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
218 def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
219 def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6;
220 def NAL; // BAL with rd=0
229 def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6;
230 def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6;