1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips32r6 instructions.
12 //===----------------------------------------------------------------------===//
14 include "Mips32r6InstrFormats.td"
16 // Notes about removals/changes from MIPS32r6:
18 // Reencoded: cache, pref
19 // Reencoded: clo, clz
20 // Reencoded: jr -> jalr
21 // Reencoded: jr.hb -> jalr.hb
28 // Removed: /.ps$/, cvt.ps.s, cvt.ps.pw
30 // Removed: bc1any2, bc1any4
32 // Removed: bc2f, bc2t
35 // Removed: c.cond.fmt, bc1[ft]
40 // Removed: lwl, lwr, lwle, lwre, swl, swr, swle, swre
42 // Removed: madd.[ds], nmadd.[ds], nmsub.[ds], sub.[ds]
43 // Removed: mfhi, mflo, mthi, mtlo, madd, maddu, msub, msubu, mul
44 // Removed: movf, movt
45 // Removed: movf.fmt, movt.fmt, movn.fmt, movz.fmt
46 // Removed: movn, movz
47 // Removed: mult, multu
52 // Removed: teqi, tgei, tgeiu, tlti, tltiu, tnei
53 // Rencoded: [ls][wd]c2
55 def brtarget21 : Operand<OtherVT> {
56 let EncoderMethod = "getBranchTarget21OpValue";
57 let OperandType = "OPERAND_PCREL";
58 let DecoderMethod = "DecodeBranchTarget21";
59 let ParserMatchClass = MipsJumpTargetAsmOperand;
62 def brtarget26 : Operand<OtherVT> {
63 let EncoderMethod = "getBranchTarget26OpValue";
64 let OperandType = "OPERAND_PCREL";
65 let DecoderMethod = "DecodeBranchTarget26";
66 let ParserMatchClass = MipsJumpTargetAsmOperand;
69 def jmpoffset16 : Operand<OtherVT> {
70 let EncoderMethod = "getJumpOffset16OpValue";
71 let ParserMatchClass = MipsJumpTargetAsmOperand;
74 def calloffset16 : Operand<iPTR> {
75 let EncoderMethod = "getJumpOffset16OpValue";
76 let ParserMatchClass = MipsJumpTargetAsmOperand;
79 //===----------------------------------------------------------------------===//
81 // Instruction Encodings
83 //===----------------------------------------------------------------------===//
85 class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>;
86 class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>;
87 class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
88 class AUI_ENC : AUI_FM;
89 class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;
91 class BALC_ENC : BRANCH_OFF26_FM<0b111010>;
92 class BC_ENC : BRANCH_OFF26_FM<0b110010>;
93 class BEQC_ENC : CMP_BRANCH_OFF16_FM<0b001000>;
94 class BEQZALC_ENC : CMP_BRANCH_RT_OFF16_FM<0b001000>;
95 class BNEC_ENC : CMP_BRANCH_OFF16_FM<0b011000>;
96 class BNEZALC_ENC : CMP_BRANCH_RT_OFF16_FM<0b011000>;
98 class BLTZC_ENC : CMP_BRANCH_OFF16_FM<0b010111>;
99 class BGEZC_ENC : CMP_BRANCH_OFF16_FM<0b010110>;
100 class BGTZALC_ENC : CMP_BRANCH_RT_OFF16_FM<0b000111>;
102 class BLEZC_ENC : CMP_BRANCH_RT_OFF16_FM<0b010110>;
103 class BLTZALC_ENC : CMP_BRANCH_OFF16_FM<0b000111>;
104 class BGTZC_ENC : CMP_BRANCH_RT_OFF16_FM<0b010111>;
106 class BEQZC_ENC : CMP_BRANCH_OFF21_FM<0b110110>;
107 class BGEZALC_ENC : CMP_BRANCH_OFF16_FM<0b000110>;
108 class BNEZC_ENC : CMP_BRANCH_OFF21_FM<0b111110>;
110 class BC1EQZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1EQZ>;
111 class BC1NEZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1NEZ>;
112 class BC2EQZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2EQZ>;
113 class BC2NEZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2NEZ>;
115 class JIALC_ENC : JMP_IDX_COMPACT_FM<0b111110>;
116 class JIC_ENC : JMP_IDX_COMPACT_FM<0b110110>;
118 class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>;
119 class BLEZALC_ENC : CMP_BRANCH_RT_OFF16_FM<0b000110>;
120 class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
121 class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
122 class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;
123 class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>;
124 class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>;
125 class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>;
126 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
127 class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>;
129 class MADDF_S_ENC : COP1_3R_FM<0b011000, FIELD_FMT_S>;
130 class MADDF_D_ENC : COP1_3R_FM<0b011000, FIELD_FMT_D>;
131 class MSUBF_S_ENC : COP1_3R_FM<0b011001, FIELD_FMT_S>;
132 class MSUBF_D_ENC : COP1_3R_FM<0b011001, FIELD_FMT_D>;
134 class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>;
135 class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>;
137 class SELEQZ_ENC : SPECIAL_3R_FM<0b00000, 0b110101>;
138 class SELNEZ_ENC : SPECIAL_3R_FM<0b00000, 0b110111>;
140 class LWPC_ENC : PCREL19_FM<OPCODE2_LWPC>;
141 class LWUPC_ENC : PCREL19_FM<OPCODE2_LWUPC>;
143 class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
144 class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
145 class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>;
146 class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>;
148 class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>;
149 class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>;
150 class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>;
151 class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>;
153 class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>;
154 class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>;
155 class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>;
156 class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>;
158 class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>;
159 class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>;
160 class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>;
161 class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>;
163 class CMP_CONDN_DESC_BASE<string CondStr, string Typestr, RegisterOperand FGROpnd> {
164 dag OutOperandList = (outs FGROpnd:$fd);
165 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
166 string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft");
167 list<dag> Pattern = [];
170 //===----------------------------------------------------------------------===//
172 // Instruction Multiclasses
174 //===----------------------------------------------------------------------===//
176 multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
177 RegisterOperand FGROpnd>{
178 def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_F>,
179 CMP_CONDN_DESC_BASE<"f", Typestr, FGROpnd>,
181 def CMP_UN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
182 CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>,
184 def CMP_EQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,
185 CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>,
187 def CMP_UEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UEQ>,
188 CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>,
190 def CMP_OLT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLT>,
191 CMP_CONDN_DESC_BASE<"olt", Typestr, FGROpnd>,
193 def CMP_ULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULT>,
194 CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>,
196 def CMP_OLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLE>,
197 CMP_CONDN_DESC_BASE<"ole", Typestr, FGROpnd>,
199 def CMP_ULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULE>,
200 CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>,
202 def CMP_SF_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SF>,
203 CMP_CONDN_DESC_BASE<"sf", Typestr, FGROpnd>,
205 def CMP_NGLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGLE>,
206 CMP_CONDN_DESC_BASE<"ngle", Typestr, FGROpnd>,
208 def CMP_SEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SEQ>,
209 CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>,
211 def CMP_NGL_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGL>,
212 CMP_CONDN_DESC_BASE<"ngl", Typestr, FGROpnd>,
214 def CMP_LT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
215 CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>,
217 def CMP_NGE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGE>,
218 CMP_CONDN_DESC_BASE<"nge", Typestr, FGROpnd>,
220 def CMP_LE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
221 CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>,
223 def CMP_NGT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGT>,
224 CMP_CONDN_DESC_BASE<"ngt", Typestr, FGROpnd>,
228 //===----------------------------------------------------------------------===//
230 // Instruction Descriptions
232 //===----------------------------------------------------------------------===//
234 class PCREL19_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
235 dag OutOperandList = (outs GPROpnd:$rs);
236 dag InOperandList = (ins simm19_lsl2:$imm);
237 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
238 list<dag> Pattern = [];
241 class ADDIUPC_DESC : PCREL19_DESC_BASE<"addiupc", GPR32Opnd>;
242 class LWPC_DESC: PCREL19_DESC_BASE<"lwpc", GPR32Opnd>;
243 class LWUPC_DESC: PCREL19_DESC_BASE<"lwupc", GPR32Opnd>;
245 class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
247 dag OutOperandList = (outs GPROpnd:$rd);
248 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
249 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
250 list<dag> Pattern = [];
253 class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2>;
255 class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
256 dag OutOperandList = (outs GPROpnd:$rs);
257 dag InOperandList = (ins simm16:$imm);
258 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
259 list<dag> Pattern = [];
262 class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>;
263 class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>;
265 class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
266 dag OutOperandList = (outs GPROpnd:$rs);
267 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
268 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
269 list<dag> Pattern = [];
272 class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
274 class BRANCH_DESC_BASE {
276 bit isTerminator = 1;
277 bit hasDelaySlot = 0;
280 class BC_DESC_BASE<string instr_asm, DAGOperand opnd> : BRANCH_DESC_BASE {
281 dag InOperandList = (ins opnd:$offset);
282 dag OutOperandList = (outs);
283 string AsmString = !strconcat(instr_asm, "\t$offset");
287 class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd,
288 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
289 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
290 dag OutOperandList = (outs);
291 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
292 list<Register> Defs = [AT];
295 class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
296 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
297 dag InOperandList = (ins GPROpnd:$rs, opnd:$offset);
298 dag OutOperandList = (outs);
299 string AsmString = !strconcat(instr_asm, "\t$rs, $offset");
300 list<Register> Defs = [AT];
303 class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
304 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
305 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
306 dag OutOperandList = (outs);
307 string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
308 list<Register> Defs = [AT];
311 class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> {
313 list<Register> Defs = [RA];
316 class BC_DESC : BC_DESC_BASE<"bc", brtarget26>;
317 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
318 class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
320 class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd> {
321 string Constraints = "$rs = $rt";
324 class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd> {
325 string Constraints = "$rs = $rt";
328 class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;
329 class BGTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR32Opnd>;
331 class BEQZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>;
332 class BNEZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>;
334 class COP1_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
335 dag InOperandList = (ins FGR64Opnd:$ft, brtarget:$offset);
336 dag OutOperandList = (outs);
337 string AsmString = instr_asm;
338 bit hasDelaySlot = 1;
341 class BC1EQZ_DESC : COP1_BCCZ_DESC_BASE<"bc1eqz $ft, $offset">;
342 class BC1NEZ_DESC : COP1_BCCZ_DESC_BASE<"bc1nez $ft, $offset">;
344 class COP2_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
345 dag InOperandList = (ins COP2Opnd:$ct, brtarget:$offset);
346 dag OutOperandList = (outs);
347 string AsmString = instr_asm;
348 bit hasDelaySlot = 1;
351 class BC2EQZ_DESC : COP2_BCCZ_DESC_BASE<"bc2eqz $ct, $offset">;
352 class BC2NEZ_DESC : COP2_BCCZ_DESC_BASE<"bc2nez $ct, $offset">;
354 class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
355 RegisterOperand GPROpnd> {
356 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
357 string AsmString = !strconcat(opstr, "\t$rt, $offset");
358 list<dag> Pattern = [];
359 bit isTerminator = 1;
360 bit hasDelaySlot = 0;
361 string DecoderMethod = "DecodeSimm16";
364 class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
367 list<Register> Defs = [RA];
370 class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR32Opnd> {
372 list<Register> Defs = [AT];
375 class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
376 dag OutOperandList = (outs GPROpnd:$rd);
377 dag InOperandList = (ins GPROpnd:$rt);
378 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
379 list<dag> Pattern = [];
382 class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>;
384 class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
385 dag OutOperandList = (outs GPROpnd:$rd);
386 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
387 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
388 list<dag> Pattern = [];
391 class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd>;
392 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd>;
393 class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd>;
394 class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd>;
396 class BEQZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> {
397 list<Register> Defs = [RA];
400 class BGEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezalc", brtarget, GPR32Opnd> {
401 string Constraints = "$rs = $rt";
402 list<Register> Defs = [RA];
405 class BGTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzalc", brtarget, GPR32Opnd> {
406 list<Register> Defs = [RA];
409 class BLEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezalc", brtarget, GPR32Opnd> {
410 list<Register> Defs = [RA];
413 class BLTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzalc", brtarget, GPR32Opnd> {
414 string Constraints = "$rs = $rt";
415 list<Register> Defs = [RA];
418 class BNEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bnezalc", brtarget, GPR32Opnd> {
419 list<Register> Defs = [RA];
421 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
422 dag OutOperandList = (outs GPROpnd:$rd);
423 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
424 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
425 list<dag> Pattern = [];
428 class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd>;
429 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd>;
430 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd>;
431 class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
433 class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
434 dag OutOperandList = (outs FGROpnd:$fd);
435 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
436 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
437 list<dag> Pattern = [];
438 string Constraints = "$fd_in = $fd";
441 class SEL_D_DESC : COP1_4R_DESC_BASE<"sel.d", FGR64Opnd>;
442 class SEL_S_DESC : COP1_4R_DESC_BASE<"sel.s", FGR32Opnd>;
444 class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
445 dag OutOperandList = (outs GPROpnd:$rd);
446 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
447 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
448 list<dag> Pattern = [];
451 class SELEQZ_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR32Opnd>;
452 class SELNEZ_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR32Opnd>;
454 class MADDF_S_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>;
455 class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>;
456 class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>;
457 class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>;
459 class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
460 dag OutOperandList = (outs FGROpnd:$fd);
461 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
462 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
463 list<dag> Pattern = [];
466 class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>;
467 class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>;
468 class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>;
469 class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>;
471 class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>;
472 class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>;
473 class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>;
474 class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>;
476 class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
477 dag OutOperandList = (outs FGROpnd:$fd);
478 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
479 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
480 list<dag> Pattern = [];
483 class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
484 class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
485 class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
486 class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
488 class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
489 dag OutOperandList = (outs FGROpnd:$fd);
490 dag InOperandList = (ins FGROpnd:$fs);
491 string AsmString = !strconcat(instr_asm, "\t$fd, $fs");
492 list<dag> Pattern = [];
495 class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>;
496 class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>;
497 class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>;
498 class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>;
500 //===----------------------------------------------------------------------===//
502 // Instruction Definitions
504 //===----------------------------------------------------------------------===//
506 def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
507 def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
508 def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
509 def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
510 def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
511 def BALC : BALC_ENC, BALC_DESC, ISA_MIPS32R6;
512 def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6;
513 def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6;
514 def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6;
515 def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6;
516 def BC : BC_ENC, BC_DESC, ISA_MIPS32R6;
517 def BEQC : BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;
518 def BEQZALC : BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6;
519 def BEQZC : BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6;
520 def BGEC; // Also aliased to blec with operands swapped
521 def BGEUC; // Also aliased to bleuc with operands swapped
522 def BGEZALC : BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6;
523 def BGEZC : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6;
524 def BGTZALC : BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6;
525 def BGTZC : BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6;
526 def BITSWAP : BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
527 def BLEZALC : BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6;
528 def BLEZC : BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6;
529 def BLTC; // Also aliased to bgtc with operands swapped
530 def BLTUC; // Also aliased to bgtuc with operands swapped
531 def BLTZALC : BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6;
532 def BLTZC : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6;
533 def BNEC : BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;
534 def BNEZALC : BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6;
535 def BNEZC : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
538 def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6;
539 def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6;
540 defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;
541 defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>;
542 def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;
543 def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
544 def JIALC : JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
545 def JIC : JIC_ENC, JIC_DESC, ISA_MIPS32R6;
546 // def LSA; // See MSA
547 def LWPC : LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
548 def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
549 def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6;
550 def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6;
551 def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6;
552 def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6;
553 def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6;
554 def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6;
555 def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6;
556 def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6;
557 def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6;
558 def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6;
559 def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6;
560 def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6;
561 def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6;
562 def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6;
563 def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6;
564 def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
565 def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
566 def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6;
567 def NAL; // BAL with rd=0
568 def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6;
569 def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6;
570 def SELEQZ : SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6;
571 def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6;
572 def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6;
573 def SELNEZ : SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6;
574 def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6;
575 def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6;
576 def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6;
577 def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6;