1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips32r6 instructions.
12 //===----------------------------------------------------------------------===//
14 include "Mips32r6InstrFormats.td"
16 // Notes about removals/changes from MIPS32r6:
18 // Reencoded: cache, pref
19 // Reencoded: clo, clz
20 // Reencoded: jr -> jalr
21 // Reencoded: jr.hb -> jalr.hb
28 // Removed: /.ps$/, cvt.ps.s, cvt.ps.pw
30 // Removed: bc1any2, bc1any4
32 // Removed: bc2f, bc2t
35 // Removed: c.cond.fmt, bc1[ft]
40 // Removed: lwl, lwr, lwle, lwre, swl, swr, swle, swre
42 // Removed: madd.[ds], nmadd.[ds], nmsub.[ds], sub.[ds]
43 // Removed: mfhi, mflo, mthi, mtlo, madd, maddu, msub, msubu, mul
44 // Removed: movf, movt
45 // Removed: movf.fmt, movt.fmt, movn.fmt, movz.fmt
46 // Removed: movn, movz
47 // Removed: mult, multu
52 // Removed: teqi, tgei, tgeiu, tlti, tltiu, tnei
53 // Rencoded: [ls][wd]c2
55 def brtarget21 : Operand<OtherVT> {
56 let EncoderMethod = "getBranchTarget21OpValue";
57 let OperandType = "OPERAND_PCREL";
58 let DecoderMethod = "DecodeBranchTarget21";
59 let ParserMatchClass = MipsJumpTargetAsmOperand;
62 def brtarget26 : Operand<OtherVT> {
63 let EncoderMethod = "getBranchTarget26OpValue";
64 let OperandType = "OPERAND_PCREL";
65 let DecoderMethod = "DecodeBranchTarget26";
66 let ParserMatchClass = MipsJumpTargetAsmOperand;
69 def jmpoffset16 : Operand<OtherVT> {
70 let EncoderMethod = "getJumpOffset16OpValue";
71 let ParserMatchClass = MipsJumpTargetAsmOperand;
74 def calloffset16 : Operand<iPTR> {
75 let EncoderMethod = "getJumpOffset16OpValue";
76 let ParserMatchClass = MipsJumpTargetAsmOperand;
79 //===----------------------------------------------------------------------===//
81 // Instruction Encodings
83 //===----------------------------------------------------------------------===//
85 class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>;
86 class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>;
87 class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
88 class AUI_ENC : AUI_FM;
89 class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;
91 class BALC_ENC : BRANCH_OFF26_FM<0b111010>;
92 class BC_ENC : BRANCH_OFF26_FM<0b110010>;
93 class BEQC_ENC : CMP_BRANCH_OFF16_FM<0b001000>;
94 class BEQZALC_ENC : CMP_BRANCH_RT_OFF16_FM<0b001000>;
95 class BNEC_ENC : CMP_BRANCH_OFF16_FM<0b011000>;
96 class BNEZALC_ENC : CMP_BRANCH_RT_OFF16_FM<0b011000>;
98 class BLTZC_ENC : CMP_BRANCH_OFF16_FM<0b010111>;
99 class BGEZC_ENC : CMP_BRANCH_OFF16_FM<0b010110>;
100 class BGTZALC_ENC : CMP_BRANCH_RT_OFF16_FM<0b000111>;
102 class BLEZC_ENC : CMP_BRANCH_RT_OFF16_FM<0b010110>;
103 class BLTZALC_ENC : CMP_BRANCH_OFF16_FM<0b000111>;
104 class BGTZC_ENC : CMP_BRANCH_RT_OFF16_FM<0b010111>;
106 class BEQZC_ENC : CMP_BRANCH_OFF21_FM<0b110110>;
107 class BGEZALC_ENC : CMP_BRANCH_OFF16_FM<0b000110>;
108 class BNEZC_ENC : CMP_BRANCH_OFF21_FM<0b111110>;
110 class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>;
111 class BLEZALC_ENC : CMP_BRANCH_RT_OFF16_FM<0b000110>;
113 class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>;
114 class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>;
116 class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
117 class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
119 class JIALC_ENC : JMP_IDX_COMPACT_FM<0b111110>;
120 class JIC_ENC : JMP_IDX_COMPACT_FM<0b110110>;
122 class LWPC_ENC : PCREL19_FM<OPCODE2_LWPC>;
123 class LWUPC_ENC : PCREL19_FM<OPCODE2_LWUPC>;
125 class MADDF_S_ENC : COP1_3R_FM<0b011000, FIELD_FMT_S>;
126 class MADDF_D_ENC : COP1_3R_FM<0b011000, FIELD_FMT_D>;
127 class MSUBF_S_ENC : COP1_3R_FM<0b011001, FIELD_FMT_S>;
128 class MSUBF_D_ENC : COP1_3R_FM<0b011001, FIELD_FMT_D>;
130 class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
131 class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
132 class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>;
133 class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>;
135 class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>;
136 class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>;
137 class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>;
138 class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>;
140 class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;
141 class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>;
142 class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>;
143 class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>;
144 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
145 class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>;
147 class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>;
148 class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>;
150 class SELEQZ_ENC : SPECIAL_3R_FM<0b00000, 0b110101>;
151 class SELNEZ_ENC : SPECIAL_3R_FM<0b00000, 0b110111>;
153 class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>;
154 class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>;
155 class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>;
156 class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>;
158 class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>;
159 class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>;
161 class CMP_CONDN_DESC_BASE<string CondStr, string Typestr,
162 RegisterOperand FGROpnd> {
163 dag OutOperandList = (outs FGROpnd:$fd);
164 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
165 string AsmString = !strconcat("cmp.", CondStr, ".", Typestr,
167 list<dag> Pattern = [];
170 //===----------------------------------------------------------------------===//
172 // Instruction Multiclasses
174 //===----------------------------------------------------------------------===//
176 multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
177 RegisterOperand FGROpnd>{
178 def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_F>,
179 CMP_CONDN_DESC_BASE<"f", Typestr, FGROpnd>,
181 def CMP_UN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
182 CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>,
184 def CMP_EQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,
185 CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>,
187 def CMP_UEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UEQ>,
188 CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>,
190 def CMP_OLT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLT>,
191 CMP_CONDN_DESC_BASE<"olt", Typestr, FGROpnd>,
193 def CMP_ULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULT>,
194 CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>,
196 def CMP_OLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLE>,
197 CMP_CONDN_DESC_BASE<"ole", Typestr, FGROpnd>,
199 def CMP_ULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULE>,
200 CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>,
202 def CMP_SF_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SF>,
203 CMP_CONDN_DESC_BASE<"sf", Typestr, FGROpnd>,
205 def CMP_NGLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGLE>,
206 CMP_CONDN_DESC_BASE<"ngle", Typestr, FGROpnd>,
208 def CMP_SEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SEQ>,
209 CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>,
211 def CMP_NGL_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGL>,
212 CMP_CONDN_DESC_BASE<"ngl", Typestr, FGROpnd>,
214 def CMP_LT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
215 CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>,
217 def CMP_NGE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGE>,
218 CMP_CONDN_DESC_BASE<"nge", Typestr, FGROpnd>,
220 def CMP_LE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
221 CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>,
223 def CMP_NGT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGT>,
224 CMP_CONDN_DESC_BASE<"ngt", Typestr, FGROpnd>,
228 //===----------------------------------------------------------------------===//
230 // Instruction Descriptions
232 //===----------------------------------------------------------------------===//
234 class PCREL19_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
235 dag OutOperandList = (outs GPROpnd:$rs);
236 dag InOperandList = (ins simm19_lsl2:$imm);
237 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
238 list<dag> Pattern = [];
241 class ADDIUPC_DESC : PCREL19_DESC_BASE<"addiupc", GPR32Opnd>;
242 class LWPC_DESC: PCREL19_DESC_BASE<"lwpc", GPR32Opnd>;
243 class LWUPC_DESC: PCREL19_DESC_BASE<"lwupc", GPR32Opnd>;
245 class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
247 dag OutOperandList = (outs GPROpnd:$rd);
248 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
249 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
250 list<dag> Pattern = [];
253 class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2>;
255 class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
256 dag OutOperandList = (outs GPROpnd:$rs);
257 dag InOperandList = (ins simm16:$imm);
258 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
259 list<dag> Pattern = [];
262 class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>;
263 class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>;
265 class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
266 dag OutOperandList = (outs GPROpnd:$rs);
267 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
268 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
269 list<dag> Pattern = [];
272 class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
274 class BRANCH_DESC_BASE {
276 bit isTerminator = 1;
277 bit hasDelaySlot = 0;
280 class BC_DESC_BASE<string instr_asm, DAGOperand opnd> : BRANCH_DESC_BASE {
281 dag InOperandList = (ins opnd:$offset);
282 dag OutOperandList = (outs);
283 string AsmString = !strconcat(instr_asm, "\t$offset");
287 class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> {
289 list<Register> Defs = [RA];
292 class BC_DESC : BC_DESC_BASE<"bc", brtarget26>;
294 class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd,
295 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
296 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
297 dag OutOperandList = (outs);
298 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
299 list<Register> Defs = [AT];
302 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
303 class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
305 class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
306 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
307 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
308 dag OutOperandList = (outs);
309 string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
310 list<Register> Defs = [AT];
313 class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd> {
314 string Constraints = "$rs = $rt";
317 class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd> {
318 string Constraints = "$rs = $rt";
321 class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;
322 class BGTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR32Opnd>;
324 class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
325 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
326 dag InOperandList = (ins GPROpnd:$rs, opnd:$offset);
327 dag OutOperandList = (outs);
328 string AsmString = !strconcat(instr_asm, "\t$rs, $offset");
329 list<Register> Defs = [AT];
332 class BEQZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>;
333 class BNEZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>;
335 class BEQZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> {
336 list<Register> Defs = [RA];
339 class BGEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezalc", brtarget, GPR32Opnd> {
340 string Constraints = "$rs = $rt";
341 list<Register> Defs = [RA];
344 class BGTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzalc", brtarget, GPR32Opnd> {
345 list<Register> Defs = [RA];
348 class BLEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezalc", brtarget, GPR32Opnd> {
349 list<Register> Defs = [RA];
352 class BLTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzalc", brtarget, GPR32Opnd> {
353 string Constraints = "$rs = $rt";
354 list<Register> Defs = [RA];
357 class BNEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bnezalc", brtarget, GPR32Opnd> {
358 list<Register> Defs = [RA];
361 class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
362 dag OutOperandList = (outs GPROpnd:$rd);
363 dag InOperandList = (ins GPROpnd:$rt);
364 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
365 list<dag> Pattern = [];
368 class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>;
370 class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
371 dag OutOperandList = (outs FGROpnd:$fd);
372 dag InOperandList = (ins FGROpnd:$fs);
373 string AsmString = !strconcat(instr_asm, "\t$fd, $fs");
374 list<dag> Pattern = [];
377 class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>;
378 class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>;
379 class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>;
380 class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>;
382 class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
383 dag OutOperandList = (outs GPROpnd:$rd);
384 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
385 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
386 list<dag> Pattern = [];
389 class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd>;
390 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd>;
391 class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd>;
392 class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd>;
394 class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
395 RegisterOperand GPROpnd> {
396 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
397 string AsmString = !strconcat(opstr, "\t$rt, $offset");
398 list<dag> Pattern = [];
399 bit isTerminator = 1;
400 bit hasDelaySlot = 0;
401 string DecoderMethod = "DecodeSimm16";
404 class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
407 list<Register> Defs = [RA];
410 class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR32Opnd> {
412 list<Register> Defs = [AT];
415 class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
416 dag OutOperandList = (outs FGROpnd:$fd);
417 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
418 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
419 list<dag> Pattern = [];
420 string Constraints = "$fd_in = $fd";
423 class MADDF_S_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>;
424 class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>;
425 class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>;
426 class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>;
428 class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
429 dag OutOperandList = (outs FGROpnd:$fd);
430 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
431 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
432 list<dag> Pattern = [];
435 class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>;
436 class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>;
437 class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>;
438 class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>;
440 class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>;
441 class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>;
442 class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>;
443 class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>;
445 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
446 dag OutOperandList = (outs GPROpnd:$rd);
447 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
448 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
449 list<dag> Pattern = [];
452 class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd>;
453 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd>;
454 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd>;
455 class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
457 class SEL_D_DESC : COP1_4R_DESC_BASE<"sel.d", FGR64Opnd>;
458 class SEL_S_DESC : COP1_4R_DESC_BASE<"sel.s", FGR32Opnd>;
460 class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
461 dag OutOperandList = (outs GPROpnd:$rd);
462 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
463 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
464 list<dag> Pattern = [];
467 class SELEQZ_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR32Opnd>;
468 class SELNEZ_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR32Opnd>;
470 class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
471 dag OutOperandList = (outs FGROpnd:$fd);
472 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
473 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
474 list<dag> Pattern = [];
477 class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
478 class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
479 class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
480 class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
482 //===----------------------------------------------------------------------===//
484 // Instruction Definitions
486 //===----------------------------------------------------------------------===//
488 def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
489 def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
490 def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
491 def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
492 def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
493 def BALC : BALC_ENC, BALC_DESC, ISA_MIPS32R6;
498 def BC : BC_ENC, BC_DESC, ISA_MIPS32R6;
499 def BEQC : BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;
500 def BEQZALC : BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6;
501 def BEQZC : BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6;
502 def BGEC; // Also aliased to blec with operands swapped
503 def BGEUC; // Also aliased to bleuc with operands swapped
504 def BGEZALC : BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6;
505 def BGEZC : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6;
506 def BGTZALC : BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6;
507 def BGTZC : BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6;
508 def BITSWAP : BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
509 def BLEZALC : BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6;
510 def BLEZC : BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6;
511 def BLTC; // Also aliased to bgtc with operands swapped
512 def BLTUC; // Also aliased to bgtuc with operands swapped
513 def BLTZALC : BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6;
514 def BLTZC : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6;
515 def BNEC : BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;
516 def BNEZALC : BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6;
517 def BNEZC : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
520 def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6;
521 def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6;
522 defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;
523 defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>;
524 def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;
525 def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
526 def JIALC : JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
527 def JIC : JIC_ENC, JIC_DESC, ISA_MIPS32R6;
528 // def LSA; // See MSA
529 def LWPC : LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
530 def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
531 def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6;
532 def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6;
533 def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6;
534 def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6;
535 def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6;
536 def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6;
537 def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6;
538 def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6;
539 def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6;
540 def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6;
541 def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6;
542 def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6;
543 def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6;
544 def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6;
545 def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6;
546 def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
547 def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
548 def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6;
549 def NAL; // BAL with rd=0
550 def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6;
551 def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6;
552 def SELEQZ : SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6;
553 def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6;
554 def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6;
555 def SELNEZ : SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6;
556 def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6;
557 def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6;
558 def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6;
559 def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6;