1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips32r6 instructions.
12 //===----------------------------------------------------------------------===//
14 include "Mips32r6InstrFormats.td"
16 // Notes about removals/changes from MIPS32r6:
18 // Reencoded: cache, pref
19 // Reencoded: clo, clz
20 // Reencoded: jr -> jalr
21 // Reencoded: jr.hb -> jalr.hb
28 // Removed: bc1any2, bc1any4
30 // Removed: bc2f, bc2t
40 // Rencoded: [ls][wd]c2
42 def brtarget21 : Operand<OtherVT> {
43 let EncoderMethod = "getBranchTarget21OpValue";
44 let OperandType = "OPERAND_PCREL";
45 let DecoderMethod = "DecodeBranchTarget21";
46 let ParserMatchClass = MipsJumpTargetAsmOperand;
49 def brtarget26 : Operand<OtherVT> {
50 let EncoderMethod = "getBranchTarget26OpValue";
51 let OperandType = "OPERAND_PCREL";
52 let DecoderMethod = "DecodeBranchTarget26";
53 let ParserMatchClass = MipsJumpTargetAsmOperand;
56 def jmpoffset16 : Operand<OtherVT> {
57 let EncoderMethod = "getJumpOffset16OpValue";
58 let ParserMatchClass = MipsJumpTargetAsmOperand;
61 def calloffset16 : Operand<iPTR> {
62 let EncoderMethod = "getJumpOffset16OpValue";
63 let ParserMatchClass = MipsJumpTargetAsmOperand;
66 //===----------------------------------------------------------------------===//
68 // Instruction Encodings
70 //===----------------------------------------------------------------------===//
72 class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>;
73 class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>;
74 class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
75 class AUI_ENC : AUI_FM;
76 class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;
78 class BALC_ENC : BRANCH_OFF26_FM<0b111010>;
79 class BC_ENC : BRANCH_OFF26_FM<0b110010>;
80 class BEQC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
81 DecodeDisambiguates<"AddiGroupBranch">;
82 class BEQZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_ADDI>,
83 DecodeDisambiguatedBy<"DaddiGroupBranch">;
84 class BNEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
85 DecodeDisambiguates<"DaddiGroupBranch">;
86 class BNEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_DADDI>,
87 DecodeDisambiguatedBy<"DaddiGroupBranch">;
89 class BLTZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZL>,
90 DecodeDisambiguates<"BgtzlGroupBranch">;
91 class BGEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZL>,
92 DecodeDisambiguatedBy<"BlezlGroupBranch">;
93 class BGEUC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZ>,
94 DecodeDisambiguatedBy<"BlezGroupBranch">;
95 class BGEZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZL>,
96 DecodeDisambiguates<"BlezlGroupBranch">;
97 class BGTZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZ>,
98 DecodeDisambiguatedBy<"BgtzGroupBranch">;
100 class BLEZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZL>,
101 DecodeDisambiguatedBy<"BlezlGroupBranch">;
102 class BLTZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZ>,
103 DecodeDisambiguates<"BgtzGroupBranch">;
104 class BGTZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZL>,
105 DecodeDisambiguatedBy<"BgtzlGroupBranch">;
107 class BEQZC_ENC : CMP_BRANCH_OFF21_FM<0b110110>;
108 class BGEZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZ>,
109 DecodeDisambiguates<"BlezGroupBranch">;
110 class BNEZC_ENC : CMP_BRANCH_OFF21_FM<0b111110>;
112 class BC1EQZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1EQZ>;
113 class BC1NEZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1NEZ>;
114 class BC2EQZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2EQZ>;
115 class BC2NEZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2NEZ>;
117 class JIALC_ENC : JMP_IDX_COMPACT_FM<0b111110>;
118 class JIC_ENC : JMP_IDX_COMPACT_FM<0b110110>;
119 class JR_HB_R6_ENC : JR_HB_R6_FM<OPCODE6_JALR>;
120 class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>;
121 class BLEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZ>,
122 DecodeDisambiguatedBy<"BlezGroupBranch">;
123 class BNVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
124 DecodeDisambiguatedBy<"DaddiGroupBranch">;
125 class BOVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
126 DecodeDisambiguatedBy<"AddiGroupBranch">;
127 class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
128 class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
129 class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;
130 class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>;
131 class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>;
132 class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>;
133 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
134 class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>;
136 class MADDF_S_ENC : COP1_3R_FM<0b011000, FIELD_FMT_S>;
137 class MADDF_D_ENC : COP1_3R_FM<0b011000, FIELD_FMT_D>;
138 class MSUBF_S_ENC : COP1_3R_FM<0b011001, FIELD_FMT_S>;
139 class MSUBF_D_ENC : COP1_3R_FM<0b011001, FIELD_FMT_D>;
141 class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>;
142 class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>;
144 class SELEQZ_ENC : SPECIAL_3R_FM<0b00000, 0b110101>;
145 class SELNEZ_ENC : SPECIAL_3R_FM<0b00000, 0b110111>;
147 class LWPC_ENC : PCREL19_FM<OPCODE2_LWPC>;
148 class LWUPC_ENC : PCREL19_FM<OPCODE2_LWUPC>;
150 class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
151 class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
152 class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>;
153 class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>;
155 class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>;
156 class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>;
157 class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>;
158 class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>;
160 class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>;
161 class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>;
162 class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>;
163 class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>;
165 class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>;
166 class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>;
167 class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>;
168 class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>;
170 class CMP_CONDN_DESC_BASE<string CondStr, string Typestr,
171 RegisterOperand FGROpnd,
172 SDPatternOperator Op = null_frag> {
173 dag OutOperandList = (outs FGRCCOpnd:$fd);
174 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
175 string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft");
176 list<dag> Pattern = [(set FGRCCOpnd:$fd, (Op FGROpnd:$fs, FGROpnd:$ft))];
179 //===----------------------------------------------------------------------===//
181 // Instruction Multiclasses
183 //===----------------------------------------------------------------------===//
185 multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
186 RegisterOperand FGROpnd>{
187 def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_F>,
188 CMP_CONDN_DESC_BASE<"f", Typestr, FGROpnd>,
190 def CMP_UN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
191 CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, setuo>,
193 def CMP_EQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,
194 CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, setoeq>,
196 def CMP_UEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UEQ>,
197 CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, setueq>,
199 def CMP_OLT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLT>,
200 CMP_CONDN_DESC_BASE<"olt", Typestr, FGROpnd, setolt>,
202 def CMP_ULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULT>,
203 CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, setult>,
205 def CMP_OLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLE>,
206 CMP_CONDN_DESC_BASE<"ole", Typestr, FGROpnd, setole>,
208 def CMP_ULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULE>,
209 CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, setule>,
211 def CMP_SF_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SF>,
212 CMP_CONDN_DESC_BASE<"sf", Typestr, FGROpnd>,
214 def CMP_NGLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGLE>,
215 CMP_CONDN_DESC_BASE<"ngle", Typestr, FGROpnd>,
217 def CMP_SEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SEQ>,
218 CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>,
220 def CMP_NGL_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGL>,
221 CMP_CONDN_DESC_BASE<"ngl", Typestr, FGROpnd>,
223 def CMP_LT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
224 CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>,
226 def CMP_NGE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGE>,
227 CMP_CONDN_DESC_BASE<"nge", Typestr, FGROpnd>,
229 def CMP_LE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
230 CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>,
232 def CMP_NGT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGT>,
233 CMP_CONDN_DESC_BASE<"ngt", Typestr, FGROpnd>,
237 //===----------------------------------------------------------------------===//
239 // Instruction Descriptions
241 //===----------------------------------------------------------------------===//
243 class PCREL_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
245 dag OutOperandList = (outs GPROpnd:$rs);
246 dag InOperandList = (ins ImmOpnd:$imm);
247 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
248 list<dag> Pattern = [];
251 class ADDIUPC_DESC : PCREL_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
252 class LWPC_DESC: PCREL_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
253 class LWUPC_DESC: PCREL_DESC_BASE<"lwupc", GPR32Opnd, simm19_lsl2>;
255 class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
257 dag OutOperandList = (outs GPROpnd:$rd);
258 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
259 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
260 list<dag> Pattern = [];
263 class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2>;
265 class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
266 dag OutOperandList = (outs GPROpnd:$rs);
267 dag InOperandList = (ins simm16:$imm);
268 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
269 list<dag> Pattern = [];
272 class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>;
273 class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>;
275 class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
276 dag OutOperandList = (outs GPROpnd:$rs);
277 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
278 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
279 list<dag> Pattern = [];
282 class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
284 class BRANCH_DESC_BASE {
286 bit isTerminator = 1;
287 bit hasDelaySlot = 0;
290 class BC_DESC_BASE<string instr_asm, DAGOperand opnd> : BRANCH_DESC_BASE {
291 dag InOperandList = (ins opnd:$offset);
292 dag OutOperandList = (outs);
293 string AsmString = !strconcat(instr_asm, "\t$offset");
297 class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd,
298 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
299 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
300 dag OutOperandList = (outs);
301 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
302 list<Register> Defs = [AT];
305 class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
306 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
307 dag InOperandList = (ins GPROpnd:$rs, opnd:$offset);
308 dag OutOperandList = (outs);
309 string AsmString = !strconcat(instr_asm, "\t$rs, $offset");
310 list<Register> Defs = [AT];
313 class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
314 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
315 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
316 dag OutOperandList = (outs);
317 string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
318 list<Register> Defs = [AT];
321 class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> {
323 list<Register> Defs = [RA];
326 class BC_DESC : BC_DESC_BASE<"bc", brtarget26>;
327 class BGEC_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR32Opnd>;
328 class BGEUC_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR32Opnd>;
329 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
330 class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
332 class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd>;
333 class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd>;
335 class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;
336 class BGTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR32Opnd>;
338 class BEQZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>;
339 class BNEZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>;
341 class COP1_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
342 dag InOperandList = (ins FGR64Opnd:$ft, brtarget:$offset);
343 dag OutOperandList = (outs);
344 string AsmString = instr_asm;
345 bit hasDelaySlot = 1;
348 class BC1EQZ_DESC : COP1_BCCZ_DESC_BASE<"bc1eqz $ft, $offset">;
349 class BC1NEZ_DESC : COP1_BCCZ_DESC_BASE<"bc1nez $ft, $offset">;
351 class COP2_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
352 dag InOperandList = (ins COP2Opnd:$ct, brtarget:$offset);
353 dag OutOperandList = (outs);
354 string AsmString = instr_asm;
355 bit hasDelaySlot = 1;
358 class BC2EQZ_DESC : COP2_BCCZ_DESC_BASE<"bc2eqz $ct, $offset">;
359 class BC2NEZ_DESC : COP2_BCCZ_DESC_BASE<"bc2nez $ct, $offset">;
361 class BOVC_DESC : CMP_BC_DESC_BASE<"bovc", brtarget, GPR32Opnd>;
362 class BNVC_DESC : CMP_BC_DESC_BASE<"bnvc", brtarget, GPR32Opnd>;
364 class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
365 RegisterOperand GPROpnd> {
366 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
367 string AsmString = !strconcat(opstr, "\t$rt, $offset");
368 list<dag> Pattern = [];
369 bit isTerminator = 1;
370 bit hasDelaySlot = 0;
371 string DecoderMethod = "DecodeSimm16";
374 class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
377 list<Register> Defs = [RA];
380 class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR32Opnd> {
382 list<Register> Defs = [AT];
385 class JR_HB_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
387 bit isIndirectBranch = 1;
388 bit hasDelaySlot = 1;
393 class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
394 dag OutOperandList = (outs GPROpnd:$rd);
395 dag InOperandList = (ins GPROpnd:$rt);
396 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
397 list<dag> Pattern = [];
400 class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>;
402 class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
403 SDPatternOperator Op=null_frag> {
404 dag OutOperandList = (outs GPROpnd:$rd);
405 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
406 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
407 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
409 // This instruction doesn't trap division by zero itself. We must insert
410 // teq instructions as well.
411 bit usesCustomInserter = 1;
414 class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd, sdiv>;
415 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd, udiv>;
416 class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd, srem>;
417 class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd, urem>;
419 class BEQZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> {
420 list<Register> Defs = [RA];
423 class BGEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezalc", brtarget, GPR32Opnd> {
424 list<Register> Defs = [RA];
427 class BGTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzalc", brtarget, GPR32Opnd> {
428 list<Register> Defs = [RA];
431 class BLEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezalc", brtarget, GPR32Opnd> {
432 list<Register> Defs = [RA];
435 class BLTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzalc", brtarget, GPR32Opnd> {
436 list<Register> Defs = [RA];
439 class BNEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bnezalc", brtarget, GPR32Opnd> {
440 list<Register> Defs = [RA];
443 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
444 SDPatternOperator Op=null_frag> {
445 dag OutOperandList = (outs GPROpnd:$rd);
446 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
447 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
448 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
451 class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd, mulhs>;
452 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd, mulhu>;
453 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd, mul>;
454 class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
456 class COP1_SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
457 dag OutOperandList = (outs FGROpnd:$fd);
458 dag InOperandList = (ins FGRCCOpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
459 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
460 list<dag> Pattern = [(set FGROpnd:$fd, (select FGRCCOpnd:$fd_in,
463 string Constraints = "$fd_in = $fd";
466 class SEL_D_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd> {
467 // We must insert a SUBREG_TO_REG around $fd_in
468 bit usesCustomInserter = 1;
470 class SEL_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd>;
472 class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
473 dag OutOperandList = (outs GPROpnd:$rd);
474 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
475 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
476 list<dag> Pattern = [];
479 class SELEQZ_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR32Opnd>;
480 class SELNEZ_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR32Opnd>;
482 class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
483 dag OutOperandList = (outs FGROpnd:$fd);
484 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
485 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
486 list<dag> Pattern = [];
487 string Constraints = "$fd_in = $fd";
490 class MADDF_S_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>;
491 class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>;
492 class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>;
493 class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>;
495 class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
496 dag OutOperandList = (outs FGROpnd:$fd);
497 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
498 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
499 list<dag> Pattern = [];
502 class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>;
503 class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>;
504 class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>;
505 class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>;
507 class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>;
508 class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>;
509 class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>;
510 class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>;
512 class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
513 dag OutOperandList = (outs FGROpnd:$fd);
514 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
515 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
516 list<dag> Pattern = [];
519 class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
520 class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
521 class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
522 class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
524 class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
525 dag OutOperandList = (outs FGROpnd:$fd);
526 dag InOperandList = (ins FGROpnd:$fs);
527 string AsmString = !strconcat(instr_asm, "\t$fd, $fs");
528 list<dag> Pattern = [];
531 class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>;
532 class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>;
533 class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>;
534 class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>;
536 //===----------------------------------------------------------------------===//
538 // Instruction Definitions
540 //===----------------------------------------------------------------------===//
542 def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
543 def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
544 def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
545 def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
546 def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
547 def BALC : BALC_ENC, BALC_DESC, ISA_MIPS32R6;
548 def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6;
549 def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6;
550 def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6;
551 def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6;
552 def BC : BC_ENC, BC_DESC, ISA_MIPS32R6;
553 def BEQC : BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;
554 def BEQZALC : BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6;
555 def BEQZC : BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6;
556 def BGEC : BGEC_ENC, BGEC_DESC, ISA_MIPS32R6;
557 def BGEUC : BGEUC_ENC, BGEUC_DESC, ISA_MIPS32R6;
558 def BGEZALC : BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6;
559 def BGEZC : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6;
560 def BGTZALC : BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6;
561 def BGTZC : BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6;
562 def BITSWAP : BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
563 def BLEZALC : BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6;
564 def BLEZC : BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6;
565 def BLTC; // Also aliased to bgtc with operands swapped
566 def BLTUC; // Also aliased to bgtuc with operands swapped
567 def BLTZALC : BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6;
568 def BLTZC : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6;
569 def BNEC : BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;
570 def BNEZALC : BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6;
571 def BNEZC : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
572 def BNVC : BNVC_ENC, BNVC_DESC, ISA_MIPS32R6;
573 def BOVC : BOVC_ENC, BOVC_DESC, ISA_MIPS32R6;
574 def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6;
575 def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6;
576 defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;
577 defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>;
578 def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;
579 def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
580 def JIALC : JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
581 def JIC : JIC_ENC, JIC_DESC, ISA_MIPS32R6;
582 def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6;
583 // def LSA; // See MSA
584 def LWPC : LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
585 def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
586 def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6;
587 def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6;
588 def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6;
589 def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6;
590 def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6;
591 def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6;
592 def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6;
593 def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6;
594 def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6;
595 def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6;
596 def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6;
597 def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6;
598 def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6;
599 def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6;
600 def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6;
601 def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
602 def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
603 def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6;
604 def NAL; // BAL with rd=0
605 def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6;
606 def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6;
607 def SELEQZ : SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32;
608 def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6;
609 def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6;
610 def SELNEZ : SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32;
611 def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6;
612 def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6;
613 def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6;
614 def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6;
616 //===----------------------------------------------------------------------===//
618 // Patterns and Pseudo Instructions
620 //===----------------------------------------------------------------------===//
622 // f32 comparisons supported via another comparison
623 def : MipsPat<(setone f32:$lhs, f32:$rhs),
624 (NOR (CMP_UEQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
625 def : MipsPat<(seto f32:$lhs, f32:$rhs),
626 (NOR (CMP_UN_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
627 def : MipsPat<(setune f32:$lhs, f32:$rhs),
628 (NOR (CMP_EQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
629 def : MipsPat<(seteq f32:$lhs, f32:$rhs), (CMP_EQ_S f32:$lhs, f32:$rhs)>,
631 def : MipsPat<(setgt f32:$lhs, f32:$rhs), (CMP_LE_S f32:$rhs, f32:$lhs)>,
633 def : MipsPat<(setge f32:$lhs, f32:$rhs), (CMP_LT_S f32:$rhs, f32:$lhs)>,
635 def : MipsPat<(setlt f32:$lhs, f32:$rhs), (CMP_OLT_S f32:$lhs, f32:$rhs)>,
637 def : MipsPat<(setlt f32:$lhs, f32:$rhs), (CMP_OLE_S f32:$lhs, f32:$rhs)>,
639 def : MipsPat<(setne f32:$lhs, f32:$rhs),
640 (NOR (CMP_EQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
642 // f64 comparisons supported via another comparison
643 def : MipsPat<(setone f64:$lhs, f64:$rhs),
644 (NOR (CMP_UEQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
645 def : MipsPat<(seto f64:$lhs, f64:$rhs),
646 (NOR (CMP_UN_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
647 def : MipsPat<(setune f64:$lhs, f64:$rhs),
648 (NOR (CMP_EQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
649 def : MipsPat<(seteq f64:$lhs, f64:$rhs), (CMP_EQ_D f64:$lhs, f64:$rhs)>,
651 def : MipsPat<(setgt f64:$lhs, f64:$rhs), (CMP_LE_D f64:$rhs, f64:$lhs)>,
653 def : MipsPat<(setge f64:$lhs, f64:$rhs), (CMP_LT_D f64:$rhs, f64:$lhs)>,
655 def : MipsPat<(setlt f64:$lhs, f64:$rhs), (CMP_OLT_D f64:$lhs, f64:$rhs)>,
657 def : MipsPat<(setlt f64:$lhs, f64:$rhs), (CMP_OLE_D f64:$lhs, f64:$rhs)>,
659 def : MipsPat<(setne f64:$lhs, f64:$rhs),
660 (NOR (CMP_EQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
663 def : MipsPat<(select i32:$cond, i32:$t, i32:$f),
664 (OR (SELNEZ i32:$t, i32:$cond), (SELEQZ i32:$f, i32:$cond))>,
666 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i32:$t, i32:$f),
667 (OR (SELNEZ i32:$t, i32:$cond), (SELEQZ i32:$f, i32:$cond))>,
669 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i32:$t, i32:$f),
670 (OR (SELNEZ i32:$f, i32:$cond), (SELEQZ i32:$t, i32:$cond))>,
672 def : MipsPat<(select (i32 (seteq i32:$cond, immZExt16:$imm)), i32:$t, i32:$f),
673 (OR (SELNEZ i32:$t, (XORi i32:$cond, immZExt16:$imm)),
674 (SELEQZ i32:$f, (XORi i32:$cond, immZExt16:$imm)))>,
676 def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i32:$t, i32:$f),
677 (OR (SELNEZ i32:$f, (XORi i32:$cond, immZExt16:$imm)),
678 (SELEQZ i32:$t, (XORi i32:$cond, immZExt16:$imm)))>,
680 def : MipsPat<(select (i32 (setgt i32:$cond, immSExt16Plus1:$imm)), i32:$t,
682 (OR (SELNEZ i32:$t, (SLTi i32:$cond, (Plus1 imm:$imm))),
683 (SELEQZ i32:$f, (SLTi i32:$cond, (Plus1 imm:$imm))))>,
685 def : MipsPat<(select (i32 (setugt i32:$cond, immSExt16Plus1:$imm)),
687 (OR (SELNEZ i32:$t, (SLTiu i32:$cond, (Plus1 imm:$imm))),
688 (SELEQZ i32:$f, (SLTiu i32:$cond, (Plus1 imm:$imm))))>,
691 def : MipsPat<(select i32:$cond, i32:$t, immz),
692 (SELNEZ i32:$t, i32:$cond)>, ISA_MIPS32R6;
693 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i32:$t, immz),
694 (SELNEZ i32:$t, i32:$cond)>, ISA_MIPS32R6;
695 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i32:$t, immz),
696 (SELEQZ i32:$t, i32:$cond)>, ISA_MIPS32R6;
697 def : MipsPat<(select i32:$cond, immz, i32:$f),
698 (SELEQZ i32:$f, i32:$cond)>, ISA_MIPS32R6;
699 def : MipsPat<(select (i32 (setne i32:$cond, immz)), immz, i32:$f),
700 (SELEQZ i32:$f, i32:$cond)>, ISA_MIPS32R6;
701 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), immz, i32:$f),
702 (SELNEZ i32:$f, i32:$cond)>, ISA_MIPS32R6;