lib/Target/Mips/Mips32r6InstrInfo.td

   1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes Mips32r6 instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // Notes about removals/changes from MIPS32r6:
  15 // Unclear: ssnop
  16 // Reencoded: cache, pref
  17 // Reencoded: clo, clz
  18 // Reencoded: jr -> jalr
  19 // Reencoded: jr.hb -> jalr.hb
  20 // Reencoded: ldc2
  21 // Reencoded: ll, sc
  22 // Reencoded: lwc2
  23 // Reencoded: sdbbp
  24 // Reencoded: sdc2
  25 // Reencoded: swc2
  26 // Removed: /.ps$/, cvt.ps.s, cvt.ps.pw
  27 // Removed: addi
  28 // Removed: bc1any2, bc1any4
  29 // Removed: bc2[ft]
  30 // Removed: bc2f, bc2t
  31 // Removed: bc[12][ft]l, bgezl, bgtzl, bgtzl, blezl, bltzall, bltzl, bnel, bgezall,
  32 // Removed: beql
  33 // Removed: bgezal
  34 // Removed: bltzal
  35 // Removed: c.cond.fmt, bc1[ft]
  36 // Removed: div, divu
  37 // Removed: jalx
  38 // Removed: ldxc1
  39 // Removed: luxc1
  40 // Removed: lwl, lwr, lwle, lwre, swl, swr, swle, swre
  41 // Removed: lwxc1
  42 // Removed: madd.[ds], nmadd.[ds], nmsub.[ds], sub.[ds]
  43 // Removed: mfhi, mflo, mthi, mtlo, madd, maddu, msub, msubu, mul
  44 // Removed: movf, movt
  45 // Removed: movf.fmt, movt.fmt, movn.fmt, movz.fmt
  46 // Removed: movn, movz
  47 // Removed: mult, multu
  48 // Removed: prefx
  49 // Removed: sdxc1
  50 // Removed: suxc1
  51 // Removed: swxc1
  52 // Removed: teqi, tgei, tgeiu, tlti, tltiu, tnei
  53 // Rencoded: [ls][wd]c2
  54
  55 def ADDIUPC;
  56 def ALIGN; // Known as as BALIGN in DSP ASE
  57 def ALUIPC;
  58 def AUI;
  59 def AUIPC;
  60 def BALC;
  61 def BC1EQZ;
  62 def BC1NEZ;
  63 def BC2EQZ;
  64 def BC2NEZ;
  65 def BC;
  66 def BEQC;
  67 def BEQZALC;
  68 def BEQZC;
  69 def BGEC;  // Also aliased to blec with operands swapped
  70 def BGEUC; // Also aliased to bleuc with operands swapped
  71 def BGEZALC;
  72 def BGEZC;
  73 def BGTZALC;
  74 def BGTZC;
  75 def BITSWAP; // Known as BITREV in DSP ASE
  76 def BLEZALC;
  77 def BLEZC;
  78 def BLTC; // Also aliased to bgtc with operands swapped
  79 def BLTUC; // Also aliased to bgtuc with operands swapped
  80 def BLTZALC;
  81 def BLTZC;
  82 def BNEC;
  83 def BNEZALC;
  84 def BNEZC;
  85 def BNVC;
  86 def BOVC;
  87 def CLASS_D;
  88 def CLASS_S;
  89 def CMP_CC_D;
  90 def CMP_CC_S;
  91 def DIV;   // Not to be confused with the old div
  92 def DIVU;  // Not to be confused with the old div
  93 def JIALC;
  94 def JIC;
  95 // def LSA; // See MSA
  96 def LWPC;
  97 def LWUPC;
  98 def MADDF;
  99 def MAXA_D;
 100 def MAXA_S;
 101 def MAX_D;
 102 def MAX_S;
 103 def MINA_D;
 104 def MINA_S;
 105 def MIN_D;
 106 def MOD;
 107 def MODU;
 108 def MSUBF;
 109 def MUH;
 110 def MUHU;
 111 def MUL_R6; // Not to be confused with the old mul
 112 def MULU;
 113 def NAL; // BAL with rd=0
 114 def RINT_D;
 115 def RINT_S;
 116 def SELEQZ;
 117 def SELEQZ_D;
 118 def SELEQZ_S;
 119 def SELNEZ;
 120 def SELNEZ_D;
 121 def SELNEZ_S;
 122 def SEL_D;
 123 def SEL_S;