1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips32r6 instructions.
12 //===----------------------------------------------------------------------===//
14 include "Mips32r6InstrFormats.td"
16 // Notes about removals/changes from MIPS32r6:
18 // Reencoded: cache, pref
19 // Reencoded: clo, clz
20 // Reencoded: jr -> jalr
21 // Reencoded: jr.hb -> jalr.hb
28 // Removed: /.ps$/, cvt.ps.s, cvt.ps.pw
30 // Removed: bc1any2, bc1any4
32 // Removed: bc2f, bc2t
35 // Removed: c.cond.fmt, bc1[ft]
40 // Removed: lwl, lwr, lwle, lwre, swl, swr, swle, swre
42 // Removed: madd.[ds], nmadd.[ds], nmsub.[ds], sub.[ds]
43 // Removed: mfhi, mflo, mthi, mtlo, madd, maddu, msub, msubu, mul
44 // Removed: movf, movt
45 // Removed: movf.fmt, movt.fmt, movn.fmt, movz.fmt
46 // Removed: movn, movz
47 // Removed: mult, multu
52 // Removed: teqi, tgei, tgeiu, tlti, tltiu, tnei
53 // Rencoded: [ls][wd]c2
55 //===----------------------------------------------------------------------===//
57 // Instruction Encodings
59 //===----------------------------------------------------------------------===//
61 class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>;
62 class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
63 class AUI_ENC : AUI_FM;
64 class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;
65 class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
66 class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
67 class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;
68 class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>;
69 class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>;
70 class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>;
71 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
72 class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>;
73 class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>;
74 class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>;
76 //===----------------------------------------------------------------------===//
78 // Instruction Descriptions
80 //===----------------------------------------------------------------------===//
82 class ADDIUPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
83 dag OutOperandList = (outs GPROpnd:$rs);
84 dag InOperandList = (ins simm19_lsl2:$imm);
85 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
86 list<dag> Pattern = [];
89 class ADDIUPC_DESC : ADDIUPC_DESC_BASE<"addiupc", GPR32Opnd>;
91 class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
92 dag OutOperandList = (outs GPROpnd:$rs);
93 dag InOperandList = (ins simm16:$imm);
94 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
95 list<dag> Pattern = [];
98 class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>;
99 class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>;
101 class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
102 dag OutOperandList = (outs GPROpnd:$rs);
103 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
104 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
105 list<dag> Pattern = [];
108 class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
110 class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
111 dag OutOperandList = (outs GPROpnd:$rd);
112 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
113 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
114 list<dag> Pattern = [];
117 class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd>;
118 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd>;
119 class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd>;
120 class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd>;
122 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
123 dag OutOperandList = (outs GPROpnd:$rd);
124 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
125 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
126 list<dag> Pattern = [];
129 class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd>;
130 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd>;
131 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd>;
132 class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
134 class SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
135 dag OutOperandList = (outs FGROpnd:$fd);
136 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
137 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
138 list<dag> Pattern = [];
139 string Constraints = "$fd_in = $fd";
142 class SEL_D_DESC : SEL_DESC_BASE<"sel.d", FGR64Opnd>;
143 class SEL_S_DESC : SEL_DESC_BASE<"sel.s", FGR32Opnd>;
145 //===----------------------------------------------------------------------===//
147 // Instruction Definitions
149 //===----------------------------------------------------------------------===//
151 def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
152 def ALIGN; // Known as as BALIGN in DSP ASE
153 def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
154 def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
155 def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
165 def BGEC; // Also aliased to blec with operands swapped
166 def BGEUC; // Also aliased to bleuc with operands swapped
171 def BITSWAP; // Known as BITREV in DSP ASE
174 def BLTC; // Also aliased to bgtc with operands swapped
175 def BLTUC; // Also aliased to bgtuc with operands swapped
187 def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;
188 def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
191 // def LSA; // See MSA
202 def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6;
203 def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6;
205 def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6;
206 def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
207 def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
208 def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6;
209 def NAL; // BAL with rd=0
218 def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6;
219 def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6;