1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips32r6 instructions.
12 //===----------------------------------------------------------------------===//
14 include "Mips32r6InstrFormats.td"
16 // Notes about removals/changes from MIPS32r6:
18 // Reencoded: cache, pref
19 // Reencoded: clo, clz
20 // Reencoded: jr -> jalr
21 // Reencoded: jr.hb -> jalr.hb
28 // Removed: bc1any2, bc1any4
30 // Removed: bc2f, bc2t
33 // Removed: c.cond.fmt, bc1[ft]
38 // Removed: madd.[ds], nmadd.[ds], nmsub.[ds], sub.[ds]
39 // Removed: madd, maddu, msub, msubu
40 // Removed: movf, movt
41 // Removed: movf.fmt, movt.fmt, movn.fmt, movz.fmt
42 // Removed: movn, movz
47 // Rencoded: [ls][wd]c2
49 def brtarget21 : Operand<OtherVT> {
50 let EncoderMethod = "getBranchTarget21OpValue";
51 let OperandType = "OPERAND_PCREL";
52 let DecoderMethod = "DecodeBranchTarget21";
53 let ParserMatchClass = MipsJumpTargetAsmOperand;
56 def brtarget26 : Operand<OtherVT> {
57 let EncoderMethod = "getBranchTarget26OpValue";
58 let OperandType = "OPERAND_PCREL";
59 let DecoderMethod = "DecodeBranchTarget26";
60 let ParserMatchClass = MipsJumpTargetAsmOperand;
63 def jmpoffset16 : Operand<OtherVT> {
64 let EncoderMethod = "getJumpOffset16OpValue";
65 let ParserMatchClass = MipsJumpTargetAsmOperand;
68 def calloffset16 : Operand<iPTR> {
69 let EncoderMethod = "getJumpOffset16OpValue";
70 let ParserMatchClass = MipsJumpTargetAsmOperand;
73 //===----------------------------------------------------------------------===//
75 // Instruction Encodings
77 //===----------------------------------------------------------------------===//
79 class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>;
80 class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>;
81 class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
82 class AUI_ENC : AUI_FM;
83 class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;
85 class BALC_ENC : BRANCH_OFF26_FM<0b111010>;
86 class BC_ENC : BRANCH_OFF26_FM<0b110010>;
87 class BEQC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
88 DecodeDisambiguates<"AddiGroupBranch">;
89 class BEQZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_ADDI>,
90 DecodeDisambiguatedBy<"DaddiGroupBranch">;
91 class BNEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
92 DecodeDisambiguates<"DaddiGroupBranch">;
93 class BNEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_DADDI>,
94 DecodeDisambiguatedBy<"DaddiGroupBranch">;
96 class BLTZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZL>,
97 DecodeDisambiguates<"BgtzlGroupBranch">;
98 class BGEZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZL>,
99 DecodeDisambiguates<"BlezlGroupBranch">;
100 class BGTZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZ>,
101 DecodeDisambiguatedBy<"BgtzGroupBranch">;
103 class BLEZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZL>,
104 DecodeDisambiguatedBy<"BlezlGroupBranch">;
105 class BLTZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZ>,
106 DecodeDisambiguates<"BgtzGroupBranch">;
107 class BGTZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZL>,
108 DecodeDisambiguatedBy<"BgtzlGroupBranch">;
110 class BEQZC_ENC : CMP_BRANCH_OFF21_FM<0b110110>;
111 class BGEZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZ>;
112 class BNEZC_ENC : CMP_BRANCH_OFF21_FM<0b111110>;
114 class BC1EQZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1EQZ>;
115 class BC1NEZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1NEZ>;
116 class BC2EQZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2EQZ>;
117 class BC2NEZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2NEZ>;
119 class JIALC_ENC : JMP_IDX_COMPACT_FM<0b111110>;
120 class JIC_ENC : JMP_IDX_COMPACT_FM<0b110110>;
121 class JR_HB_R6_ENC : JR_HB_R6_FM<OPCODE6_JALR>;
122 class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>;
123 class BLEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZ>;
124 class BNVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
125 DecodeDisambiguatedBy<"DaddiGroupBranch">;
126 class BOVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
127 DecodeDisambiguatedBy<"AddiGroupBranch">;
128 class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
129 class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
130 class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;
131 class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>;
132 class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>;
133 class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>;
134 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
135 class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>;
137 class MADDF_S_ENC : COP1_3R_FM<0b011000, FIELD_FMT_S>;
138 class MADDF_D_ENC : COP1_3R_FM<0b011000, FIELD_FMT_D>;
139 class MSUBF_S_ENC : COP1_3R_FM<0b011001, FIELD_FMT_S>;
140 class MSUBF_D_ENC : COP1_3R_FM<0b011001, FIELD_FMT_D>;
142 class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>;
143 class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>;
145 class SELEQZ_ENC : SPECIAL_3R_FM<0b00000, 0b110101>;
146 class SELNEZ_ENC : SPECIAL_3R_FM<0b00000, 0b110111>;
148 class LWPC_ENC : PCREL19_FM<OPCODE2_LWPC>;
149 class LWUPC_ENC : PCREL19_FM<OPCODE2_LWUPC>;
151 class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
152 class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
153 class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>;
154 class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>;
156 class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>;
157 class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>;
158 class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>;
159 class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>;
161 class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>;
162 class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>;
163 class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>;
164 class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>;
166 class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>;
167 class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>;
168 class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>;
169 class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>;
171 class CMP_CONDN_DESC_BASE<string CondStr, string Typestr, RegisterOperand FGROpnd> {
172 dag OutOperandList = (outs FGROpnd:$fd);
173 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
174 string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft");
175 list<dag> Pattern = [];
178 //===----------------------------------------------------------------------===//
180 // Instruction Multiclasses
182 //===----------------------------------------------------------------------===//
184 multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
185 RegisterOperand FGROpnd>{
186 def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_F>,
187 CMP_CONDN_DESC_BASE<"f", Typestr, FGROpnd>,
189 def CMP_UN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
190 CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>,
192 def CMP_EQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,
193 CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>,
195 def CMP_UEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UEQ>,
196 CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>,
198 def CMP_OLT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLT>,
199 CMP_CONDN_DESC_BASE<"olt", Typestr, FGROpnd>,
201 def CMP_ULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULT>,
202 CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>,
204 def CMP_OLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLE>,
205 CMP_CONDN_DESC_BASE<"ole", Typestr, FGROpnd>,
207 def CMP_ULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULE>,
208 CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>,
210 def CMP_SF_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SF>,
211 CMP_CONDN_DESC_BASE<"sf", Typestr, FGROpnd>,
213 def CMP_NGLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGLE>,
214 CMP_CONDN_DESC_BASE<"ngle", Typestr, FGROpnd>,
216 def CMP_SEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SEQ>,
217 CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>,
219 def CMP_NGL_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGL>,
220 CMP_CONDN_DESC_BASE<"ngl", Typestr, FGROpnd>,
222 def CMP_LT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
223 CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>,
225 def CMP_NGE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGE>,
226 CMP_CONDN_DESC_BASE<"nge", Typestr, FGROpnd>,
228 def CMP_LE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
229 CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>,
231 def CMP_NGT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGT>,
232 CMP_CONDN_DESC_BASE<"ngt", Typestr, FGROpnd>,
236 //===----------------------------------------------------------------------===//
238 // Instruction Descriptions
240 //===----------------------------------------------------------------------===//
242 class PCREL_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
244 dag OutOperandList = (outs GPROpnd:$rs);
245 dag InOperandList = (ins ImmOpnd:$imm);
246 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
247 list<dag> Pattern = [];
250 class ADDIUPC_DESC : PCREL_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
251 class LWPC_DESC: PCREL_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
252 class LWUPC_DESC: PCREL_DESC_BASE<"lwupc", GPR32Opnd, simm19_lsl2>;
254 class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
256 dag OutOperandList = (outs GPROpnd:$rd);
257 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
258 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
259 list<dag> Pattern = [];
262 class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2>;
264 class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
265 dag OutOperandList = (outs GPROpnd:$rs);
266 dag InOperandList = (ins simm16:$imm);
267 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
268 list<dag> Pattern = [];
271 class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>;
272 class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>;
274 class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
275 dag OutOperandList = (outs GPROpnd:$rs);
276 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
277 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
278 list<dag> Pattern = [];
281 class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
283 class BRANCH_DESC_BASE {
285 bit isTerminator = 1;
286 bit hasDelaySlot = 0;
289 class BC_DESC_BASE<string instr_asm, DAGOperand opnd> : BRANCH_DESC_BASE {
290 dag InOperandList = (ins opnd:$offset);
291 dag OutOperandList = (outs);
292 string AsmString = !strconcat(instr_asm, "\t$offset");
296 class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd,
297 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
298 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
299 dag OutOperandList = (outs);
300 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
301 list<Register> Defs = [AT];
304 class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
305 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
306 dag InOperandList = (ins GPROpnd:$rs, opnd:$offset);
307 dag OutOperandList = (outs);
308 string AsmString = !strconcat(instr_asm, "\t$rs, $offset");
309 list<Register> Defs = [AT];
312 class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
313 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
314 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
315 dag OutOperandList = (outs);
316 string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
317 list<Register> Defs = [AT];
320 class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> {
322 list<Register> Defs = [RA];
325 class BC_DESC : BC_DESC_BASE<"bc", brtarget26>;
326 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
327 class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
329 class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd>;
330 class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd>;
332 class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;
333 class BGTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR32Opnd>;
335 class BEQZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>;
336 class BNEZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>;
338 class COP1_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
339 dag InOperandList = (ins FGR64Opnd:$ft, brtarget:$offset);
340 dag OutOperandList = (outs);
341 string AsmString = instr_asm;
342 bit hasDelaySlot = 1;
345 class BC1EQZ_DESC : COP1_BCCZ_DESC_BASE<"bc1eqz $ft, $offset">;
346 class BC1NEZ_DESC : COP1_BCCZ_DESC_BASE<"bc1nez $ft, $offset">;
348 class COP2_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
349 dag InOperandList = (ins COP2Opnd:$ct, brtarget:$offset);
350 dag OutOperandList = (outs);
351 string AsmString = instr_asm;
352 bit hasDelaySlot = 1;
355 class BC2EQZ_DESC : COP2_BCCZ_DESC_BASE<"bc2eqz $ct, $offset">;
356 class BC2NEZ_DESC : COP2_BCCZ_DESC_BASE<"bc2nez $ct, $offset">;
358 class BOVC_DESC : CMP_BC_DESC_BASE<"bovc", brtarget, GPR32Opnd>;
359 class BNVC_DESC : CMP_BC_DESC_BASE<"bnvc", brtarget, GPR32Opnd>;
361 class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
362 RegisterOperand GPROpnd> {
363 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
364 string AsmString = !strconcat(opstr, "\t$rt, $offset");
365 list<dag> Pattern = [];
366 bit isTerminator = 1;
367 bit hasDelaySlot = 0;
368 string DecoderMethod = "DecodeSimm16";
371 class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
374 list<Register> Defs = [RA];
377 class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR32Opnd> {
379 list<Register> Defs = [AT];
382 class JR_HB_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
384 bit isIndirectBranch = 1;
385 bit hasDelaySlot = 1;
390 class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
391 dag OutOperandList = (outs GPROpnd:$rd);
392 dag InOperandList = (ins GPROpnd:$rt);
393 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
394 list<dag> Pattern = [];
397 class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>;
399 class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
400 SDPatternOperator Op=null_frag> {
401 dag OutOperandList = (outs GPROpnd:$rd);
402 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
403 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
404 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
406 // This instruction doesn't trap division by zero itself. We must insert
407 // teq instructions as well.
408 bit usesCustomInserter = 1;
411 class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd, sdiv>;
412 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd, udiv>;
413 class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd, srem>;
414 class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd, urem>;
416 class BEQZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> {
417 list<Register> Defs = [RA];
420 class BGEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezalc", brtarget, GPR32Opnd> {
421 list<Register> Defs = [RA];
424 class BGTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzalc", brtarget, GPR32Opnd> {
425 list<Register> Defs = [RA];
428 class BLEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezalc", brtarget, GPR32Opnd> {
429 list<Register> Defs = [RA];
432 class BLTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzalc", brtarget, GPR32Opnd> {
433 list<Register> Defs = [RA];
436 class BNEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bnezalc", brtarget, GPR32Opnd> {
437 list<Register> Defs = [RA];
440 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
441 SDPatternOperator Op=null_frag> {
442 dag OutOperandList = (outs GPROpnd:$rd);
443 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
444 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
445 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
448 class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd, mulhs>;
449 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd, mulhu>;
450 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd, mul>;
451 class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
453 class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
454 dag OutOperandList = (outs FGROpnd:$fd);
455 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
456 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
457 list<dag> Pattern = [];
458 string Constraints = "$fd_in = $fd";
461 class SEL_D_DESC : COP1_4R_DESC_BASE<"sel.d", FGR64Opnd>;
462 class SEL_S_DESC : COP1_4R_DESC_BASE<"sel.s", FGR32Opnd>;
464 class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
465 dag OutOperandList = (outs GPROpnd:$rd);
466 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
467 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
468 list<dag> Pattern = [];
471 class SELEQZ_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR32Opnd>;
472 class SELNEZ_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR32Opnd>;
474 class MADDF_S_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>;
475 class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>;
476 class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>;
477 class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>;
479 class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
480 dag OutOperandList = (outs FGROpnd:$fd);
481 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
482 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
483 list<dag> Pattern = [];
486 class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>;
487 class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>;
488 class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>;
489 class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>;
491 class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>;
492 class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>;
493 class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>;
494 class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>;
496 class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
497 dag OutOperandList = (outs FGROpnd:$fd);
498 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
499 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
500 list<dag> Pattern = [];
503 class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
504 class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
505 class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
506 class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
508 class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
509 dag OutOperandList = (outs FGROpnd:$fd);
510 dag InOperandList = (ins FGROpnd:$fs);
511 string AsmString = !strconcat(instr_asm, "\t$fd, $fs");
512 list<dag> Pattern = [];
515 class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>;
516 class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>;
517 class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>;
518 class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>;
520 //===----------------------------------------------------------------------===//
522 // Instruction Definitions
524 //===----------------------------------------------------------------------===//
526 def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
527 def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
528 def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
529 def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
530 def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
531 def BALC : BALC_ENC, BALC_DESC, ISA_MIPS32R6;
532 def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6;
533 def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6;
534 def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6;
535 def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6;
536 def BC : BC_ENC, BC_DESC, ISA_MIPS32R6;
537 def BEQC : BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;
538 def BEQZALC : BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6;
539 def BEQZC : BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6;
540 def BGEC; // Also aliased to blec with operands swapped
541 def BGEUC; // Also aliased to bleuc with operands swapped
542 def BGEZALC : BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6;
543 def BGEZC : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6;
544 def BGTZALC : BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6;
545 def BGTZC : BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6;
546 def BITSWAP : BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
547 def BLEZALC : BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6;
548 def BLEZC : BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6;
549 def BLTC; // Also aliased to bgtc with operands swapped
550 def BLTUC; // Also aliased to bgtuc with operands swapped
551 def BLTZALC : BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6;
552 def BLTZC : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6;
553 def BNEC : BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;
554 def BNEZALC : BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6;
555 def BNEZC : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
556 def BNVC : BNVC_ENC, BNVC_DESC, ISA_MIPS32R6;
557 def BOVC : BOVC_ENC, BOVC_DESC, ISA_MIPS32R6;
558 def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6;
559 def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6;
560 defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;
561 defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>;
562 def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;
563 def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
564 def JIALC : JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
565 def JIC : JIC_ENC, JIC_DESC, ISA_MIPS32R6;
566 def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6;
567 // def LSA; // See MSA
568 def LWPC : LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
569 def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
570 def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6;
571 def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6;
572 def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6;
573 def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6;
574 def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6;
575 def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6;
576 def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6;
577 def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6;
578 def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6;
579 def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6;
580 def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6;
581 def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6;
582 def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6;
583 def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6;
584 def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6;
585 def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
586 def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
587 def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6;
588 def NAL; // BAL with rd=0
589 def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6;
590 def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6;
591 def SELEQZ : SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6;
592 def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6;
593 def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6;
594 def SELNEZ : SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6;
595 def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6;
596 def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6;
597 def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6;
598 def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6;