1 //===-- Mips16ISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Mips16 ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsDAGToDAGISel specialized for mips16.
12 //===----------------------------------------------------------------------===//
14 #include "Mips16ISelDAGToDAG.h"
15 #include "MCTargetDesc/MipsBaseInfo.h"
17 #include "MipsAnalyzeImmediate.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsRegisterInfo.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAGNodes.h"
26 #include "llvm/IR/CFG.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetMachine.h"
37 #define DEBUG_TYPE "mips-isel"
39 bool Mips16DAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
40 Subtarget = &TM.getSubtarget<MipsSubtarget>();
41 if (!Subtarget->inMips16Mode())
43 return MipsDAGToDAGISel::runOnMachineFunction(MF);
45 /// Select multiply instructions.
46 std::pair<SDNode*, SDNode*>
47 Mips16DAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, SDLoc DL, EVT Ty,
48 bool HasLo, bool HasHi) {
49 SDNode *Lo = nullptr, *Hi = nullptr;
50 SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0),
52 SDValue InFlag = SDValue(Mul, 0);
55 unsigned Opcode = Mips::Mflo16;
56 Lo = CurDAG->getMachineNode(Opcode, DL, Ty, MVT::Glue, InFlag);
57 InFlag = SDValue(Lo, 1);
60 unsigned Opcode = Mips::Mfhi16;
61 Hi = CurDAG->getMachineNode(Opcode, DL, Ty, InFlag);
63 return std::make_pair(Lo, Hi);
66 void Mips16DAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
67 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
69 if (!MipsFI->globalBaseRegSet())
72 MachineBasicBlock &MBB = MF.front();
73 MachineBasicBlock::iterator I = MBB.begin();
74 MachineRegisterInfo &RegInfo = MF.getRegInfo();
75 const TargetInstrInfo &TII =
76 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
77 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
78 unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg();
79 const TargetRegisterClass *RC =
80 (const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
82 V0 = RegInfo.createVirtualRegister(RC);
83 V1 = RegInfo.createVirtualRegister(RC);
84 V2 = RegInfo.createVirtualRegister(RC);
86 BuildMI(MBB, I, DL, TII.get(Mips::GotPrologue16), V0).
87 addReg(V1, RegState::Define).
88 addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI).
89 addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO);
91 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
92 BuildMI(MBB, I, DL, TII.get(Mips::AdduRxRyRz16), GlobalBaseReg)
93 .addReg(V1).addReg(V2);
96 // Insert instructions to initialize the Mips16 SP Alias register in the
97 // first MBB of the function.
99 void Mips16DAGToDAGISel::initMips16SPAliasReg(MachineFunction &MF) {
100 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
102 if (!MipsFI->mips16SPAliasRegSet())
105 MachineBasicBlock &MBB = MF.front();
106 MachineBasicBlock::iterator I = MBB.begin();
107 const TargetInstrInfo &TII =
108 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
109 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
110 unsigned Mips16SPAliasReg = MipsFI->getMips16SPAliasReg();
112 BuildMI(MBB, I, DL, TII.get(Mips::MoveR3216), Mips16SPAliasReg)
116 void Mips16DAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
117 initGlobalBaseReg(MF);
118 initMips16SPAliasReg(MF);
121 /// getMips16SPAliasReg - Output the instructions required to put the
122 /// SP into a Mips16 accessible aliased register.
123 SDValue Mips16DAGToDAGISel::getMips16SPAliasReg() {
124 unsigned Mips16SPAliasReg =
125 MF->getInfo<MipsFunctionInfo>()->getMips16SPAliasReg();
126 return CurDAG->getRegister(Mips16SPAliasReg,
127 getTargetLowering()->getPointerTy());
130 void Mips16DAGToDAGISel::getMips16SPRefReg(SDNode *Parent, SDValue &AliasReg) {
131 SDValue AliasFPReg = CurDAG->getRegister(Mips::S0,
132 getTargetLowering()->getPointerTy());
134 switch (Parent->getOpcode()) {
136 LoadSDNode *SD = dyn_cast<LoadSDNode>(Parent);
137 switch (SD->getMemoryVT().getSizeInBits()) {
140 AliasReg = TM.getSubtargetImpl()->getFrameLowering()->hasFP(*MF)
142 : getMips16SPAliasReg();
148 StoreSDNode *SD = dyn_cast<StoreSDNode>(Parent);
149 switch (SD->getMemoryVT().getSizeInBits()) {
152 AliasReg = TM.getSubtargetImpl()->getFrameLowering()->hasFP(*MF)
154 : getMips16SPAliasReg();
161 AliasReg = CurDAG->getRegister(Mips::SP, getTargetLowering()->getPointerTy());
166 bool Mips16DAGToDAGISel::selectAddr16(
167 SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset,
169 EVT ValTy = Addr.getValueType();
171 Alias = CurDAG->getTargetConstant(0, ValTy);
173 // if Address is FI, get the TargetFrameIndex.
174 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
175 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
176 Offset = CurDAG->getTargetConstant(0, ValTy);
177 getMips16SPRefReg(Parent, Alias);
180 // on PIC code Load GA
181 if (Addr.getOpcode() == MipsISD::Wrapper) {
182 Base = Addr.getOperand(0);
183 Offset = Addr.getOperand(1);
186 if (TM.getRelocationModel() != Reloc::PIC_) {
187 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
188 Addr.getOpcode() == ISD::TargetGlobalAddress))
191 // Addresses of the form FI+const or FI|const
192 if (CurDAG->isBaseWithConstantOffset(Addr)) {
193 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
194 if (isInt<16>(CN->getSExtValue())) {
196 // If the first operand is a FI, get the TargetFI Node
197 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
198 (Addr.getOperand(0))) {
199 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
200 getMips16SPRefReg(Parent, Alias);
203 Base = Addr.getOperand(0);
205 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
209 // Operand is a result from an ADD.
210 if (Addr.getOpcode() == ISD::ADD) {
211 // When loading from constant pools, load the lower address part in
212 // the instruction itself. Example, instead of:
213 // lui $2, %hi($CPI1_0)
214 // addiu $2, $2, %lo($CPI1_0)
217 // lui $2, %hi($CPI1_0)
218 // lwc1 $f0, %lo($CPI1_0)($2)
219 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
220 Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
221 SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
222 if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
223 isa<JumpTableSDNode>(Opnd0)) {
224 Base = Addr.getOperand(0);
230 // If an indexed floating point load/store can be emitted, return false.
231 const LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(Parent);
234 if (LS->getMemoryVT() == MVT::f32 && Subtarget->hasMips4_32r2())
236 if (LS->getMemoryVT() == MVT::f64 && Subtarget->hasMips4_32r2())
241 Offset = CurDAG->getTargetConstant(0, ValTy);
245 /// Select instructions not customized! Used for
246 /// expanded, promoted and normal instructions
247 std::pair<bool, SDNode*> Mips16DAGToDAGISel::selectNode(SDNode *Node) {
248 unsigned Opcode = Node->getOpcode();
252 // Instruction Selection not handled by the auto-generated
253 // tablegen selection should be handled here.
255 EVT NodeTy = Node->getValueType(0);
263 SDValue InFlag = Node->getOperand(2), CmpLHS;
264 unsigned Opc = InFlag.getOpcode(); (void)Opc;
265 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
266 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
267 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
270 if (Opcode == ISD::ADDE) {
271 CmpLHS = InFlag.getValue(0);
272 MOp = Mips::AdduRxRyRz16;
274 CmpLHS = InFlag.getOperand(0);
275 MOp = Mips::SubuRxRyRz16;
278 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
280 SDValue LHS = Node->getOperand(0);
281 SDValue RHS = Node->getOperand(1);
283 EVT VT = LHS.getValueType();
285 unsigned Sltu_op = Mips::SltuRxRyRz16;
286 SDNode *Carry = CurDAG->getMachineNode(Sltu_op, DL, VT, Ops);
287 unsigned Addu_op = Mips::AdduRxRyRz16;
288 SDNode *AddCarry = CurDAG->getMachineNode(Addu_op, DL, VT,
289 SDValue(Carry,0), RHS);
291 SDNode *Result = CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
292 SDValue(AddCarry,0));
293 return std::make_pair(true, Result);
296 /// Mul with two results
298 case ISD::UMUL_LOHI: {
299 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MultuRxRy16 : Mips::MultRxRy16);
300 std::pair<SDNode*, SDNode*> LoHi = selectMULT(Node, MultOpc, DL, NodeTy,
302 if (!SDValue(Node, 0).use_empty())
303 ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0));
305 if (!SDValue(Node, 1).use_empty())
306 ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0));
308 return std::make_pair(true, nullptr);
313 MultOpc = (Opcode == ISD::MULHU ? Mips::MultuRxRy16 : Mips::MultRxRy16);
314 SDNode *Result = selectMULT(Node, MultOpc, DL, NodeTy, false, true).second;
315 return std::make_pair(true, Result);
319 return std::make_pair(false, nullptr);
322 FunctionPass *llvm::createMips16ISelDag(MipsTargetMachine &TM) {
323 return new Mips16DAGToDAGISel(TM);