lib/Target/Mips/Mips.td

   1 //===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 // This is the top level entry point for the Mips target.
  10 //===----------------------------------------------------------------------===//
  11
  12 //===----------------------------------------------------------------------===//
  13 // Target-independent interfaces
  14 //===----------------------------------------------------------------------===//
  15
  16 include "llvm/Target/Target.td"
  17
  18 //===----------------------------------------------------------------------===//
  19 // Register File, Calling Conv, Instruction Descriptions
  20 //===----------------------------------------------------------------------===//
  21
  22 include "MipsRegisterInfo.td"
  23 include "MipsSchedule.td"
  24 include "MipsInstrInfo.td"
  25 include "MipsCallingConv.td"
  26
  27 def MipsInstrInfo : InstrInfo;
  28
  29 //===----------------------------------------------------------------------===//
  30 // Mips Subtarget features                                                    //
  31 //===----------------------------------------------------------------------===//
  32
  33 def FeatureGP64Bit     : SubtargetFeature<"gp64", "IsGP64bit", "true",
  34                                 "General Purpose Registers are 64-bit wide.">;
  35 def FeatureFP64Bit     : SubtargetFeature<"fp64", "IsFP64bit", "true",
  36                                 "Support 64-bit FP registers.">;
  37 def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
  38                                 "true", "Only supports single precision float">;
  39 def FeatureO32         : SubtargetFeature<"o32", "MipsABI", "O32",
  40                                 "Enable o32 ABI">;
  41 def FeatureN32         : SubtargetFeature<"n32", "MipsABI", "N32",
  42                                 "Enable n32 ABI">;
  43 def FeatureN64         : SubtargetFeature<"n64", "MipsABI", "N64",
  44                                 "Enable n64 ABI">;
  45 def FeatureEABI        : SubtargetFeature<"eabi", "MipsABI", "EABI",
  46                                 "Enable eabi ABI">;
  47 def FeatureVFPU        : SubtargetFeature<"vfpu", "HasVFPU",
  48                                 "true", "Enable vector FPU instructions.">;
  49 def FeatureSEInReg     : SubtargetFeature<"seinreg", "HasSEInReg", "true",
  50                                 "Enable 'signext in register' instructions.">;
  51 def FeatureCondMov     : SubtargetFeature<"condmov", "HasCondMov", "true",
  52                                 "Enable 'conditional move' instructions.">;
  53 def FeatureSwap        : SubtargetFeature<"swap", "HasSwap", "true",
  54                                 "Enable 'byte/half swap' instructions.">;
  55 def FeatureBitCount    : SubtargetFeature<"bitcount", "HasBitCount", "true",
  56                                 "Enable 'count leading bits' instructions.">;
  57 def FeatureFPIdx       : SubtargetFeature<"FPIdx", "HasFPIdx", "true",
  58                                 "Enable 'FP indexed load/store' instructions.">;
  59 def FeatureMips32      : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
  60                                 "Mips32 ISA Support",
  61                                 [FeatureCondMov, FeatureBitCount]>;
  62 def FeatureMips32r2    : SubtargetFeature<"mips32r2", "MipsArchVersion",
  63                                 "Mips32r2", "Mips32r2 ISA Support",
  64                                 [FeatureMips32, FeatureSEInReg, FeatureSwap,
  65                                  FeatureFPIdx]>;
  66 def FeatureMips64      : SubtargetFeature<"mips64", "MipsArchVersion",
  67                                 "Mips64", "Mips64 ISA Support",
  68                                 [FeatureGP64Bit, FeatureFP64Bit,
  69                                  FeatureMips32, FeatureFPIdx]>;
  70 def FeatureMips64r2    : SubtargetFeature<"mips64r2", "MipsArchVersion",
  71                                 "Mips64r2", "Mips64r2 ISA Support",
  72                                 [FeatureMips64, FeatureMips32r2]>;
  73
  74 def FeatureMips16  : SubtargetFeature<"mips16", "InMips16Mode", "true",
  75                                       "Mips16 mode">;
  76
  77 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
  78 def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
  79                                     "Mips DSP-R2 ASE", [FeatureDSP]>;
  80
  81 def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;
  82
  83 def FeatureMicroMips  : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
  84                                          "microMips mode">;
  85
  86 //===----------------------------------------------------------------------===//
  87 // Mips processors supported.
  88 //===----------------------------------------------------------------------===//
  89
  90 class Proc<string Name, list<SubtargetFeature> Features>
  91  : Processor<Name, MipsGenericItineraries, Features>;
  92
  93 def : Proc<"mips32", [FeatureMips32]>;
  94 def : Proc<"mips32r2", [FeatureMips32r2]>;
  95 def : Proc<"mips64", [FeatureMips64]>;
  96 def : Proc<"mips64r2", [FeatureMips64r2]>;
  97 def : Proc<"mips16", [FeatureMips16]>;
  98
  99 def MipsAsmParser : AsmParser {
 100   let ShouldEmitMatchRegisterName = 0;
 101   let MnemonicContainsDot = 1;
 102 }
 103
 104 def MipsAsmParserVariant : AsmParserVariant {
 105   int Variant = 0;
 106
 107   // Recognize hard coded registers.
 108   string RegisterPrefix = "$";
 109 }
 110
 111 def Mips : Target {
 112   let InstructionSet = MipsInstrInfo;
 113   let AssemblyParsers = [MipsAsmParser];
 114   let AssemblyParserVariants = [MipsAsmParserVariant];
 115 }