1 def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
3 def simm4 : Operand<i32>;
5 def simm12 : Operand<i32> {
6 let DecoderMethod = "DecodeSimm12";
9 def uimm5_lsl2 : Operand<OtherVT> {
10 let EncoderMethod = "getUImm5Lsl2Encoding";
13 def simm9_addiusp : Operand<i32> {
14 let EncoderMethod = "getSImm9AddiuspValue";
17 def mem_mm_12 : Operand<i32> {
18 let PrintMethod = "printMemOperand";
19 let MIOperandInfo = (ops GPR32, simm12);
20 let EncoderMethod = "getMemEncodingMMImm12";
21 let ParserMatchClass = MipsMemAsmOperand;
22 let OperandType = "OPERAND_MEMORY";
25 def jmptarget_mm : Operand<OtherVT> {
26 let EncoderMethod = "getJumpTargetOpValueMM";
29 def calltarget_mm : Operand<iPTR> {
30 let EncoderMethod = "getJumpTargetOpValueMM";
33 def brtarget_mm : Operand<OtherVT> {
34 let EncoderMethod = "getBranchTargetOpValueMM";
35 let OperandType = "OPERAND_PCREL";
36 let DecoderMethod = "DecodeBranchTargetMM";
39 class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,
41 InstSE<(outs), (ins RO:$rs, opnd:$offset),
42 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI> {
49 let canFoldAsLoad = 1 in
50 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
52 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
53 !strconcat(opstr, "\t$rt, $addr"),
54 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
56 let DecoderMethod = "DecodeMemMMImm12";
57 string Constraints = "$src = $rt";
60 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
62 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
63 !strconcat(opstr, "\t$rt, $addr"),
64 [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
65 let DecoderMethod = "DecodeMemMMImm12";
68 class LLBaseMM<string opstr, RegisterOperand RO> :
69 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
70 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
71 let DecoderMethod = "DecodeMemMMImm12";
75 class SCBaseMM<string opstr, RegisterOperand RO> :
76 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
77 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
78 let DecoderMethod = "DecodeMemMMImm12";
80 let Constraints = "$rt = $dst";
83 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
84 InstrItinClass Itin = NoItinerary> :
85 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
86 !strconcat(opstr, "\t$rt, $addr"),
87 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
88 let DecoderMethod = "DecodeMemMMImm12";
89 let canFoldAsLoad = 1;
93 class LogicRMM16<string opstr, RegisterOperand RO,
94 InstrItinClass Itin = NoItinerary,
95 SDPatternOperator OpNode = null_frag> :
96 MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),
97 !strconcat(opstr, "\t$rt, $rs"),
98 [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
100 let Constraints = "$rt = $dst";
103 class NotMM16<string opstr, RegisterOperand RO> :
104 MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),
105 !strconcat(opstr, "\t$rt, $rs"),
106 [(set RO:$rt, (not RO:$rs))], NoItinerary, FrmR>;
108 class AddImmUS5<string opstr, RegisterOperand RO> :
109 MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
110 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> {
111 let Constraints = "$rd = $dst";
112 let isCommutable = 1;
115 class AddImmUSP<string opstr> :
116 MicroMipsInst16<(outs), (ins simm9_addiusp:$imm),
117 !strconcat(opstr, "\t$imm"), [], NoItinerary, FrmI>;
119 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
120 MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
121 [], II_MFHI_MFLO, FrmR> {
123 let hasSideEffects = 0;
126 class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
127 InstrItinClass Itin = NoItinerary> :
128 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
129 !strconcat(opstr, "\t$rd, $rs"), [], Itin, FrmR> {
130 let isCommutable = isComm;
131 let isReMaterializable = 1;
134 // 16-bit Jump and Link (Call)
135 class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
136 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
137 [(MipsJmpLink RO:$rs)], IIBranch, FrmR> {
139 let hasDelaySlot = 1;
144 class JumpRegMM16<string opstr, RegisterOperand RO> :
145 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
146 [], IIBranch, FrmR> {
147 let hasDelaySlot = 1;
149 let isIndirectBranch = 1;
152 // Base class for JRADDIUSP instruction.
153 class JumpRAddiuStackMM16 :
154 MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jraddiusp\t$imm",
155 [], IIBranch, FrmR> {
156 let isTerminator = 1;
158 let hasDelaySlot = 1;
160 let isIndirectBranch = 1;
163 // 16-bit Jump and Link (Call) - Short Delay Slot
164 class JumpLinkRegSMM16<string opstr, RegisterOperand RO> :
165 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
166 [], IIBranch, FrmR> {
168 let hasDelaySlot = 1;
172 // 16-bit Jump Register Compact - No delay slot
173 class JumpRegCMM16<string opstr, RegisterOperand RO> :
174 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
175 [], IIBranch, FrmR> {
176 let isTerminator = 1;
179 let isIndirectBranch = 1;
182 // MicroMIPS Jump and Link (Call) - Short Delay Slot
183 let isCall = 1, hasDelaySlot = 1, Defs = [RA] in {
184 class JumpLinkMM<string opstr, DAGOperand opnd> :
185 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
186 [], IIBranch, FrmJ, opstr> {
187 let DecoderMethod = "DecodeJumpTargetMM";
190 class JumpLinkRegMM<string opstr, RegisterOperand RO>:
191 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
194 class BranchCompareToZeroLinkMM<string opstr, DAGOperand opnd,
195 RegisterOperand RO> :
196 InstSE<(outs), (ins RO:$rs, opnd:$offset),
197 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
200 def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
202 def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
204 def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
206 def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>;
207 def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
208 def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
209 def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
210 def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
211 def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
212 def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>;
213 def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>;
214 def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
215 def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
216 def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>;
218 class WaitMM<string opstr> :
219 InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
220 NoItinerary, FrmOther, opstr>;
222 let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
223 /// Compact Branch Instructions
224 def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>,
225 COMPACT_BRANCH_FM_MM<0x7>;
226 def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>,
227 COMPACT_BRANCH_FM_MM<0x5>;
229 /// Arithmetic Instructions (ALU Immediate)
230 def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
232 def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
234 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
236 def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
238 def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
240 def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
242 def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
244 def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM;
246 def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
249 /// Arithmetic Instructions (3-Operand, R-Type)
250 def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd>, ADD_FM_MM<0, 0x150>;
251 def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd>, ADD_FM_MM<0, 0x1d0>;
252 def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
253 def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
254 def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
255 def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
256 def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
258 def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
260 def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
262 def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
264 def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
265 def MULT_MM : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
267 def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
269 def SDIV_MM : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
271 def UDIV_MM : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
274 /// Shift Instructions
275 def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
277 def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
279 def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
281 def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
283 def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
285 def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
287 def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
289 def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
292 /// Load and Store Instructions - aligned
293 let DecoderMethod = "DecodeMemMMImm16" in {
294 def LB_MM : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>;
295 def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>;
296 def LH_MM : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>;
297 def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>;
298 def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
299 def SB_MM : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>;
300 def SH_MM : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>;
301 def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
304 def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU>, LL_FM_MM<0xe>;
306 /// Load and Store Instructions - unaligned
307 def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
309 def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
311 def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
313 def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
317 def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
318 NoItinerary>, ADD_FM_MM<0, 0x58>;
319 def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
320 NoItinerary>, ADD_FM_MM<0, 0x18>;
321 def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT>,
322 CMov_F_I_FM_MM<0x25>;
323 def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF>,
326 /// Move to/from HI/LO
327 def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
329 def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
331 def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
333 def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
336 /// Multiply Add/Sub Instructions
337 def MADD_MM : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>;
338 def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>;
339 def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>;
340 def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>;
343 def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>,
345 def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>,
348 /// Sign Ext In Register Instructions.
349 def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
350 SEB_FM_MM<0x0ac>, ISA_MIPS32R2;
351 def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
352 SEB_FM_MM<0x0ec>, ISA_MIPS32R2;
354 /// Word Swap Bytes Within Halfwords
355 def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM_MM<0x1ec>,
358 def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>,
360 def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>,
363 /// Jump Instructions
364 let DecoderMethod = "DecodeJumpTargetMM" in {
365 def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
367 def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>;
369 def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>;
370 def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
372 /// Jump Instructions - Short Delay Slot
373 def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>;
374 def JALRS_MM : JumpLinkRegMM<"jalrs", GPR32Opnd>, JALR_FM_MM<0x13c>;
376 /// Branch Instructions
377 def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
379 def BNE_MM : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
381 def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
383 def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,
385 def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
387 def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
389 def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,
391 def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
394 /// Branch Instructions - Short Delay Slot
395 def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm,
396 GPR32Opnd>, BGEZAL_FM_MM<0x13>;
397 def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm,
398 GPR32Opnd>, BGEZAL_FM_MM<0x11>;
400 /// Control Instructions
401 def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM;
402 def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM;
403 def SYSCALL_MM : MMRel, SYS_FT<"syscall">, SYS_FM_MM;
404 def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM;
405 def ERET_MM : MMRel, ER_FT<"eret">, ER_FM_MM<0x3cd>;
406 def DERET_MM : MMRel, ER_FT<"deret">, ER_FM_MM<0x38d>;
407 def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>,
409 def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>,
412 /// Trap Instructions
413 def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM_MM<0x0>;
414 def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM_MM<0x08>;
415 def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM_MM<0x10>;
416 def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM_MM<0x20>;
417 def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM_MM<0x28>;
418 def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM_MM<0x30>;
420 def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM_MM<0x0e>;
421 def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM_MM<0x09>;
422 def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM_MM<0x0b>;
423 def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM_MM<0x08>;
424 def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM_MM<0x0a>;
425 def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM_MM<0x0c>;
427 /// Load-linked, Store-conditional
428 def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
429 def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
431 def TLBP_MM : MMRel, TLB<"tlbp">, COP0_TLB_FM_MM<0x0d>;
432 def TLBR_MM : MMRel, TLB<"tlbr">, COP0_TLB_FM_MM<0x4d>;
433 def TLBWI_MM : MMRel, TLB<"tlbwi">, COP0_TLB_FM_MM<0x8d>;
434 def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>;
437 //===----------------------------------------------------------------------===//
438 // MicroMips instruction aliases
439 //===----------------------------------------------------------------------===//
441 let Predicates = [InMicroMips] in {
442 def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;