1 def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
3 def simm4 : Operand<i32> {
4 let DecoderMethod = "DecodeSimm4";
6 def li_simm7 : Operand<i32> {
7 let DecoderMethod = "DecodeLiSimm7";
10 def simm12 : Operand<i32> {
11 let DecoderMethod = "DecodeSimm12";
14 def uimm5_lsl2 : Operand<OtherVT> {
15 let EncoderMethod = "getUImm5Lsl2Encoding";
18 def uimm6_lsl2 : Operand<i32> {
19 let EncoderMethod = "getUImm6Lsl2Encoding";
20 let DecoderMethod = "DecodeUImm6Lsl2";
23 def simm9_addiusp : Operand<i32> {
24 let EncoderMethod = "getSImm9AddiuspValue";
27 def uimm3_shift : Operand<i32> {
28 let EncoderMethod = "getUImm3Mod8Encoding";
31 def simm3_lsa2 : Operand<i32> {
32 let EncoderMethod = "getSImm3Lsa2Value";
33 let DecoderMethod = "DecodeAddiur2Simm7";
36 def uimm4_andi : Operand<i32> {
37 let EncoderMethod = "getUImm4AndValue";
40 def immSExtAddiur2 : ImmLeaf<i32, [{return Imm == 1 || Imm == -1 ||
42 Imm < 28 && Imm > 0);}]>;
44 def immSExtAddius5 : ImmLeaf<i32, [{return Imm >= -8 && Imm <= 7;}]>;
46 def immZExtAndi16 : ImmLeaf<i32,
47 [{return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
48 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
49 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );}]>;
51 def immZExt2Shift : ImmLeaf<i32, [{return Imm >= 1 && Imm <= 8;}]>;
53 def immLi16 : ImmLeaf<i32, [{return Imm >= -1 && Imm <= 126;}]>;
55 def MicroMipsMemGPRMM16AsmOperand : AsmOperandClass {
56 let Name = "MicroMipsMem";
57 let RenderMethod = "addMicroMipsMemOperands";
58 let ParserMethod = "parseMemOperand";
59 let PredicateMethod = "isMemWithGRPMM16Base";
62 class mem_mm_4_generic : Operand<i32> {
63 let PrintMethod = "printMemOperand";
64 let MIOperandInfo = (ops ptr_rc, simm4);
65 let OperandType = "OPERAND_MEMORY";
66 let ParserMatchClass = MicroMipsMemGPRMM16AsmOperand;
69 def mem_mm_4 : mem_mm_4_generic {
70 let EncoderMethod = "getMemEncodingMMImm4";
73 def mem_mm_4_lsl1 : mem_mm_4_generic {
74 let EncoderMethod = "getMemEncodingMMImm4Lsl1";
77 def mem_mm_4_lsl2 : mem_mm_4_generic {
78 let EncoderMethod = "getMemEncodingMMImm4Lsl2";
81 def mem_mm_12 : Operand<i32> {
82 let PrintMethod = "printMemOperand";
83 let MIOperandInfo = (ops GPR32, simm12);
84 let EncoderMethod = "getMemEncodingMMImm12";
85 let ParserMatchClass = MipsMemAsmOperand;
86 let OperandType = "OPERAND_MEMORY";
89 def MipsMemUimm4AsmOperand : AsmOperandClass {
90 let Name = "MemOffsetUimm4";
91 let SuperClasses = [MipsMemAsmOperand];
92 let RenderMethod = "addMemOperands";
93 let ParserMethod = "parseMemOperand";
94 let PredicateMethod = "isMemWithUimmOffsetSP<6>";
97 def mem_mm_4sp : Operand<i32> {
98 let PrintMethod = "printMemOperand";
99 let MIOperandInfo = (ops GPR32, uimm8);
100 let EncoderMethod = "getMemEncodingMMImm4sp";
101 let ParserMatchClass = MipsMemUimm4AsmOperand;
102 let OperandType = "OPERAND_MEMORY";
105 def jmptarget_mm : Operand<OtherVT> {
106 let EncoderMethod = "getJumpTargetOpValueMM";
109 def calltarget_mm : Operand<iPTR> {
110 let EncoderMethod = "getJumpTargetOpValueMM";
113 def brtarget_mm : Operand<OtherVT> {
114 let EncoderMethod = "getBranchTargetOpValueMM";
115 let OperandType = "OPERAND_PCREL";
116 let DecoderMethod = "DecodeBranchTargetMM";
119 class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,
120 RegisterOperand RO> :
121 InstSE<(outs), (ins RO:$rs, opnd:$offset),
122 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI> {
124 let isTerminator = 1;
125 let hasDelaySlot = 0;
129 let canFoldAsLoad = 1 in
130 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
132 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
133 !strconcat(opstr, "\t$rt, $addr"),
134 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
136 let DecoderMethod = "DecodeMemMMImm12";
137 string Constraints = "$src = $rt";
140 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
142 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
143 !strconcat(opstr, "\t$rt, $addr"),
144 [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
145 let DecoderMethod = "DecodeMemMMImm12";
148 class LLBaseMM<string opstr, RegisterOperand RO> :
149 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
150 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
151 let DecoderMethod = "DecodeMemMMImm12";
155 class SCBaseMM<string opstr, RegisterOperand RO> :
156 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
157 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
158 let DecoderMethod = "DecodeMemMMImm12";
160 let Constraints = "$rt = $dst";
163 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
164 InstrItinClass Itin = NoItinerary> :
165 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
166 !strconcat(opstr, "\t$rt, $addr"),
167 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
168 let DecoderMethod = "DecodeMemMMImm12";
169 let canFoldAsLoad = 1;
173 class ArithRMM16<string opstr, RegisterOperand RO, bit isComm = 0,
174 InstrItinClass Itin = NoItinerary,
175 SDPatternOperator OpNode = null_frag> :
176 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt),
177 !strconcat(opstr, "\t$rd, $rs, $rt"),
178 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
179 let isCommutable = isComm;
182 class AndImmMM16<string opstr, RegisterOperand RO,
183 InstrItinClass Itin = NoItinerary> :
184 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, uimm4_andi:$imm),
185 !strconcat(opstr, "\t$rd, $rs, $imm"), [], Itin, FrmI>;
187 class LogicRMM16<string opstr, RegisterOperand RO,
188 InstrItinClass Itin = NoItinerary,
189 SDPatternOperator OpNode = null_frag> :
190 MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),
191 !strconcat(opstr, "\t$rt, $rs"),
192 [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
193 let isCommutable = 1;
194 let Constraints = "$rt = $dst";
197 class NotMM16<string opstr, RegisterOperand RO> :
198 MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),
199 !strconcat(opstr, "\t$rt, $rs"),
200 [(set RO:$rt, (not RO:$rs))], NoItinerary, FrmR>;
202 class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO,
203 InstrItinClass Itin = NoItinerary> :
204 MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
205 !strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>;
207 class LoadMM16<string opstr, DAGOperand RO, SDPatternOperator OpNode,
208 InstrItinClass Itin, Operand MemOpnd> :
209 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$addr),
210 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
211 let DecoderMethod = "DecodeMemMMImm4";
212 let canFoldAsLoad = 1;
216 class StoreMM16<string opstr, DAGOperand RTOpnd, DAGOperand RO,
217 SDPatternOperator OpNode, InstrItinClass Itin,
219 MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
220 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
221 let DecoderMethod = "DecodeMemMMImm4";
225 class AddImmUR2<string opstr, RegisterOperand RO> :
226 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm),
227 !strconcat(opstr, "\t$rd, $rs, $imm"),
228 [], NoItinerary, FrmR> {
229 let isCommutable = 1;
232 class AddImmUS5<string opstr, RegisterOperand RO> :
233 MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
234 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> {
235 let Constraints = "$rd = $dst";
238 class AddImmUR1SP<string opstr, RegisterOperand RO> :
239 MicroMipsInst16<(outs RO:$rd), (ins uimm6_lsl2:$imm),
240 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR>;
242 class AddImmUSP<string opstr> :
243 MicroMipsInst16<(outs), (ins simm9_addiusp:$imm),
244 !strconcat(opstr, "\t$imm"), [], NoItinerary, FrmI>;
246 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
247 MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
248 [], II_MFHI_MFLO, FrmR> {
250 let hasSideEffects = 0;
253 class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
254 InstrItinClass Itin = NoItinerary> :
255 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
256 !strconcat(opstr, "\t$rd, $rs"), [], Itin, FrmR> {
257 let isCommutable = isComm;
258 let isReMaterializable = 1;
261 class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO,
262 SDPatternOperator imm_type = null_frag> :
263 MicroMipsInst16<(outs RO:$rd), (ins Od:$imm),
264 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmI> {
265 let isReMaterializable = 1;
268 // 16-bit Jump and Link (Call)
269 class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
270 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
271 [(MipsJmpLink RO:$rs)], IIBranch, FrmR> {
273 let hasDelaySlot = 1;
278 class JumpRegMM16<string opstr, RegisterOperand RO> :
279 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
280 [], IIBranch, FrmR> {
281 let hasDelaySlot = 1;
283 let isIndirectBranch = 1;
286 // Base class for JRADDIUSP instruction.
287 class JumpRAddiuStackMM16 :
288 MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jraddiusp\t$imm",
289 [], IIBranch, FrmR> {
290 let isTerminator = 1;
293 let isIndirectBranch = 1;
296 // 16-bit Jump and Link (Call) - Short Delay Slot
297 class JumpLinkRegSMM16<string opstr, RegisterOperand RO> :
298 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
299 [], IIBranch, FrmR> {
301 let hasDelaySlot = 1;
305 // 16-bit Jump Register Compact - No delay slot
306 class JumpRegCMM16<string opstr, RegisterOperand RO> :
307 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
308 [], IIBranch, FrmR> {
309 let isTerminator = 1;
312 let isIndirectBranch = 1;
315 // Break16 and Sdbbp16
316 class BrkSdbbp16MM<string opstr> :
317 MicroMipsInst16<(outs), (ins uimm4:$code_),
318 !strconcat(opstr, "\t$code_"),
319 [], NoItinerary, FrmOther>;
321 // MicroMIPS Jump and Link (Call) - Short Delay Slot
322 let isCall = 1, hasDelaySlot = 1, Defs = [RA] in {
323 class JumpLinkMM<string opstr, DAGOperand opnd> :
324 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
325 [], IIBranch, FrmJ, opstr> {
326 let DecoderMethod = "DecodeJumpTargetMM";
329 class JumpLinkRegMM<string opstr, RegisterOperand RO>:
330 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
333 class BranchCompareToZeroLinkMM<string opstr, DAGOperand opnd,
334 RegisterOperand RO> :
335 InstSE<(outs), (ins RO:$rs, opnd:$offset),
336 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
339 class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO,
340 InstrItinClass Itin = NoItinerary,
341 SDPatternOperator OpNode = null_frag> :
342 InstSE<(outs RO:$rd), (ins PtrRC:$base, PtrRC:$index),
343 !strconcat(opstr, "\t$rd, ${index}(${base})"), [], Itin, FrmFI>;
345 /// A list of registers used by load/store multiple instructions.
346 def RegListAsmOperand : AsmOperandClass {
347 let Name = "RegList";
348 let ParserMethod = "parseRegisterList";
351 def reglist : Operand<i32> {
352 let EncoderMethod = "getRegisterListOpValue";
353 let ParserMatchClass = RegListAsmOperand;
354 let PrintMethod = "printRegisterList";
355 let DecoderMethod = "DecodeRegListOperand";
358 def RegList16AsmOperand : AsmOperandClass {
359 let Name = "RegList16";
360 let ParserMethod = "parseRegisterList";
361 let PredicateMethod = "isRegList16";
362 let RenderMethod = "addRegListOperands";
365 def reglist16 : Operand<i32> {
366 let EncoderMethod = "getRegisterListOpValue16";
367 let DecoderMethod = "DecodeRegListOperand16";
368 let PrintMethod = "printRegisterList";
369 let ParserMatchClass = RegList16AsmOperand;
372 class StoreMultMM<string opstr,
373 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
374 InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr),
375 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
376 let DecoderMethod = "DecodeMemMMImm12";
380 class LoadMultMM<string opstr,
381 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
382 InstSE<(outs reglist:$rt), (ins mem_mm_12:$addr),
383 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
384 let DecoderMethod = "DecodeMemMMImm12";
388 class StoreMultMM16<string opstr,
389 InstrItinClass Itin = NoItinerary,
390 ComplexPattern Addr = addr> :
391 MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
392 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
396 class LoadMultMM16<string opstr,
397 InstrItinClass Itin = NoItinerary,
398 ComplexPattern Addr = addr> :
399 MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
400 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
404 def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
406 def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
408 def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>;
409 def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
411 def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
413 def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
415 def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>;
416 def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
418 def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
420 def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU,
421 mem_mm_4>, LOAD_STORE_FM_MM16<0x02>;
422 def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, zextloadi16, II_LHU,
423 mem_mm_4_lsl1>, LOAD_STORE_FM_MM16<0x0a>;
424 def LW16_MM : LoadMM16<"lw16", GPRMM16Opnd, load, II_LW, mem_mm_4_lsl2>,
425 LOAD_STORE_FM_MM16<0x1a>;
426 def SB16_MM : StoreMM16<"sb16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei8,
427 II_SB, mem_mm_4>, LOAD_STORE_FM_MM16<0x22>;
428 def SH16_MM : StoreMM16<"sh16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei16,
429 II_SH, mem_mm_4_lsl1>,
430 LOAD_STORE_FM_MM16<0x2a>;
431 def SW16_MM : StoreMM16<"sw16", GPRMM16OpndZero, GPRMM16Opnd, store, II_SW,
432 mem_mm_4_lsl2>, LOAD_STORE_FM_MM16<0x3a>;
433 def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16;
434 def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16;
435 def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
436 def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
437 def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
438 def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
439 def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
440 def LI16_MM : LoadImmMM16<"li16", li_simm7, GPRMM16Opnd, immLi16>,
441 LI_FM_MM16, IsAsCheapAsAMove;
442 def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>;
443 def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>;
444 def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
445 def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
446 def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>;
447 def BREAK16_MM : BrkSdbbp16MM<"break16">, BRKSDBBP16_FM_MM<0x28>;
448 def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16">, BRKSDBBP16_FM_MM<0x2C>;
450 class WaitMM<string opstr> :
451 InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
452 NoItinerary, FrmOther, opstr>;
454 let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
455 /// Compact Branch Instructions
456 def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>,
457 COMPACT_BRANCH_FM_MM<0x7>;
458 def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>,
459 COMPACT_BRANCH_FM_MM<0x5>;
461 /// Arithmetic Instructions (ALU Immediate)
462 def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
464 def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
466 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
468 def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
470 def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
472 def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
474 def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
476 def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM;
478 def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
481 /// Arithmetic Instructions (3-Operand, R-Type)
482 def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd>, ADD_FM_MM<0, 0x150>;
483 def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd>, ADD_FM_MM<0, 0x1d0>;
484 def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
485 def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
486 def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
487 def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
488 def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
490 def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
492 def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
494 def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
496 def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
497 def MULT_MM : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
499 def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
501 def SDIV_MM : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
503 def UDIV_MM : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
506 /// Shift Instructions
507 def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
509 def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
511 def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
513 def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
515 def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
517 def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
519 def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
521 def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
524 /// Load and Store Instructions - aligned
525 let DecoderMethod = "DecodeMemMMImm16" in {
526 def LB_MM : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>;
527 def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>;
528 def LH_MM : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>;
529 def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>;
530 def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
531 def SB_MM : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>;
532 def SH_MM : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>;
533 def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
536 def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>;
538 def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU>, LL_FM_MM<0xe>;
540 /// Load and Store Instructions - unaligned
541 def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
543 def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
545 def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
547 def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
550 /// Load and Store Instructions - multiple
551 def SWM32_MM : StoreMultMM<"swm32">, LWM_FM_MM<0xd>;
552 def LWM32_MM : LoadMultMM<"lwm32">, LWM_FM_MM<0x5>;
553 def SWM16_MM : StoreMultMM16<"swm16">, LWM_FM_MM16<0x5>;
554 def LWM16_MM : LoadMultMM16<"lwm16">, LWM_FM_MM16<0x4>;
557 def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
558 NoItinerary>, ADD_FM_MM<0, 0x58>;
559 def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
560 NoItinerary>, ADD_FM_MM<0, 0x18>;
561 def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT>,
562 CMov_F_I_FM_MM<0x25>;
563 def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF>,
566 /// Move to/from HI/LO
567 def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
569 def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
571 def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
573 def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
576 /// Multiply Add/Sub Instructions
577 def MADD_MM : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>;
578 def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>;
579 def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>;
580 def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>;
583 def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>,
585 def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>,
588 /// Sign Ext In Register Instructions.
589 def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
590 SEB_FM_MM<0x0ac>, ISA_MIPS32R2;
591 def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
592 SEB_FM_MM<0x0ec>, ISA_MIPS32R2;
594 /// Word Swap Bytes Within Halfwords
595 def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM_MM<0x1ec>,
598 def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>,
600 def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>,
603 /// Jump Instructions
604 let DecoderMethod = "DecodeJumpTargetMM" in {
605 def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
607 def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>;
609 def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>;
610 def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
612 /// Jump Instructions - Short Delay Slot
613 def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>;
614 def JALRS_MM : JumpLinkRegMM<"jalrs", GPR32Opnd>, JALR_FM_MM<0x13c>;
616 /// Branch Instructions
617 def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
619 def BNE_MM : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
621 def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
623 def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,
625 def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
627 def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
629 def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,
631 def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
634 /// Branch Instructions - Short Delay Slot
635 def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm,
636 GPR32Opnd>, BGEZAL_FM_MM<0x13>;
637 def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm,
638 GPR32Opnd>, BGEZAL_FM_MM<0x11>;
640 /// Control Instructions
641 def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM;
642 def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM;
643 def SYSCALL_MM : MMRel, SYS_FT<"syscall">, SYS_FM_MM;
644 def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM;
645 def ERET_MM : MMRel, ER_FT<"eret">, ER_FM_MM<0x3cd>;
646 def DERET_MM : MMRel, ER_FT<"deret">, ER_FM_MM<0x38d>;
647 def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>,
649 def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>,
652 /// Trap Instructions
653 def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM_MM<0x0>;
654 def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM_MM<0x08>;
655 def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM_MM<0x10>;
656 def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM_MM<0x20>;
657 def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM_MM<0x28>;
658 def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM_MM<0x30>;
660 def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM_MM<0x0e>;
661 def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM_MM<0x09>;
662 def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM_MM<0x0b>;
663 def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM_MM<0x08>;
664 def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM_MM<0x0a>;
665 def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM_MM<0x0c>;
667 /// Load-linked, Store-conditional
668 def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
669 def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
671 def TLBP_MM : MMRel, TLB<"tlbp">, COP0_TLB_FM_MM<0x0d>;
672 def TLBR_MM : MMRel, TLB<"tlbr">, COP0_TLB_FM_MM<0x4d>;
673 def TLBWI_MM : MMRel, TLB<"tlbwi">, COP0_TLB_FM_MM<0x8d>;
674 def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>;
676 def SDBBP_MM : MMRel, SYS_FT<"sdbbp">, SDBBP_FM_MM;
677 def RDHWR_MM : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM_MM;
680 let Predicates = [InMicroMips] in {
682 //===----------------------------------------------------------------------===//
683 // MicroMips arbitrary patterns that map to one or more instructions
684 //===----------------------------------------------------------------------===//
686 def : MipsPat<(add GPRMM16:$src, immSExtAddiur2:$imm),
687 (ADDIUR2_MM GPRMM16:$src, immSExtAddiur2:$imm)>;
688 def : MipsPat<(add GPR32:$src, immSExtAddius5:$imm),
689 (ADDIUS5_MM GPR32:$src, immSExtAddius5:$imm)>;
690 def : MipsPat<(add GPR32:$src, immSExt16:$imm),
691 (ADDiu_MM GPR32:$src, immSExt16:$imm)>;
693 def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
694 (ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>;
695 def : MipsPat<(and GPR32:$src, immZExt16:$imm),
696 (ANDi_MM GPR32:$src, immZExt16:$imm)>;
698 def : MipsPat<(shl GPRMM16:$src, immZExt2Shift:$imm),
699 (SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
700 def : MipsPat<(shl GPR32:$src, immZExt5:$imm),
701 (SLL_MM GPR32:$src, immZExt5:$imm)>;
703 def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm),
704 (SRL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
705 def : MipsPat<(srl GPR32:$src, immZExt5:$imm),
706 (SRL_MM GPR32:$src, immZExt5:$imm)>;
708 //===----------------------------------------------------------------------===//
709 // MicroMips instruction aliases
710 //===----------------------------------------------------------------------===//
712 def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;