1 def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
3 def simm12 : Operand<i32> {
4 let DecoderMethod = "DecodeSimm12";
7 def uimm5_lsl2 : Operand<OtherVT> {
8 let EncoderMethod = "getUImm5Lsl2Encoding";
11 def mem_mm_12 : Operand<i32> {
12 let PrintMethod = "printMemOperand";
13 let MIOperandInfo = (ops GPR32, simm12);
14 let EncoderMethod = "getMemEncodingMMImm12";
15 let ParserMatchClass = MipsMemAsmOperand;
16 let OperandType = "OPERAND_MEMORY";
19 def jmptarget_mm : Operand<OtherVT> {
20 let EncoderMethod = "getJumpTargetOpValueMM";
23 def calltarget_mm : Operand<iPTR> {
24 let EncoderMethod = "getJumpTargetOpValueMM";
27 def brtarget_mm : Operand<OtherVT> {
28 let EncoderMethod = "getBranchTargetOpValueMM";
29 let OperandType = "OPERAND_PCREL";
30 let DecoderMethod = "DecodeBranchTargetMM";
33 class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,
35 InstSE<(outs), (ins RO:$rs, opnd:$offset),
36 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI> {
43 let canFoldAsLoad = 1 in
44 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
46 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
47 !strconcat(opstr, "\t$rt, $addr"),
48 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
50 let DecoderMethod = "DecodeMemMMImm12";
51 string Constraints = "$src = $rt";
54 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
56 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
57 !strconcat(opstr, "\t$rt, $addr"),
58 [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
59 let DecoderMethod = "DecodeMemMMImm12";
62 class LLBaseMM<string opstr, RegisterOperand RO> :
63 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
64 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
65 let DecoderMethod = "DecodeMemMMImm12";
69 class SCBaseMM<string opstr, RegisterOperand RO> :
70 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
71 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
72 let DecoderMethod = "DecodeMemMMImm12";
74 let Constraints = "$rt = $dst";
77 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
78 InstrItinClass Itin = NoItinerary> :
79 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
80 !strconcat(opstr, "\t$rt, $addr"),
81 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
82 let DecoderMethod = "DecodeMemMMImm12";
83 let canFoldAsLoad = 1;
87 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
88 MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
89 [], II_MFHI_MFLO, FrmR> {
91 let hasSideEffects = 0;
94 class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
95 InstrItinClass Itin = NoItinerary> :
96 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
97 !strconcat(opstr, "\t$rd, $rs"), [], Itin, FrmR> {
98 let isCommutable = isComm;
99 let isReMaterializable = 1;
102 // 16-bit Jump and Link (Call)
103 class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
104 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
105 [(MipsJmpLink RO:$rs)], IIBranch, FrmR> {
107 let hasDelaySlot = 1;
111 // Base class for JRADDIUSP instruction.
112 class JumpRAddiuStackMM16 :
113 MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jraddiusp\t$imm",
114 [], IIBranch, FrmR> {
115 let isTerminator = 1;
117 let hasDelaySlot = 1;
119 let isIndirectBranch = 1;
122 // MicroMIPS Jump and Link (Call) - Short Delay Slot
123 let isCall = 1, hasDelaySlot = 1, Defs = [RA] in {
124 class JumpLinkMM<string opstr, DAGOperand opnd> :
125 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
126 [], IIBranch, FrmJ, opstr> {
127 let DecoderMethod = "DecodeJumpTargetMM";
130 class JumpLinkRegMM<string opstr, RegisterOperand RO>:
131 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
134 class BranchCompareToZeroLinkMM<string opstr, DAGOperand opnd,
135 RegisterOperand RO> :
136 InstSE<(outs), (ins RO:$rs, opnd:$offset),
137 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
140 def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
141 def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
142 def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
143 def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>;
144 def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
146 class WaitMM<string opstr> :
147 InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
148 NoItinerary, FrmOther, opstr>;
150 let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
151 /// Compact Branch Instructions
152 def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>,
153 COMPACT_BRANCH_FM_MM<0x7>;
154 def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>,
155 COMPACT_BRANCH_FM_MM<0x5>;
157 /// Arithmetic Instructions (ALU Immediate)
158 def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
160 def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
162 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
164 def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
166 def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
168 def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
170 def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
172 def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM;
174 def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
177 /// Arithmetic Instructions (3-Operand, R-Type)
178 def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd>, ADD_FM_MM<0, 0x150>;
179 def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd>, ADD_FM_MM<0, 0x1d0>;
180 def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
181 def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
182 def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
183 def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
184 def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
186 def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
188 def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
190 def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
192 def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
193 def MULT_MM : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
195 def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
197 def SDIV_MM : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
199 def UDIV_MM : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
202 /// Shift Instructions
203 def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
205 def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
207 def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
209 def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
211 def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
213 def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
215 def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
217 def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
220 /// Load and Store Instructions - aligned
221 let DecoderMethod = "DecodeMemMMImm16" in {
222 def LB_MM : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>;
223 def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>;
224 def LH_MM : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>;
225 def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>;
226 def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
227 def SB_MM : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>;
228 def SH_MM : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>;
229 def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
232 def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU>, LL_FM_MM<0xe>;
234 /// Load and Store Instructions - unaligned
235 def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
237 def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
239 def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
241 def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
245 def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
246 NoItinerary>, ADD_FM_MM<0, 0x58>;
247 def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
248 NoItinerary>, ADD_FM_MM<0, 0x18>;
249 def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT>,
250 CMov_F_I_FM_MM<0x25>;
251 def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF>,
254 /// Move to/from HI/LO
255 def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
257 def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
259 def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
261 def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
264 /// Multiply Add/Sub Instructions
265 def MADD_MM : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>;
266 def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>;
267 def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>;
268 def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>;
271 def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>,
273 def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>,
276 /// Sign Ext In Register Instructions.
277 def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
278 SEB_FM_MM<0x0ac>, ISA_MIPS32R2;
279 def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
280 SEB_FM_MM<0x0ec>, ISA_MIPS32R2;
282 /// Word Swap Bytes Within Halfwords
283 def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM_MM<0x1ec>,
286 def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>,
288 def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>,
291 /// Jump Instructions
292 let DecoderMethod = "DecodeJumpTargetMM" in {
293 def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
295 def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>;
297 def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>;
298 def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
300 /// Jump Instructions - Short Delay Slot
301 def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>;
302 def JALRS_MM : JumpLinkRegMM<"jalrs", GPR32Opnd>, JALR_FM_MM<0x13c>;
304 /// Branch Instructions
305 def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
307 def BNE_MM : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
309 def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
311 def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,
313 def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
315 def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
317 def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,
319 def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
322 /// Branch Instructions - Short Delay Slot
323 def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm,
324 GPR32Opnd>, BGEZAL_FM_MM<0x13>;
325 def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm,
326 GPR32Opnd>, BGEZAL_FM_MM<0x11>;
328 /// Control Instructions
329 def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM;
330 def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM;
331 def SYSCALL_MM : MMRel, SYS_FT<"syscall">, SYS_FM_MM;
332 def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM;
333 def ERET_MM : MMRel, ER_FT<"eret">, ER_FM_MM<0x3cd>;
334 def DERET_MM : MMRel, ER_FT<"deret">, ER_FM_MM<0x38d>;
335 def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>,
337 def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>,
340 /// Trap Instructions
341 def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM_MM<0x0>;
342 def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM_MM<0x08>;
343 def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM_MM<0x10>;
344 def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM_MM<0x20>;
345 def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM_MM<0x28>;
346 def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM_MM<0x30>;
348 def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM_MM<0x0e>;
349 def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM_MM<0x09>;
350 def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM_MM<0x0b>;
351 def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM_MM<0x08>;
352 def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM_MM<0x0a>;
353 def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM_MM<0x0c>;
355 /// Load-linked, Store-conditional
356 def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
357 def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
359 def TLBP_MM : MMRel, TLB<"tlbp">, COP0_TLB_FM_MM<0x0d>;
360 def TLBR_MM : MMRel, TLB<"tlbr">, COP0_TLB_FM_MM<0x4d>;
361 def TLBWI_MM : MMRel, TLB<"tlbwi">, COP0_TLB_FM_MM<0x8d>;
362 def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>;
365 //===----------------------------------------------------------------------===//
366 // MicroMips instruction aliases
367 //===----------------------------------------------------------------------===//
369 let Predicates = [InMicroMips] in {
370 def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;