1 def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
3 def simm4 : Operand<i32> {
4 let DecoderMethod = "DecodeSimm4";
6 def li_simm7 : Operand<i32> {
7 let DecoderMethod = "DecodeLiSimm7";
10 def simm12 : Operand<i32> {
11 let DecoderMethod = "DecodeSimm12";
14 def uimm5_lsl2 : Operand<OtherVT> {
15 let EncoderMethod = "getUImm5Lsl2Encoding";
18 def uimm6_lsl2 : Operand<i32> {
19 let EncoderMethod = "getUImm6Lsl2Encoding";
20 let DecoderMethod = "DecodeUImm6Lsl2";
23 def simm9_addiusp : Operand<i32> {
24 let EncoderMethod = "getSImm9AddiuspValue";
27 def uimm3_shift : Operand<i32> {
28 let EncoderMethod = "getUImm3Mod8Encoding";
31 def simm3_lsa2 : Operand<i32> {
32 let EncoderMethod = "getSImm3Lsa2Value";
33 let DecoderMethod = "DecodeAddiur2Simm7";
36 def uimm4_andi : Operand<i32> {
37 let EncoderMethod = "getUImm4AndValue";
40 def immSExtAddiur2 : ImmLeaf<i32, [{return Imm == 1 || Imm == -1 ||
42 Imm < 28 && Imm > 0);}]>;
44 def immSExtAddius5 : ImmLeaf<i32, [{return Imm >= -8 && Imm <= 7;}]>;
46 def immZExtAndi16 : ImmLeaf<i32,
47 [{return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
48 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
49 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );}]>;
51 def immZExt2Shift : ImmLeaf<i32, [{return Imm >= 1 && Imm <= 8;}]>;
53 def immLi16 : ImmLeaf<i32, [{return Imm >= -1 && Imm <= 126;}]>;
55 def MicroMipsMemGPRMM16AsmOperand : AsmOperandClass {
56 let Name = "MicroMipsMem";
57 let RenderMethod = "addMicroMipsMemOperands";
58 let ParserMethod = "parseMemOperand";
59 let PredicateMethod = "isMemWithGRPMM16Base";
62 class mem_mm_4_generic : Operand<i32> {
63 let PrintMethod = "printMemOperand";
64 let MIOperandInfo = (ops ptr_rc, simm4);
65 let OperandType = "OPERAND_MEMORY";
66 let ParserMatchClass = MicroMipsMemGPRMM16AsmOperand;
69 def mem_mm_4 : mem_mm_4_generic {
70 let EncoderMethod = "getMemEncodingMMImm4";
73 def mem_mm_4_lsl1 : mem_mm_4_generic {
74 let EncoderMethod = "getMemEncodingMMImm4Lsl1";
77 def mem_mm_4_lsl2 : mem_mm_4_generic {
78 let EncoderMethod = "getMemEncodingMMImm4Lsl2";
81 def mem_mm_12 : Operand<i32> {
82 let PrintMethod = "printMemOperand";
83 let MIOperandInfo = (ops GPR32, simm12);
84 let EncoderMethod = "getMemEncodingMMImm12";
85 let ParserMatchClass = MipsMemAsmOperand;
86 let OperandType = "OPERAND_MEMORY";
89 def jmptarget_mm : Operand<OtherVT> {
90 let EncoderMethod = "getJumpTargetOpValueMM";
93 def calltarget_mm : Operand<iPTR> {
94 let EncoderMethod = "getJumpTargetOpValueMM";
97 def brtarget_mm : Operand<OtherVT> {
98 let EncoderMethod = "getBranchTargetOpValueMM";
99 let OperandType = "OPERAND_PCREL";
100 let DecoderMethod = "DecodeBranchTargetMM";
103 class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,
104 RegisterOperand RO> :
105 InstSE<(outs), (ins RO:$rs, opnd:$offset),
106 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI> {
108 let isTerminator = 1;
109 let hasDelaySlot = 0;
113 let canFoldAsLoad = 1 in
114 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
116 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
117 !strconcat(opstr, "\t$rt, $addr"),
118 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
120 let DecoderMethod = "DecodeMemMMImm12";
121 string Constraints = "$src = $rt";
124 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
126 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
127 !strconcat(opstr, "\t$rt, $addr"),
128 [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
129 let DecoderMethod = "DecodeMemMMImm12";
132 class LLBaseMM<string opstr, RegisterOperand RO> :
133 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
134 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
135 let DecoderMethod = "DecodeMemMMImm12";
139 class SCBaseMM<string opstr, RegisterOperand RO> :
140 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
141 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
142 let DecoderMethod = "DecodeMemMMImm12";
144 let Constraints = "$rt = $dst";
147 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
148 InstrItinClass Itin = NoItinerary> :
149 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
150 !strconcat(opstr, "\t$rt, $addr"),
151 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
152 let DecoderMethod = "DecodeMemMMImm12";
153 let canFoldAsLoad = 1;
157 class ArithRMM16<string opstr, RegisterOperand RO, bit isComm = 0,
158 InstrItinClass Itin = NoItinerary,
159 SDPatternOperator OpNode = null_frag> :
160 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt),
161 !strconcat(opstr, "\t$rd, $rs, $rt"),
162 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
163 let isCommutable = isComm;
166 class AndImmMM16<string opstr, RegisterOperand RO,
167 InstrItinClass Itin = NoItinerary> :
168 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, uimm4_andi:$imm),
169 !strconcat(opstr, "\t$rd, $rs, $imm"), [], Itin, FrmI>;
171 class LogicRMM16<string opstr, RegisterOperand RO,
172 InstrItinClass Itin = NoItinerary,
173 SDPatternOperator OpNode = null_frag> :
174 MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),
175 !strconcat(opstr, "\t$rt, $rs"),
176 [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
177 let isCommutable = 1;
178 let Constraints = "$rt = $dst";
181 class NotMM16<string opstr, RegisterOperand RO> :
182 MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),
183 !strconcat(opstr, "\t$rt, $rs"),
184 [(set RO:$rt, (not RO:$rs))], NoItinerary, FrmR>;
186 class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO,
187 InstrItinClass Itin = NoItinerary> :
188 MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
189 !strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>;
191 class LoadMM16<string opstr, DAGOperand RO, SDPatternOperator OpNode,
192 InstrItinClass Itin, Operand MemOpnd> :
193 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$addr),
194 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
195 let DecoderMethod = "DecodeMemMMImm4";
196 let canFoldAsLoad = 1;
200 class StoreMM16<string opstr, DAGOperand RTOpnd, DAGOperand RO,
201 SDPatternOperator OpNode, InstrItinClass Itin,
203 MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
204 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
205 let DecoderMethod = "DecodeMemMMImm4";
209 class AddImmUR2<string opstr, RegisterOperand RO> :
210 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm),
211 !strconcat(opstr, "\t$rd, $rs, $imm"),
212 [], NoItinerary, FrmR> {
213 let isCommutable = 1;
216 class AddImmUS5<string opstr, RegisterOperand RO> :
217 MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
218 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> {
219 let Constraints = "$rd = $dst";
222 class AddImmUR1SP<string opstr, RegisterOperand RO> :
223 MicroMipsInst16<(outs RO:$rd), (ins uimm6_lsl2:$imm),
224 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR>;
226 class AddImmUSP<string opstr> :
227 MicroMipsInst16<(outs), (ins simm9_addiusp:$imm),
228 !strconcat(opstr, "\t$imm"), [], NoItinerary, FrmI>;
230 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
231 MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
232 [], II_MFHI_MFLO, FrmR> {
234 let hasSideEffects = 0;
237 class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
238 InstrItinClass Itin = NoItinerary> :
239 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
240 !strconcat(opstr, "\t$rd, $rs"), [], Itin, FrmR> {
241 let isCommutable = isComm;
242 let isReMaterializable = 1;
245 class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO,
246 SDPatternOperator imm_type = null_frag> :
247 MicroMipsInst16<(outs RO:$rd), (ins Od:$imm),
248 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmI> {
249 let isReMaterializable = 1;
252 // 16-bit Jump and Link (Call)
253 class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
254 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
255 [(MipsJmpLink RO:$rs)], IIBranch, FrmR> {
257 let hasDelaySlot = 1;
262 class JumpRegMM16<string opstr, RegisterOperand RO> :
263 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
264 [], IIBranch, FrmR> {
265 let hasDelaySlot = 1;
267 let isIndirectBranch = 1;
270 // Base class for JRADDIUSP instruction.
271 class JumpRAddiuStackMM16 :
272 MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jraddiusp\t$imm",
273 [], IIBranch, FrmR> {
274 let isTerminator = 1;
277 let isIndirectBranch = 1;
280 // 16-bit Jump and Link (Call) - Short Delay Slot
281 class JumpLinkRegSMM16<string opstr, RegisterOperand RO> :
282 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
283 [], IIBranch, FrmR> {
285 let hasDelaySlot = 1;
289 // 16-bit Jump Register Compact - No delay slot
290 class JumpRegCMM16<string opstr, RegisterOperand RO> :
291 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
292 [], IIBranch, FrmR> {
293 let isTerminator = 1;
296 let isIndirectBranch = 1;
299 // Break16 and Sdbbp16
300 class BrkSdbbp16MM<string opstr> :
301 MicroMipsInst16<(outs), (ins uimm4:$code_),
302 !strconcat(opstr, "\t$code_"),
303 [], NoItinerary, FrmOther>;
305 // MicroMIPS Jump and Link (Call) - Short Delay Slot
306 let isCall = 1, hasDelaySlot = 1, Defs = [RA] in {
307 class JumpLinkMM<string opstr, DAGOperand opnd> :
308 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
309 [], IIBranch, FrmJ, opstr> {
310 let DecoderMethod = "DecodeJumpTargetMM";
313 class JumpLinkRegMM<string opstr, RegisterOperand RO>:
314 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
317 class BranchCompareToZeroLinkMM<string opstr, DAGOperand opnd,
318 RegisterOperand RO> :
319 InstSE<(outs), (ins RO:$rs, opnd:$offset),
320 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
323 class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO,
324 InstrItinClass Itin = NoItinerary,
325 SDPatternOperator OpNode = null_frag> :
326 InstSE<(outs RO:$rd), (ins PtrRC:$base, PtrRC:$index),
327 !strconcat(opstr, "\t$rd, ${index}(${base})"), [], Itin, FrmFI>;
329 /// A list of registers used by load/store multiple instructions.
330 def RegListAsmOperand : AsmOperandClass {
331 let Name = "RegList";
332 let ParserMethod = "parseRegisterList";
335 def reglist : Operand<i32> {
336 let EncoderMethod = "getRegisterListOpValue";
337 let ParserMatchClass = RegListAsmOperand;
338 let PrintMethod = "printRegisterList";
339 let DecoderMethod = "DecodeRegListOperand";
342 class StoreMultMM<string opstr,
343 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
344 InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr),
345 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
346 let DecoderMethod = "DecodeMemMMImm12";
350 class LoadMultMM<string opstr,
351 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
352 InstSE<(outs reglist:$rt), (ins mem_mm_12:$addr),
353 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
354 let DecoderMethod = "DecodeMemMMImm12";
358 def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
360 def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
362 def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>;
363 def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
365 def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
367 def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
369 def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>;
370 def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
372 def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
374 def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU,
375 mem_mm_4>, LOAD_STORE_FM_MM16<0x02>;
376 def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, zextloadi16, II_LHU,
377 mem_mm_4_lsl1>, LOAD_STORE_FM_MM16<0x0a>;
378 def LW16_MM : LoadMM16<"lw16", GPRMM16Opnd, load, II_LW, mem_mm_4_lsl2>,
379 LOAD_STORE_FM_MM16<0x1a>;
380 def SB16_MM : StoreMM16<"sb16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei8,
381 II_SB, mem_mm_4>, LOAD_STORE_FM_MM16<0x22>;
382 def SH16_MM : StoreMM16<"sh16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei16,
383 II_SH, mem_mm_4_lsl1>,
384 LOAD_STORE_FM_MM16<0x2a>;
385 def SW16_MM : StoreMM16<"sw16", GPRMM16OpndZero, GPRMM16Opnd, store, II_SW,
386 mem_mm_4_lsl2>, LOAD_STORE_FM_MM16<0x3a>;
387 def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16;
388 def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16;
389 def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
390 def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
391 def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
392 def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
393 def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
394 def LI16_MM : LoadImmMM16<"li16", li_simm7, GPRMM16Opnd, immLi16>,
395 LI_FM_MM16, IsAsCheapAsAMove;
396 def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>;
397 def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>;
398 def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
399 def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
400 def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>;
401 def BREAK16_MM : BrkSdbbp16MM<"break16">, BRKSDBBP16_FM_MM<0x28>;
402 def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16">, BRKSDBBP16_FM_MM<0x2C>;
404 class WaitMM<string opstr> :
405 InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
406 NoItinerary, FrmOther, opstr>;
408 let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
409 /// Compact Branch Instructions
410 def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>,
411 COMPACT_BRANCH_FM_MM<0x7>;
412 def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>,
413 COMPACT_BRANCH_FM_MM<0x5>;
415 /// Arithmetic Instructions (ALU Immediate)
416 def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
418 def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
420 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
422 def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
424 def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
426 def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
428 def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
430 def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM;
432 def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
435 /// Arithmetic Instructions (3-Operand, R-Type)
436 def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd>, ADD_FM_MM<0, 0x150>;
437 def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd>, ADD_FM_MM<0, 0x1d0>;
438 def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
439 def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
440 def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
441 def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
442 def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
444 def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
446 def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
448 def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
450 def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
451 def MULT_MM : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
453 def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
455 def SDIV_MM : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
457 def UDIV_MM : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
460 /// Shift Instructions
461 def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
463 def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
465 def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
467 def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
469 def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
471 def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
473 def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
475 def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
478 /// Load and Store Instructions - aligned
479 let DecoderMethod = "DecodeMemMMImm16" in {
480 def LB_MM : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>;
481 def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>;
482 def LH_MM : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>;
483 def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>;
484 def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
485 def SB_MM : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>;
486 def SH_MM : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>;
487 def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
490 def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>;
492 def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU>, LL_FM_MM<0xe>;
494 /// Load and Store Instructions - unaligned
495 def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
497 def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
499 def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
501 def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
504 /// Load and Store Instructions - multiple
505 def SWM32_MM : StoreMultMM<"swm32">, LWM_FM_MM<0xd>;
506 def LWM32_MM : LoadMultMM<"lwm32">, LWM_FM_MM<0x5>;
509 def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
510 NoItinerary>, ADD_FM_MM<0, 0x58>;
511 def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
512 NoItinerary>, ADD_FM_MM<0, 0x18>;
513 def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT>,
514 CMov_F_I_FM_MM<0x25>;
515 def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF>,
518 /// Move to/from HI/LO
519 def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
521 def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
523 def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
525 def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
528 /// Multiply Add/Sub Instructions
529 def MADD_MM : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>;
530 def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>;
531 def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>;
532 def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>;
535 def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>,
537 def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>,
540 /// Sign Ext In Register Instructions.
541 def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
542 SEB_FM_MM<0x0ac>, ISA_MIPS32R2;
543 def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
544 SEB_FM_MM<0x0ec>, ISA_MIPS32R2;
546 /// Word Swap Bytes Within Halfwords
547 def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM_MM<0x1ec>,
550 def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>,
552 def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>,
555 /// Jump Instructions
556 let DecoderMethod = "DecodeJumpTargetMM" in {
557 def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
559 def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>;
561 def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>;
562 def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
564 /// Jump Instructions - Short Delay Slot
565 def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>;
566 def JALRS_MM : JumpLinkRegMM<"jalrs", GPR32Opnd>, JALR_FM_MM<0x13c>;
568 /// Branch Instructions
569 def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
571 def BNE_MM : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
573 def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
575 def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,
577 def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
579 def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
581 def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,
583 def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
586 /// Branch Instructions - Short Delay Slot
587 def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm,
588 GPR32Opnd>, BGEZAL_FM_MM<0x13>;
589 def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm,
590 GPR32Opnd>, BGEZAL_FM_MM<0x11>;
592 /// Control Instructions
593 def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM;
594 def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM;
595 def SYSCALL_MM : MMRel, SYS_FT<"syscall">, SYS_FM_MM;
596 def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM;
597 def ERET_MM : MMRel, ER_FT<"eret">, ER_FM_MM<0x3cd>;
598 def DERET_MM : MMRel, ER_FT<"deret">, ER_FM_MM<0x38d>;
599 def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>,
601 def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>,
604 /// Trap Instructions
605 def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM_MM<0x0>;
606 def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM_MM<0x08>;
607 def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM_MM<0x10>;
608 def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM_MM<0x20>;
609 def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM_MM<0x28>;
610 def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM_MM<0x30>;
612 def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM_MM<0x0e>;
613 def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM_MM<0x09>;
614 def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM_MM<0x0b>;
615 def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM_MM<0x08>;
616 def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM_MM<0x0a>;
617 def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM_MM<0x0c>;
619 /// Load-linked, Store-conditional
620 def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
621 def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
623 def TLBP_MM : MMRel, TLB<"tlbp">, COP0_TLB_FM_MM<0x0d>;
624 def TLBR_MM : MMRel, TLB<"tlbr">, COP0_TLB_FM_MM<0x4d>;
625 def TLBWI_MM : MMRel, TLB<"tlbwi">, COP0_TLB_FM_MM<0x8d>;
626 def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>;
628 def SDBBP_MM : MMRel, SYS_FT<"sdbbp">, SDBBP_FM_MM;
629 def RDHWR_MM : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM_MM;
632 let Predicates = [InMicroMips] in {
634 //===----------------------------------------------------------------------===//
635 // MicroMips arbitrary patterns that map to one or more instructions
636 //===----------------------------------------------------------------------===//
638 def : MipsPat<(add GPRMM16:$src, immSExtAddiur2:$imm),
639 (ADDIUR2_MM GPRMM16:$src, immSExtAddiur2:$imm)>;
640 def : MipsPat<(add GPR32:$src, immSExtAddius5:$imm),
641 (ADDIUS5_MM GPR32:$src, immSExtAddius5:$imm)>;
642 def : MipsPat<(add GPR32:$src, immSExt16:$imm),
643 (ADDiu_MM GPR32:$src, immSExt16:$imm)>;
645 def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
646 (ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>;
647 def : MipsPat<(and GPR32:$src, immZExt16:$imm),
648 (ANDi_MM GPR32:$src, immZExt16:$imm)>;
650 def : MipsPat<(shl GPRMM16:$src, immZExt2Shift:$imm),
651 (SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
652 def : MipsPat<(shl GPR32:$src, immZExt5:$imm),
653 (SLL_MM GPR32:$src, immZExt5:$imm)>;
655 def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm),
656 (SRL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
657 def : MipsPat<(srl GPR32:$src, immZExt5:$imm),
658 (SRL_MM GPR32:$src, immZExt5:$imm)>;
660 //===----------------------------------------------------------------------===//
661 // MicroMips instruction aliases
662 //===----------------------------------------------------------------------===//
664 def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;