lib/Target/Mips/MicroMipsInstrFPU.td

   1 let isCodeGenOnly = 1, Predicates = [InMicroMips] in {
   2 def FADD_S_MM : MMRel, ADDS_FT<"add.s", FGR32Opnd, IIFadd, 1, fadd>,
   3                 ADDS_FM_MM<0, 0x30>;
   4 def FDIV_S_MM : MMRel, ADDS_FT<"div.s", FGR32Opnd, IIFdivSingle, 0, fdiv>,
   5                 ADDS_FM_MM<0, 0xf0>;
   6 def FMUL_S_MM : MMRel, ADDS_FT<"mul.s", FGR32Opnd, IIFmulSingle, 1, fmul>,
   7                 ADDS_FM_MM<0, 0xb0>;
   8 def FSUB_S_MM : MMRel, ADDS_FT<"sub.s", FGR32Opnd, IIFadd, 0, fsub>,
   9                 ADDS_FM_MM<0, 0x70>;
  10
  11 def FADD_MM  : MMRel, ADDS_FT<"add.d", AFGR64Opnd, IIFadd, 1, fadd>,
  12                ADDS_FM_MM<1, 0x30>;
  13 def FDIV_MM  : MMRel, ADDS_FT<"div.d", AFGR64Opnd, IIFdivDouble, 0, fdiv>,
  14                ADDS_FM_MM<1, 0xf0>;
  15 def FMUL_MM  : MMRel, ADDS_FT<"mul.d", AFGR64Opnd, IIFmulDouble, 1, fmul>,
  16                ADDS_FM_MM<1, 0xb0>;
  17 def FSUB_MM  : MMRel, ADDS_FT<"sub.d", AFGR64Opnd, IIFadd, 0, fsub>,
  18                ADDS_FM_MM<1, 0x70>;
  19
  20 def LWC1_MM : MMRel, LW_FT<"lwc1", FGR32Opnd, IIFLoad, load>, LW_FM_MM<0x27>;
  21 def SWC1_MM : MMRel, SW_FT<"swc1", FGR32Opnd, IIFStore, store>,
  22               LW_FM_MM<0x26>;
  23 def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, IIFLoad, load>, LW_FM_MM<0x2f>;
  24 def SDC1_MM : MMRel, SW_FT<"sdc1", AFGR64Opnd, IIFStore, store>,
  25               LW_FM_MM<0x2e>;
  26 def LWXC1_MM : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, IIFLoad, load>,
  27                LWXC1_FM_MM<0x48>;
  28 def SWXC1_MM : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, IIFStore, store>,
  29                SWXC1_FM_MM<0x88>;
  30 def LUXC1_MM : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, IIFLoad>,
  31                LWXC1_FM_MM<0x148>;
  32 def SUXC1_MM : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, IIFStore>,
  33                SWXC1_FM_MM<0x188>;
  34
  35 def FCMP_S32_MM : MMRel, CEQS_FT<"s", FGR32, IIFcmp, MipsFPCmp>,
  36                   CEQS_FM_MM<0>;
  37 def FCMP_D32_MM : MMRel, CEQS_FT<"d", AFGR64, IIFcmp, MipsFPCmp>,
  38                   CEQS_FM_MM<1>;
  39
  40 def BC1F_MM : MMRel, BC1F_FT<"bc1f", brtarget_mm, IIBranch, MIPS_BRANCH_F>,
  41               BC1F_FM_MM<0x1c>;
  42 def BC1T_MM : MMRel, BC1F_FT<"bc1t", brtarget_mm, IIBranch, MIPS_BRANCH_T>,
  43               BC1F_FM_MM<0x1d>;
  44
  45 def CEIL_W_S_MM  : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>,
  46                    ROUND_W_FM_MM<0, 0x6c>;
  47 def CVT_W_S_MM   : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>,
  48                    ROUND_W_FM_MM<0, 0x24>;
  49 def FLOOR_W_S_MM : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>,
  50                    ROUND_W_FM_MM<0, 0x2c>;
  51 def ROUND_W_S_MM : MMRel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>,
  52                    ROUND_W_FM_MM<0, 0xec>;
  53 def TRUNC_W_S_MM : MMRel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>,
  54                    ROUND_W_FM_MM<0, 0xac>;
  55 def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd,IIFsqrtSingle,
  56                                 fsqrt>, ROUND_W_FM_MM<0, 0x28>;
  57
  58 def CEIL_W_MM  : MMRel, ABSS_FT<"ceil.w.d", FGR32Opnd, AFGR64Opnd, IIFcvt>,
  59                  ROUND_W_FM_MM<1, 0x6c>;
  60 def CVT_W_MM   : MMRel, ABSS_FT<"cvt.w.d", FGR32Opnd, AFGR64Opnd, IIFcvt>,
  61                  ROUND_W_FM_MM<1, 0x24>;
  62 def FLOOR_W_MM : MMRel, ABSS_FT<"floor.w.d", FGR32Opnd, AFGR64Opnd, IIFcvt>,
  63                  ROUND_W_FM_MM<1, 0x2c>;
  64 def ROUND_W_MM : MMRel, ABSS_FT<"round.w.d", FGR32Opnd, AFGR64Opnd, IIFcvt>,
  65                  ROUND_W_FM_MM<1, 0xec>;
  66 def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, IIFcvt>,
  67                  ROUND_W_FM_MM<1, 0xac>;
  68
  69 def FSQRT_MM : MMRel, ABSS_FT<"sqrt.d", AFGR64Opnd, AFGR64Opnd,
  70                               IIFsqrtDouble, fsqrt>, ROUND_W_FM_MM<1, 0x28>;
  71
  72 def CVT_L_S_MM   : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>,
  73                    ROUND_W_FM_MM<0, 0x4>;
  74 def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>,
  75                    ROUND_W_FM_MM<1, 0x4>;
  76
  77 def FABS_S_MM : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, IIFcvt, fabs>,
  78                 ABS_FM_MM<0, 0xd>;
  79 def FMOV_S_MM : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, IIFmove>,
  80                 ABS_FM_MM<0, 0x1>;
  81 def FNEG_S_MM : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, IIFcvt, fneg>,
  82                 ABS_FM_MM<0, 0x2d>;
  83 def CVT_D_S_MM : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, IIFcvt>,
  84                  ABS_FM_MM<0, 0x4d>;
  85 def CVT_D32_W_MM : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, IIFcvt>,
  86                    ABS_FM_MM<1, 0x4d>;
  87 def CVT_S_D32_MM : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, IIFcvt>,
  88                    ABS_FM_MM<0, 0x6d>;
  89 def CVT_S_W_MM : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, IIFcvt>,
  90                  ABS_FM_MM<1, 0x6d>;
  91
  92 def FABS_MM : MMRel, ABSS_FT<"abs.d", AFGR64Opnd, AFGR64Opnd, IIFcvt, fabs>,
  93               ABS_FM_MM<1, 0xd>;
  94 def FNEG_MM : MMRel, ABSS_FT<"neg.d", AFGR64Opnd, AFGR64Opnd, IIFcvt, fneg>,
  95               ABS_FM_MM<1, 0x2d>;
  96
  97 def FMOV_D32_MM : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, IIFmove>,
  98                   ABS_FM_MM<1, 0x1>, Requires<[NotFP64bit, HasStdEnc]>;
  99 }