1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MipsMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
15 #include "MipsMCCodeEmitter.h"
16 #include "MCTargetDesc/MipsFixupKinds.h"
17 #include "MCTargetDesc/MipsMCExpr.h"
18 #include "MCTargetDesc/MipsMCTargetDesc.h"
19 #include "llvm/ADT/APFloat.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCFixup.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "mccodeemitter"
31 #define GET_INSTRMAP_INFO
32 #include "MipsGenInstrInfo.inc"
33 #undef GET_INSTRMAP_INFO
36 MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
37 const MCRegisterInfo &MRI,
38 const MCSubtargetInfo &STI,
40 return new MipsMCCodeEmitter(MCII, Ctx, false);
43 MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
44 const MCRegisterInfo &MRI,
45 const MCSubtargetInfo &STI,
47 return new MipsMCCodeEmitter(MCII, Ctx, true);
49 } // End of namespace llvm.
51 // If the D<shift> instruction has a shift amount that is greater
52 // than 31 (checked in calling routine), lower it to a D<shift>32 instruction
53 static void LowerLargeShift(MCInst& Inst) {
55 assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!");
56 assert(Inst.getOperand(2).isImm());
58 int64_t Shift = Inst.getOperand(2).getImm();
64 Inst.getOperand(2).setImm(Shift);
66 switch (Inst.getOpcode()) {
68 // Calling function is not synchronized
69 llvm_unreachable("Unexpected shift instruction");
71 Inst.setOpcode(Mips::DSLL32);
74 Inst.setOpcode(Mips::DSRL32);
77 Inst.setOpcode(Mips::DSRA32);
80 Inst.setOpcode(Mips::DROTR32);
85 // Pick a DEXT or DINS instruction variant based on the pos and size operands
86 static void LowerDextDins(MCInst& InstIn) {
87 int Opcode = InstIn.getOpcode();
89 if (Opcode == Mips::DEXT)
90 assert(InstIn.getNumOperands() == 4 &&
91 "Invalid no. of machine operands for DEXT!");
92 else // Only DEXT and DINS are possible
93 assert(InstIn.getNumOperands() == 5 &&
94 "Invalid no. of machine operands for DINS!");
96 assert(InstIn.getOperand(2).isImm());
97 int64_t pos = InstIn.getOperand(2).getImm();
98 assert(InstIn.getOperand(3).isImm());
99 int64_t size = InstIn.getOperand(3).getImm();
102 if (pos < 32) // DEXT/DINS, do nothing
105 InstIn.getOperand(2).setImm(pos - 32);
106 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU);
110 assert(pos < 32 && "DEXT/DINS cannot have both size and pos > 32");
111 InstIn.getOperand(3).setImm(size - 32);
112 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM);
116 bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
117 return STI.getFeatureBits() & Mips::FeatureMicroMips;
120 void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const {
124 void MipsMCCodeEmitter::EmitInstruction(uint64_t Val, unsigned Size,
125 const MCSubtargetInfo &STI,
126 raw_ostream &OS) const {
127 // Output the instruction encoding in little endian byte order.
128 // Little-endian byte ordering:
129 // mips32r2: 4 | 3 | 2 | 1
130 // microMIPS: 2 | 1 | 4 | 3
131 if (IsLittleEndian && Size == 4 && isMicroMips(STI)) {
132 EmitInstruction(Val >> 16, 2, STI, OS);
133 EmitInstruction(Val, 2, STI, OS);
135 for (unsigned i = 0; i < Size; ++i) {
136 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
137 EmitByte((Val >> Shift) & 0xff, OS);
142 /// EncodeInstruction - Emit the instruction.
143 /// Size the instruction with Desc.getSize().
144 void MipsMCCodeEmitter::
145 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
146 SmallVectorImpl<MCFixup> &Fixups,
147 const MCSubtargetInfo &STI) const
150 // Non-pseudo instructions that get changed for direct object
151 // only based on operand values.
152 // If this list of instructions get much longer we will move
153 // the check to a function call. Until then, this is more efficient.
155 switch (MI.getOpcode()) {
156 // If shift amount is >= 32 it the inst needs to be lowered further
161 LowerLargeShift(TmpInst);
163 // Double extract instruction is chosen by pos and size operands
166 LowerDextDins(TmpInst);
169 unsigned long N = Fixups.size();
170 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
172 // Check for unimplemented opcodes.
173 // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
174 // so we have to special check for them.
175 unsigned Opcode = TmpInst.getOpcode();
176 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) &&
177 (Opcode != Mips::SLL_MM) && !Binary)
178 llvm_unreachable("unimplemented opcode in EncodeInstruction()");
180 if (STI.getFeatureBits() & Mips::FeatureMicroMips) {
181 int NewOpcode = Mips::Std2MicroMips (Opcode, Mips::Arch_micromips);
182 if (NewOpcode != -1) {
183 if (Fixups.size() > N)
186 TmpInst.setOpcode (NewOpcode);
187 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
191 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
193 // Get byte count of instruction
194 unsigned Size = Desc.getSize();
196 llvm_unreachable("Desc.getSize() returns 0");
198 EmitInstruction(Binary, Size, STI, OS);
201 /// getBranchTargetOpValue - Return binary encoding of the branch
202 /// target operand. If the machine operand requires relocation,
203 /// record the relocation and return zero.
204 unsigned MipsMCCodeEmitter::
205 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
206 SmallVectorImpl<MCFixup> &Fixups,
207 const MCSubtargetInfo &STI) const {
209 const MCOperand &MO = MI.getOperand(OpNo);
211 // If the destination is an immediate, divide by 4.
212 if (MO.isImm()) return MO.getImm() >> 2;
214 assert(MO.isExpr() &&
215 "getBranchTargetOpValue expects only expressions or immediates");
217 const MCExpr *Expr = MO.getExpr();
218 Fixups.push_back(MCFixup::Create(0, Expr,
219 MCFixupKind(Mips::fixup_Mips_PC16)));
223 /// getBranchTargetOpValue - Return binary encoding of the microMIPS branch
224 /// target operand. If the machine operand requires relocation,
225 /// record the relocation and return zero.
226 unsigned MipsMCCodeEmitter::
227 getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
228 SmallVectorImpl<MCFixup> &Fixups,
229 const MCSubtargetInfo &STI) const {
231 const MCOperand &MO = MI.getOperand(OpNo);
233 // If the destination is an immediate, divide by 2.
234 if (MO.isImm()) return MO.getImm() >> 1;
236 assert(MO.isExpr() &&
237 "getBranchTargetOpValueMM expects only expressions or immediates");
239 const MCExpr *Expr = MO.getExpr();
240 Fixups.push_back(MCFixup::Create(0, Expr,
242 fixup_MICROMIPS_PC16_S1)));
246 /// getBranchTarget21OpValue - Return binary encoding of the branch
247 /// target operand. If the machine operand requires relocation,
248 /// record the relocation and return zero.
249 unsigned MipsMCCodeEmitter::
250 getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
251 SmallVectorImpl<MCFixup> &Fixups,
252 const MCSubtargetInfo &STI) const {
254 const MCOperand &MO = MI.getOperand(OpNo);
256 // If the destination is an immediate, divide by 4.
257 if (MO.isImm()) return MO.getImm() >> 2;
259 assert(MO.isExpr() &&
260 "getBranchTarget21OpValue expects only expressions or immediates");
262 const MCExpr *Expr = MO.getExpr();
263 Fixups.push_back(MCFixup::Create(0, Expr,
264 MCFixupKind(Mips::fixup_MIPS_PC21_S2)));
268 /// getBranchTarget26OpValue - Return binary encoding of the branch
269 /// target operand. If the machine operand requires relocation,
270 /// record the relocation and return zero.
271 unsigned MipsMCCodeEmitter::
272 getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
273 SmallVectorImpl<MCFixup> &Fixups,
274 const MCSubtargetInfo &STI) const {
276 const MCOperand &MO = MI.getOperand(OpNo);
278 // If the destination is an immediate, divide by 4.
279 if (MO.isImm()) return MO.getImm() >> 2;
281 assert(MO.isExpr() &&
282 "getBranchTarget26OpValue expects only expressions or immediates");
284 const MCExpr *Expr = MO.getExpr();
285 Fixups.push_back(MCFixup::Create(0, Expr,
286 MCFixupKind(Mips::fixup_MIPS_PC26_S2)));
290 /// getJumpOffset16OpValue - Return binary encoding of the jump
291 /// target operand. If the machine operand requires relocation,
292 /// record the relocation and return zero.
293 unsigned MipsMCCodeEmitter::
294 getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo,
295 SmallVectorImpl<MCFixup> &Fixups,
296 const MCSubtargetInfo &STI) const {
298 const MCOperand &MO = MI.getOperand(OpNo);
300 if (MO.isImm()) return MO.getImm();
302 assert(MO.isExpr() &&
303 "getJumpOffset16OpValue expects only expressions or an immediate");
309 /// getJumpTargetOpValue - Return binary encoding of the jump
310 /// target operand. If the machine operand requires relocation,
311 /// record the relocation and return zero.
312 unsigned MipsMCCodeEmitter::
313 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
314 SmallVectorImpl<MCFixup> &Fixups,
315 const MCSubtargetInfo &STI) const {
317 const MCOperand &MO = MI.getOperand(OpNo);
318 // If the destination is an immediate, divide by 4.
319 if (MO.isImm()) return MO.getImm()>>2;
321 assert(MO.isExpr() &&
322 "getJumpTargetOpValue expects only expressions or an immediate");
324 const MCExpr *Expr = MO.getExpr();
325 Fixups.push_back(MCFixup::Create(0, Expr,
326 MCFixupKind(Mips::fixup_Mips_26)));
330 unsigned MipsMCCodeEmitter::
331 getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
332 SmallVectorImpl<MCFixup> &Fixups,
333 const MCSubtargetInfo &STI) const {
335 const MCOperand &MO = MI.getOperand(OpNo);
336 // If the destination is an immediate, divide by 2.
337 if (MO.isImm()) return MO.getImm() >> 1;
339 assert(MO.isExpr() &&
340 "getJumpTargetOpValueMM expects only expressions or an immediate");
342 const MCExpr *Expr = MO.getExpr();
343 Fixups.push_back(MCFixup::Create(0, Expr,
344 MCFixupKind(Mips::fixup_MICROMIPS_26_S1)));
348 unsigned MipsMCCodeEmitter::
349 getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo,
350 SmallVectorImpl<MCFixup> &Fixups,
351 const MCSubtargetInfo &STI) const {
353 const MCOperand &MO = MI.getOperand(OpNo);
355 // The immediate is encoded as 'immediate << 2'.
356 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
357 assert((Res & 3) == 0);
361 assert(MO.isExpr() &&
362 "getUImm5Lsl2Encoding expects only expressions or an immediate");
367 unsigned MipsMCCodeEmitter::
368 getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo,
369 SmallVectorImpl<MCFixup> &Fixups,
370 const MCSubtargetInfo &STI) const {
372 const MCOperand &MO = MI.getOperand(OpNo);
374 int Value = MO.getImm();
381 unsigned MipsMCCodeEmitter::
382 getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo,
383 SmallVectorImpl<MCFixup> &Fixups,
384 const MCSubtargetInfo &STI) const {
386 const MCOperand &MO = MI.getOperand(OpNo);
388 unsigned Value = MO.getImm();
395 unsigned MipsMCCodeEmitter::
396 getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo,
397 SmallVectorImpl<MCFixup> &Fixups,
398 const MCSubtargetInfo &STI) const {
400 const MCOperand &MO = MI.getOperand(OpNo);
402 unsigned Binary = (MO.getImm() >> 2) & 0x0000ffff;
403 return (((Binary & 0x8000) >> 7) | (Binary & 0x00ff));
409 unsigned MipsMCCodeEmitter::
410 getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups,
411 const MCSubtargetInfo &STI) const {
414 if (Expr->EvaluateAsAbsolute(Res))
417 MCExpr::ExprKind Kind = Expr->getKind();
418 if (Kind == MCExpr::Constant) {
419 return cast<MCConstantExpr>(Expr)->getValue();
422 if (Kind == MCExpr::Binary) {
423 unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI);
424 Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI);
428 if (Kind == MCExpr::Target) {
429 const MipsMCExpr *MipsExpr = cast<MipsMCExpr>(Expr);
431 Mips::Fixups FixupKind = Mips::Fixups(0);
432 switch (MipsExpr->getKind()) {
433 default: llvm_unreachable("Unsupported fixup kind for target expression!");
434 case MipsMCExpr::VK_Mips_HIGHEST:
435 FixupKind = Mips::fixup_Mips_HIGHEST;
437 case MipsMCExpr::VK_Mips_HIGHER:
438 FixupKind = Mips::fixup_Mips_HIGHER;
440 case MipsMCExpr::VK_Mips_HI:
441 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
442 : Mips::fixup_Mips_HI16;
444 case MipsMCExpr::VK_Mips_LO:
445 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
446 : Mips::fixup_Mips_LO16;
449 Fixups.push_back(MCFixup::Create(0, MipsExpr, MCFixupKind(FixupKind)));
453 if (Kind == MCExpr::SymbolRef) {
454 Mips::Fixups FixupKind = Mips::Fixups(0);
456 switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
457 default: llvm_unreachable("Unknown fixup kind!");
459 case MCSymbolRefExpr::VK_Mips_GPOFF_HI :
460 FixupKind = Mips::fixup_Mips_GPOFF_HI;
462 case MCSymbolRefExpr::VK_Mips_GPOFF_LO :
463 FixupKind = Mips::fixup_Mips_GPOFF_LO;
465 case MCSymbolRefExpr::VK_Mips_GOT_PAGE :
466 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_PAGE
467 : Mips::fixup_Mips_GOT_PAGE;
469 case MCSymbolRefExpr::VK_Mips_GOT_OFST :
470 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_OFST
471 : Mips::fixup_Mips_GOT_OFST;
473 case MCSymbolRefExpr::VK_Mips_GOT_DISP :
474 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_DISP
475 : Mips::fixup_Mips_GOT_DISP;
477 case MCSymbolRefExpr::VK_Mips_GPREL:
478 FixupKind = Mips::fixup_Mips_GPREL16;
480 case MCSymbolRefExpr::VK_Mips_GOT_CALL:
481 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_CALL16
482 : Mips::fixup_Mips_CALL16;
484 case MCSymbolRefExpr::VK_Mips_GOT16:
485 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
486 : Mips::fixup_Mips_GOT_Global;
488 case MCSymbolRefExpr::VK_Mips_GOT:
489 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
490 : Mips::fixup_Mips_GOT_Local;
492 case MCSymbolRefExpr::VK_Mips_ABS_HI:
493 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
494 : Mips::fixup_Mips_HI16;
496 case MCSymbolRefExpr::VK_Mips_ABS_LO:
497 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
498 : Mips::fixup_Mips_LO16;
500 case MCSymbolRefExpr::VK_Mips_TLSGD:
501 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_GD
502 : Mips::fixup_Mips_TLSGD;
504 case MCSymbolRefExpr::VK_Mips_TLSLDM:
505 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_LDM
506 : Mips::fixup_Mips_TLSLDM;
508 case MCSymbolRefExpr::VK_Mips_DTPREL_HI:
509 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_HI16
510 : Mips::fixup_Mips_DTPREL_HI;
512 case MCSymbolRefExpr::VK_Mips_DTPREL_LO:
513 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_LO16
514 : Mips::fixup_Mips_DTPREL_LO;
516 case MCSymbolRefExpr::VK_Mips_GOTTPREL:
517 FixupKind = Mips::fixup_Mips_GOTTPREL;
519 case MCSymbolRefExpr::VK_Mips_TPREL_HI:
520 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_HI16
521 : Mips::fixup_Mips_TPREL_HI;
523 case MCSymbolRefExpr::VK_Mips_TPREL_LO:
524 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_LO16
525 : Mips::fixup_Mips_TPREL_LO;
527 case MCSymbolRefExpr::VK_Mips_HIGHER:
528 FixupKind = Mips::fixup_Mips_HIGHER;
530 case MCSymbolRefExpr::VK_Mips_HIGHEST:
531 FixupKind = Mips::fixup_Mips_HIGHEST;
533 case MCSymbolRefExpr::VK_Mips_GOT_HI16:
534 FixupKind = Mips::fixup_Mips_GOT_HI16;
536 case MCSymbolRefExpr::VK_Mips_GOT_LO16:
537 FixupKind = Mips::fixup_Mips_GOT_LO16;
539 case MCSymbolRefExpr::VK_Mips_CALL_HI16:
540 FixupKind = Mips::fixup_Mips_CALL_HI16;
542 case MCSymbolRefExpr::VK_Mips_CALL_LO16:
543 FixupKind = Mips::fixup_Mips_CALL_LO16;
545 case MCSymbolRefExpr::VK_Mips_PCREL_HI16:
546 FixupKind = Mips::fixup_MIPS_PCHI16;
548 case MCSymbolRefExpr::VK_Mips_PCREL_LO16:
549 FixupKind = Mips::fixup_MIPS_PCLO16;
553 Fixups.push_back(MCFixup::Create(0, Expr, MCFixupKind(FixupKind)));
559 /// getMachineOpValue - Return binary encoding of operand. If the machine
560 /// operand requires relocation, record the relocation and return zero.
561 unsigned MipsMCCodeEmitter::
562 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
563 SmallVectorImpl<MCFixup> &Fixups,
564 const MCSubtargetInfo &STI) const {
566 unsigned Reg = MO.getReg();
567 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
569 } else if (MO.isImm()) {
570 return static_cast<unsigned>(MO.getImm());
571 } else if (MO.isFPImm()) {
572 return static_cast<unsigned>(APFloat(MO.getFPImm())
573 .bitcastToAPInt().getHiBits(32).getLimitedValue());
575 // MO must be an Expr.
577 return getExprOpValue(MO.getExpr(),Fixups, STI);
580 /// getMSAMemEncoding - Return binary encoding of memory operand for LD/ST
583 MipsMCCodeEmitter::getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
584 SmallVectorImpl<MCFixup> &Fixups,
585 const MCSubtargetInfo &STI) const {
586 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
587 assert(MI.getOperand(OpNo).isReg());
588 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
589 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
591 // The immediate field of an LD/ST instruction is scaled which means it must
592 // be divided (when encoding) by the size (in bytes) of the instructions'
598 switch(MI.getOpcode())
601 assert (0 && "Unexpected instruction");
605 // We don't need to scale the offset in this case
621 return (OffBits & 0xFFFF) | RegBits;
624 /// getMemEncoding - Return binary encoding of memory related operand.
625 /// If the offset operand requires relocation, record the relocation.
627 MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
628 SmallVectorImpl<MCFixup> &Fixups,
629 const MCSubtargetInfo &STI) const {
630 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
631 assert(MI.getOperand(OpNo).isReg());
632 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
633 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
635 return (OffBits & 0xFFFF) | RegBits;
638 unsigned MipsMCCodeEmitter::
639 getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo,
640 SmallVectorImpl<MCFixup> &Fixups,
641 const MCSubtargetInfo &STI) const {
642 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
643 assert(MI.getOperand(OpNo).isReg());
644 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
646 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
649 return (OffBits & 0xF) | RegBits;
652 unsigned MipsMCCodeEmitter::
653 getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo,
654 SmallVectorImpl<MCFixup> &Fixups,
655 const MCSubtargetInfo &STI) const {
656 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
657 assert(MI.getOperand(OpNo).isReg());
658 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
660 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
663 return (OffBits & 0xF) | RegBits;
666 unsigned MipsMCCodeEmitter::
667 getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo,
668 SmallVectorImpl<MCFixup> &Fixups,
669 const MCSubtargetInfo &STI) const {
670 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
671 assert(MI.getOperand(OpNo).isReg());
672 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
674 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
677 return (OffBits & 0xF) | RegBits;
680 unsigned MipsMCCodeEmitter::
681 getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo,
682 SmallVectorImpl<MCFixup> &Fixups,
683 const MCSubtargetInfo &STI) const {
684 // Register is encoded in bits 9-5, offset is encoded in bits 4-0.
685 assert(MI.getOperand(OpNo).isReg() &&
686 MI.getOperand(OpNo).getReg() == Mips::SP &&
687 "Unexpected base register!");
688 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
691 return OffBits & 0x1F;
694 unsigned MipsMCCodeEmitter::
695 getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
696 SmallVectorImpl<MCFixup> &Fixups,
697 const MCSubtargetInfo &STI) const {
698 // opNum can be invalid if instruction had reglist as operand.
699 // MemOperand is always last operand of instruction (base + offset).
700 switch (MI.getOpcode()) {
705 OpNo = MI.getNumOperands() - 2;
709 // Base register is encoded in bits 20-16, offset is encoded in bits 11-0.
710 assert(MI.getOperand(OpNo).isReg());
711 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16;
712 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
714 return (OffBits & 0x0FFF) | RegBits;
717 unsigned MipsMCCodeEmitter::
718 getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo,
719 SmallVectorImpl<MCFixup> &Fixups,
720 const MCSubtargetInfo &STI) const {
721 // opNum can be invalid if instruction had reglist as operand
722 // MemOperand is always last operand of instruction (base + offset)
723 switch (MI.getOpcode()) {
728 OpNo = MI.getNumOperands() - 2;
732 // Offset is encoded in bits 4-0.
733 assert(MI.getOperand(OpNo).isReg());
734 // Base register is always SP - thus it is not encoded.
735 assert(MI.getOperand(OpNo+1).isImm());
736 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
738 return ((OffBits >> 2) & 0x0F);
742 MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
743 SmallVectorImpl<MCFixup> &Fixups,
744 const MCSubtargetInfo &STI) const {
745 assert(MI.getOperand(OpNo).isImm());
746 unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
747 return SizeEncoding - 1;
750 // FIXME: should be called getMSBEncoding
753 MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
754 SmallVectorImpl<MCFixup> &Fixups,
755 const MCSubtargetInfo &STI) const {
756 assert(MI.getOperand(OpNo-1).isImm());
757 assert(MI.getOperand(OpNo).isImm());
758 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups, STI);
759 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
761 return Position + Size - 1;
765 MipsMCCodeEmitter::getLSAImmEncoding(const MCInst &MI, unsigned OpNo,
766 SmallVectorImpl<MCFixup> &Fixups,
767 const MCSubtargetInfo &STI) const {
768 assert(MI.getOperand(OpNo).isImm());
769 // The immediate is encoded as 'immediate - 1'.
770 return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) - 1;
774 MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
775 SmallVectorImpl<MCFixup> &Fixups,
776 const MCSubtargetInfo &STI) const {
777 const MCOperand &MO = MI.getOperand(OpNo);
779 // The immediate is encoded as 'immediate << 2'.
780 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
781 assert((Res & 3) == 0);
785 assert(MO.isExpr() &&
786 "getSimm19Lsl2Encoding expects only expressions or an immediate");
788 const MCExpr *Expr = MO.getExpr();
789 Fixups.push_back(MCFixup::Create(0, Expr,
790 MCFixupKind(Mips::fixup_MIPS_PC19_S2)));
795 MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo,
796 SmallVectorImpl<MCFixup> &Fixups,
797 const MCSubtargetInfo &STI) const {
798 const MCOperand &MO = MI.getOperand(OpNo);
800 // The immediate is encoded as 'immediate << 3'.
801 unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
802 assert((Res & 7) == 0);
806 assert(MO.isExpr() &&
807 "getSimm18Lsl2Encoding expects only expressions or an immediate");
809 const MCExpr *Expr = MO.getExpr();
810 Fixups.push_back(MCFixup::Create(0, Expr,
811 MCFixupKind(Mips::fixup_MIPS_PC18_S3)));
816 MipsMCCodeEmitter::getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo,
817 SmallVectorImpl<MCFixup> &Fixups,
818 const MCSubtargetInfo &STI) const {
819 assert(MI.getOperand(OpNo).isImm());
820 const MCOperand &MO = MI.getOperand(OpNo);
821 return MO.getImm() % 8;
825 MipsMCCodeEmitter::getUImm4AndValue(const MCInst &MI, unsigned OpNo,
826 SmallVectorImpl<MCFixup> &Fixups,
827 const MCSubtargetInfo &STI) const {
828 assert(MI.getOperand(OpNo).isImm());
829 const MCOperand &MO = MI.getOperand(OpNo);
830 unsigned Value = MO.getImm();
832 case 128: return 0x0;
845 case 255: return 0xd;
846 case 32768: return 0xe;
847 case 65535: return 0xf;
849 llvm_unreachable("Unexpected value");
853 MipsMCCodeEmitter::getRegisterListOpValue(const MCInst &MI, unsigned OpNo,
854 SmallVectorImpl<MCFixup> &Fixups,
855 const MCSubtargetInfo &STI) const {
858 // Register list operand is always first operand of instruction and it is
859 // placed before memory operand (register + imm).
861 for (unsigned I = OpNo, E = MI.getNumOperands() - 2; I < E; ++I) {
862 unsigned Reg = MI.getOperand(I).getReg();
863 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
873 MipsMCCodeEmitter::getRegisterListOpValue16(const MCInst &MI, unsigned OpNo,
874 SmallVectorImpl<MCFixup> &Fixups,
875 const MCSubtargetInfo &STI) const {
876 return (MI.getNumOperands() - 4);
880 MipsMCCodeEmitter::getRegisterPairOpValue(const MCInst &MI, unsigned OpNo,
881 SmallVectorImpl<MCFixup> &Fixups,
882 const MCSubtargetInfo &STI) const {
883 return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
886 #include "MipsGenMCCodeEmitter.inc"