1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MipsMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/MipsBaseInfo.h"
16 #include "MCTargetDesc/MipsDirectObjLower.h"
17 #include "MCTargetDesc/MipsFixupKinds.h"
18 #include "MCTargetDesc/MipsMCTargetDesc.h"
19 #include "llvm/ADT/APFloat.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/MC/MCCodeEmitter.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCExpr.h"
24 #include "llvm/MC/MCInst.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/Support/raw_ostream.h"
33 class MipsMCCodeEmitter : public MCCodeEmitter {
34 MipsMCCodeEmitter(const MipsMCCodeEmitter &) LLVM_DELETED_FUNCTION;
35 void operator=(const MipsMCCodeEmitter &) LLVM_DELETED_FUNCTION;
36 const MCInstrInfo &MCII;
38 const MCSubtargetInfo &STI;
42 MipsMCCodeEmitter(const MCInstrInfo &mcii, MCContext &Ctx_,
43 const MCSubtargetInfo &sti, bool IsLittle) :
44 MCII(mcii), Ctx(Ctx_), STI (sti), IsLittleEndian(IsLittle) {}
46 ~MipsMCCodeEmitter() {}
48 void EmitByte(unsigned char C, raw_ostream &OS) const {
52 void EmitInstruction(uint64_t Val, unsigned Size, raw_ostream &OS) const {
53 // Output the instruction encoding in little endian byte order.
54 for (unsigned i = 0; i < Size; ++i) {
55 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
56 EmitByte((Val >> Shift) & 0xff, OS);
60 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
61 SmallVectorImpl<MCFixup> &Fixups) const;
63 // getBinaryCodeForInstr - TableGen'erated function for getting the
64 // binary encoding for an instruction.
65 uint64_t getBinaryCodeForInstr(const MCInst &MI,
66 SmallVectorImpl<MCFixup> &Fixups) const;
68 // getBranchJumpOpValue - Return binary encoding of the jump
69 // target operand. If the machine operand requires relocation,
70 // record the relocation and return zero.
71 unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
72 SmallVectorImpl<MCFixup> &Fixups) const;
74 // getBranchTargetOpValue - Return binary encoding of the branch
75 // target operand. If the machine operand requires relocation,
76 // record the relocation and return zero.
77 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
78 SmallVectorImpl<MCFixup> &Fixups) const;
80 // getMachineOpValue - Return binary encoding of operand. If the machin
81 // operand requires relocation, record the relocation and return zero.
82 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
83 SmallVectorImpl<MCFixup> &Fixups) const;
85 unsigned getMemEncoding(const MCInst &MI, unsigned OpNo,
86 SmallVectorImpl<MCFixup> &Fixups) const;
87 unsigned getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
88 SmallVectorImpl<MCFixup> &Fixups) const;
89 unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
90 SmallVectorImpl<MCFixup> &Fixups) const;
92 }; // class MipsMCCodeEmitter
95 MCCodeEmitter *llvm::createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
96 const MCRegisterInfo &MRI,
97 const MCSubtargetInfo &STI,
100 return new MipsMCCodeEmitter(MCII, Ctx, STI, false);
103 MCCodeEmitter *llvm::createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
104 const MCRegisterInfo &MRI,
105 const MCSubtargetInfo &STI,
108 return new MipsMCCodeEmitter(MCII, Ctx, STI, true);
111 /// EncodeInstruction - Emit the instruction.
112 /// Size the instruction (currently only 4 bytes
113 void MipsMCCodeEmitter::
114 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
115 SmallVectorImpl<MCFixup> &Fixups) const
118 // Non-pseudo instructions that get changed for direct object
119 // only based on operand values.
120 // If this list of instructions get much longer we will move
121 // the check to a function call. Until then, this is more efficient.
123 switch (MI.getOpcode()) {
124 // If shift amount is >= 32 it the inst needs to be lowered further
128 Mips::LowerLargeShift(TmpInst);
130 // Double extract instruction is chosen by pos and size operands
133 Mips::LowerDextDins(TmpInst);
136 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups);
138 // Check for unimplemented opcodes.
139 // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
140 // so we have to special check for them.
141 unsigned Opcode = TmpInst.getOpcode();
142 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && !Binary)
143 llvm_unreachable("unimplemented opcode in EncodeInstruction()");
145 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
147 // Get byte count of instruction
148 unsigned Size = Desc.getSize();
150 llvm_unreachable("Desc.getSize() returns 0");
152 EmitInstruction(Binary, Size, OS);
155 /// getBranchTargetOpValue - Return binary encoding of the branch
156 /// target operand. If the machine operand requires relocation,
157 /// record the relocation and return zero.
158 unsigned MipsMCCodeEmitter::
159 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
160 SmallVectorImpl<MCFixup> &Fixups) const {
162 const MCOperand &MO = MI.getOperand(OpNo);
164 // If the destination is an immediate, we have nothing to do.
165 if (MO.isImm()) return MO.getImm();
166 assert(MO.isExpr() &&
167 "getBranchTargetOpValue expects only expressions or immediates");
169 const MCExpr *Expr = MO.getExpr();
170 Fixups.push_back(MCFixup::Create(0, Expr,
171 MCFixupKind(Mips::fixup_Mips_PC16)));
175 /// getJumpTargetOpValue - Return binary encoding of the jump
176 /// target operand. If the machine operand requires relocation,
177 /// record the relocation and return zero.
178 unsigned MipsMCCodeEmitter::
179 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
180 SmallVectorImpl<MCFixup> &Fixups) const {
182 const MCOperand &MO = MI.getOperand(OpNo);
183 // If the destination is an immediate, we have nothing to do.
184 if (MO.isImm()) return MO.getImm();
185 assert(MO.isExpr() &&
186 "getJumpTargetOpValue expects only expressions or an immediate");
188 const MCExpr *Expr = MO.getExpr();
189 Fixups.push_back(MCFixup::Create(0, Expr,
190 MCFixupKind(Mips::fixup_Mips_26)));
194 /// getMachineOpValue - Return binary encoding of operand. If the machine
195 /// operand requires relocation, record the relocation and return zero.
196 unsigned MipsMCCodeEmitter::
197 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
198 SmallVectorImpl<MCFixup> &Fixups) const {
200 unsigned Reg = MO.getReg();
201 unsigned RegNo = Ctx.getRegisterInfo().getEncodingValue(Reg);
203 } else if (MO.isImm()) {
204 return static_cast<unsigned>(MO.getImm());
205 } else if (MO.isFPImm()) {
206 return static_cast<unsigned>(APFloat(MO.getFPImm())
207 .bitcastToAPInt().getHiBits(32).getLimitedValue());
210 // MO must be an Expr.
213 const MCExpr *Expr = MO.getExpr();
214 MCExpr::ExprKind Kind = Expr->getKind();
216 if (Kind == MCExpr::Binary) {
217 Expr = static_cast<const MCBinaryExpr*>(Expr)->getLHS();
218 Kind = Expr->getKind();
221 assert (Kind == MCExpr::SymbolRef);
223 Mips::Fixups FixupKind = Mips::Fixups(0);
225 switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
226 default: llvm_unreachable("Unknown fixup kind!");
228 case MCSymbolRefExpr::VK_Mips_GPOFF_HI :
229 FixupKind = Mips::fixup_Mips_GPOFF_HI;
231 case MCSymbolRefExpr::VK_Mips_GPOFF_LO :
232 FixupKind = Mips::fixup_Mips_GPOFF_LO;
234 case MCSymbolRefExpr::VK_Mips_GOT_PAGE :
235 FixupKind = Mips::fixup_Mips_GOT_PAGE;
237 case MCSymbolRefExpr::VK_Mips_GOT_OFST :
238 FixupKind = Mips::fixup_Mips_GOT_OFST;
240 case MCSymbolRefExpr::VK_Mips_GOT_DISP :
241 FixupKind = Mips::fixup_Mips_GOT_DISP;
243 case MCSymbolRefExpr::VK_Mips_GPREL:
244 FixupKind = Mips::fixup_Mips_GPREL16;
246 case MCSymbolRefExpr::VK_Mips_GOT_CALL:
247 FixupKind = Mips::fixup_Mips_CALL16;
249 case MCSymbolRefExpr::VK_Mips_GOT16:
250 FixupKind = Mips::fixup_Mips_GOT_Global;
252 case MCSymbolRefExpr::VK_Mips_GOT:
253 FixupKind = Mips::fixup_Mips_GOT_Local;
255 case MCSymbolRefExpr::VK_Mips_ABS_HI:
256 FixupKind = Mips::fixup_Mips_HI16;
258 case MCSymbolRefExpr::VK_Mips_ABS_LO:
259 FixupKind = Mips::fixup_Mips_LO16;
261 case MCSymbolRefExpr::VK_Mips_TLSGD:
262 FixupKind = Mips::fixup_Mips_TLSGD;
264 case MCSymbolRefExpr::VK_Mips_TLSLDM:
265 FixupKind = Mips::fixup_Mips_TLSLDM;
267 case MCSymbolRefExpr::VK_Mips_DTPREL_HI:
268 FixupKind = Mips::fixup_Mips_DTPREL_HI;
270 case MCSymbolRefExpr::VK_Mips_DTPREL_LO:
271 FixupKind = Mips::fixup_Mips_DTPREL_LO;
273 case MCSymbolRefExpr::VK_Mips_GOTTPREL:
274 FixupKind = Mips::fixup_Mips_GOTTPREL;
276 case MCSymbolRefExpr::VK_Mips_TPREL_HI:
277 FixupKind = Mips::fixup_Mips_TPREL_HI;
279 case MCSymbolRefExpr::VK_Mips_TPREL_LO:
280 FixupKind = Mips::fixup_Mips_TPREL_LO;
282 case MCSymbolRefExpr::VK_Mips_HIGHER:
283 FixupKind = Mips::fixup_Mips_HIGHER;
285 case MCSymbolRefExpr::VK_Mips_HIGHEST:
286 FixupKind = Mips::fixup_Mips_HIGHEST;
288 case MCSymbolRefExpr::VK_Mips_GOT_HI16:
289 FixupKind = Mips::fixup_Mips_GOT_HI16;
291 case MCSymbolRefExpr::VK_Mips_GOT_LO16:
292 FixupKind = Mips::fixup_Mips_GOT_LO16;
294 case MCSymbolRefExpr::VK_Mips_CALL_HI16:
295 FixupKind = Mips::fixup_Mips_CALL_HI16;
297 case MCSymbolRefExpr::VK_Mips_CALL_LO16:
298 FixupKind = Mips::fixup_Mips_CALL_LO16;
302 Fixups.push_back(MCFixup::Create(0, MO.getExpr(), MCFixupKind(FixupKind)));
304 // All of the information is in the fixup.
308 /// getMemEncoding - Return binary encoding of memory related operand.
309 /// If the offset operand requires relocation, record the relocation.
311 MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
312 SmallVectorImpl<MCFixup> &Fixups) const {
313 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
314 assert(MI.getOperand(OpNo).isReg());
315 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups) << 16;
316 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups);
318 return (OffBits & 0xFFFF) | RegBits;
322 MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
323 SmallVectorImpl<MCFixup> &Fixups) const {
324 assert(MI.getOperand(OpNo).isImm());
325 unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
326 return SizeEncoding - 1;
329 // FIXME: should be called getMSBEncoding
332 MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
333 SmallVectorImpl<MCFixup> &Fixups) const {
334 assert(MI.getOperand(OpNo-1).isImm());
335 assert(MI.getOperand(OpNo).isImm());
336 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups);
337 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
339 return Position + Size - 1;
342 #include "MipsGenMCCodeEmitter.inc"